From 55a25c185b62b278f200988bdabc9f3f909aa352 Mon Sep 17 00:00:00 2001 From: Jigarkumar Zala Date: Thu, 20 Aug 2020 11:43:41 -0700 Subject: [PATCH] msm: camera: csiphy: Add logic to program userspace settle count Currently settle count is programmed from hardware register data value metioned in bring up sequence. It is more reliable and suitable to program the value coming from userspace as that value is more accurate with respect to sensor specific datarate. This change add logic to accomplish that operation. CRs-Fixed: 2759031 Change-Id: I87215b206632d15e2d51d6383345d2ffa16b6b9f Signed-off-by: Jigarkumar Zala --- .../cam_csiphy/cam_csiphy_core.c | 57 ++++++++++++++++--- 1 file changed, 48 insertions(+), 9 deletions(-) diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c index 4230a12fc0c7..ad151aa817ed 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c @@ -520,6 +520,11 @@ static int cam_csiphy_cphy_data_rate_config( uint32_t lane_enable = 0; uint8_t lane_cnt = 0; uint16_t lane_assign = 0; + uint64_t intermediate_var = 0; + uint16_t settle_cnt = 0; + uint32_t reg_addr = 0, reg_data = 0, reg_param_type = 0; + uint8_t skew_cal_enable = 0; + int32_t delay = 0; if ((csiphy_device == NULL) || (csiphy_device->ctrl_reg == NULL) || @@ -538,6 +543,12 @@ static int cam_csiphy_cphy_data_rate_config( settings_table->num_data_rate_settings; lane_cnt = csiphy_device->csiphy_info[idx].lane_cnt; + intermediate_var = csiphy_device->csiphy_info[idx].settle_time; + do_div(intermediate_var, 200000000); + settle_cnt = intermediate_var; + skew_cal_enable = + csiphy_device->csiphy_info[idx].mipi_flags & SKEW_CAL_MASK; + CAM_DBG(CAM_CSIPHY, "required data rate : %llu", phy_data_rate); for (data_rate_idx = 0; data_rate_idx < num_table_entries; data_rate_idx++) { @@ -574,15 +585,43 @@ static int cam_csiphy_cphy_data_rate_config( per_lane = &drate_settings[data_rate_idx].per_lane_info[lane_idx]; for (i = 0; i < num_reg_entries; i++) { - uint32_t reg_addr = - per_lane->csiphy_data_rate_regs[i].reg_addr; - - uint32_t reg_data = - per_lane->csiphy_data_rate_regs[i].reg_data; - - CAM_DBG(CAM_CSIPHY, "writing reg : %x val : %x", - reg_addr, reg_data); - cam_io_w_mb(reg_data, csiphybase + reg_addr); + reg_addr = per_lane->csiphy_data_rate_regs[i] + .reg_addr; + reg_data = per_lane->csiphy_data_rate_regs[i] + .reg_data; + reg_param_type = + per_lane->csiphy_data_rate_regs[i] + .csiphy_param_type; + delay = per_lane->csiphy_data_rate_regs[i] + .delay; + CAM_DBG(CAM_CSIPHY, + "param_type: %d writing reg : %x val : %x delay: %dus", + reg_param_type, reg_addr, reg_data, + delay); + switch (reg_param_type) { + case CSIPHY_DEFAULT_PARAMS: + cam_io_w_mb(reg_data, + csiphybase + reg_addr); + break; + case CSIPHY_SETTLE_CNT_LOWER_BYTE: + cam_io_w_mb(settle_cnt & 0xFF, + csiphybase + reg_addr); + break; + case CSIPHY_SETTLE_CNT_HIGHER_BYTE: + cam_io_w_mb((settle_cnt >> 8) & 0xFF, + csiphybase + reg_addr); + break; + case CSIPHY_SKEW_CAL: + if (skew_cal_enable) + cam_io_w_mb(reg_data, + csiphybase + reg_addr); + break; + default: + CAM_DBG(CAM_CSIPHY, "Do Nothing"); + break; + } + if (delay > 0) + usleep_range(delay, delay + 5); } } break;