diff --git a/drivers/i2c/busses/i2c-msm-geni.c b/drivers/i2c/busses/i2c-msm-geni.c index da616c37d6c0..a71dcbbd5ec5 100644 --- a/drivers/i2c/busses/i2c-msm-geni.c +++ b/drivers/i2c/busses/i2c-msm-geni.c @@ -50,7 +50,6 @@ #define SLV_ADDR_SHFT (9) #define I2C_PACK_EN (BIT(0) | BIT(1)) -#define I2C_CORE2X_VOTE (960) #define GP_IRQ0 0 #define GP_IRQ1 1 #define GP_IRQ2 2 diff --git a/drivers/i3c/master/i3c-master-msm-geni.c b/drivers/i3c/master/i3c-master-msm-geni.c index 8c03c1851923..b69e8ea977d5 100644 --- a/drivers/i3c/master/i3c-master-msm-geni.c +++ b/drivers/i3c/master/i3c-master-msm-geni.c @@ -189,9 +189,6 @@ enum geni_i3c_err_code { #define PACKING_BYTES_PW 4 #define XFER_TIMEOUT HZ #define DFS_INDEX_MAX 7 -#define I3C_CORE2X_VOTE (960) -#define DEFAULT_BUS_WIDTH (4) -#define DEFAULT_SE_CLK (19200000) #define I3C_DDR_READ_CMD BIT(7) #define I3C_ADDR_MASK 0x7f diff --git a/drivers/interconnect/qcom/bcm-voter.c b/drivers/interconnect/qcom/bcm-voter.c index 6657b47bb638..8300b8df4560 100644 --- a/drivers/interconnect/qcom/bcm-voter.c +++ b/drivers/interconnect/qcom/bcm-voter.c @@ -76,11 +76,11 @@ static void bcm_aggregate(struct qcom_icc_bcm *bcm, bool init) agg_peak[bucket] = max(agg_peak[bucket], temp); } - temp = agg_avg[bucket] * 1000ULL; + temp = agg_avg[bucket] * bcm->vote_scale; do_div(temp, le32_to_cpu(bcm->aux_data.unit)); bcm->vote_x[bucket] = temp; - temp = agg_peak[bucket] * 1000ULL; + temp = agg_peak[bucket] * bcm->vote_scale; do_div(temp, le32_to_cpu(bcm->aux_data.unit)); bcm->vote_y[bucket] = temp; } diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c index 01be3a3138d3..b165590dcef3 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -150,6 +150,9 @@ int qcom_icc_bcm_init(struct qcom_icc_bcm *bcm, struct device *dev) INIT_LIST_HEAD(&bcm->list); INIT_LIST_HEAD(&bcm->ws_list); + if (!bcm->vote_scale) + bcm->vote_scale = 1000; + /* * Link Qnodes to their respective BCMs */ diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h index 67ef15811228..c4d255ffe365 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -89,6 +89,7 @@ struct qcom_icc_node { * @addr: address offsets used when voting to RPMH * @vote_x: aggregated threshold values, represents sum_bw when @type is bw bcm * @vote_y: aggregated threshold values, represents peak_bw when @type is bw bcm + * @vote_scale: scaling factor for vote_x and vote_y * @dirty: flag used to indicate whether the bcm needs to be committed * @keepalive: flag used to indicate whether a keepalive is required * @aux_data: auxiliary data used when calculating threshold values and @@ -104,6 +105,7 @@ struct qcom_icc_bcm { u32 addr; u64 vote_x[QCOM_ICC_NUM_BUCKETS]; u64 vote_y[QCOM_ICC_NUM_BUCKETS]; + u64 vote_scale; bool dirty; bool keepalive; struct bcm_db aux_data; diff --git a/drivers/interconnect/qcom/lahaina.c b/drivers/interconnect/qcom/lahaina.c index e9c5cf28d9c5..715cd7c8294f 100644 --- a/drivers/interconnect/qcom/lahaina.c +++ b/drivers/interconnect/qcom/lahaina.c @@ -26,431 +26,2229 @@ static DEFINE_MUTEX(probe_list_lock); static int probe_count; -DEFINE_QNODE_QOS(qhm_qspi, 2, 0, 1, 65536); -DEFINE_QNODE_QOS(qhm_qup1, 2, 0, 1, 69632); -DEFINE_QNODE_QOS(xm_sdc4, 2, 0, 1, 73728); -DEFINE_QNODE_QOS(xm_ufs_mem, 2, 0, 1, 77824); -DEFINE_QNODE_QOS(xm_usb3_0, 2, 0, 1, 81920); -DEFINE_QNODE_QOS(xm_usb3_1, 2, 0, 1, 86016); -DEFINE_QNODE_QOS(qhm_qdss_bam, 2, 0, 1, 98304); -DEFINE_QNODE_QOS(qhm_qup0, 2, 0, 1, 102400); -DEFINE_QNODE_QOS(qhm_qup2, 2, 0, 1, 106496); -DEFINE_QNODE_QOS(qxm_crypto, 2, 1, 1, 118784); -DEFINE_QNODE_QOS(qxm_ipa, 2, 1, 1, 65536); -DEFINE_QNODE_QOS(xm_pcie3_0, 2, 0, 1, 77824); -DEFINE_QNODE_QOS(xm_pcie3_1, 2, 0, 1, 81920); -DEFINE_QNODE_QOS(xm_qdss_etr, 2, 0, 1, 86016); -DEFINE_QNODE_QOS(xm_sdc2, 2, 0, 1, 90112); -DEFINE_QNODE_QOS(xm_ufs_card, 2, 0, 1, 94208); -DEFINE_QNODE_QOS(alm_gpu_tcu, 1, 0, 1, 655360); -DEFINE_QNODE_QOS(alm_sys_tcu, 6, 0, 1, 659456); -DEFINE_QNODE_QOS(qnm_cmpnoc, 0, 1, 2, 135168, 397312); -DEFINE_QNODE_QOS(qnm_gpu, 0, 0, 2, 139264, 401408); -DEFINE_QNODE_QOS(qnm_mnoc_hf, 0, 1, 2, 143360, 405504); -DEFINE_QNODE_QOS(qnm_mnoc_sf, 0, 1, 2, 147456, 409600); -DEFINE_QNODE_QOS(qnm_pcie, 2, 1, 1, 663552); -DEFINE_QNODE_QOS(qnm_snoc_gc, 0, 1, 1, 667648); -DEFINE_QNODE_QOS(qnm_snoc_sf, 0, 1, 1, 671744); -DEFINE_QNODE_QOS(qnm_camnoc_hf, 0, 1, 2, 65536, 65920); -DEFINE_QNODE_QOS(qnm_camnoc_icp, 5, 1, 1, 69632); -DEFINE_QNODE_QOS(qnm_camnoc_sf, 0, 1, 2, 73728, 73856); -DEFINE_QNODE_QOS(qnm_video0, 0, 1, 1, 81920); -DEFINE_QNODE_QOS(qnm_video1, 0, 1, 1, 82048); -DEFINE_QNODE_QOS(qnm_video_cvp, 0, 1, 1, 86016); -DEFINE_QNODE_QOS(qxm_mdp0, 0, 1, 1, 90112); -DEFINE_QNODE_QOS(qxm_mdp1, 0, 1, 1, 90240); -DEFINE_QNODE_QOS(qxm_rot, 0, 1, 1, 94208); -DEFINE_QNODE_QOS(qxm_pimem, 2, 1, 1, 45056); -DEFINE_QNODE_QOS(xm_gic, 2, 0, 1, 53248); +static struct qcom_icc_qosbox qhm_qspi_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x10000, }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; -DEFINE_QNODE(qhm_qspi, MASTER_QSPI_0, 1, 4, &qhm_qspi_qos, 1, - SLAVE_A1NOC_SNOC); -DEFINE_QNODE(qhm_qup1, MASTER_QUP_1, 1, 4, &qhm_qup1_qos, 1, - SLAVE_A1NOC_SNOC); -DEFINE_QNODE(qnm_a1noc_cfg, MASTER_A1NOC_CFG, 1, 4, NULL, 1, - SLAVE_SERVICE_A1NOC); -DEFINE_QNODE(xm_sdc4, MASTER_SDCC_4, 1, 8, &xm_sdc4_qos, 1, - SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_ufs_mem, MASTER_UFS_MEM, 1, 8, &xm_ufs_mem_qos, 1, - SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_usb3_0, MASTER_USB3_0, 1, 8, &xm_usb3_0_qos, 1, - SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_usb3_1, MASTER_USB3_1, 1, 8, &xm_usb3_1_qos, 1, - SLAVE_A1NOC_SNOC); -DEFINE_QNODE(qhm_qdss_bam, MASTER_QDSS_BAM, 1, 4, &qhm_qdss_bam_qos, 1, - SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qhm_qup0, MASTER_QUP_0, 1, 4, &qhm_qup0_qos, 1, - SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qhm_qup2, MASTER_QUP_2, 1, 4, &qhm_qup2_qos, 1, - SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qnm_a2noc_cfg, MASTER_A2NOC_CFG, 1, 4, NULL, 1, - SLAVE_SERVICE_A2NOC); -DEFINE_QNODE(qxm_crypto, MASTER_CRYPTO, 1, 8, &qxm_crypto_qos, 1, - SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_ipa, MASTER_IPA, 1, 8, &qxm_ipa_qos, 1, - SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_pcie3_0, MASTER_PCIE_0, 1, 8, &xm_pcie3_0_qos, 1, - SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(xm_pcie3_1, MASTER_PCIE_1, 1, 8, &xm_pcie3_1_qos, 1, - SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(xm_qdss_etr, MASTER_QDSS_ETR, 1, 8, &xm_qdss_etr_qos, 1, - SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_sdc2, MASTER_SDCC_2, 1, 8, &xm_sdc2_qos, 1, - SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_ufs_card, MASTER_UFS_CARD, 1, 8, &xm_ufs_card_qos, 1, - SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qup0_core_master, MASTER_QUP_CORE_0, 1, 4, NULL, 1, - SLAVE_QUP_CORE_0); -DEFINE_QNODE(qup1_core_master, MASTER_QUP_CORE_1, 1, 4, NULL, 1, - SLAVE_QUP_CORE_1); -DEFINE_QNODE(qup2_core_master, MASTER_QUP_CORE_2, 1, 4, NULL, 1, - SLAVE_QUP_CORE_2); -DEFINE_QNODE(qnm_gemnoc_cnoc, MASTER_GEM_NOC_CNOC, 1, 16, NULL, 56, - SLAVE_AHB2PHY_SOUTH, SLAVE_AHB2PHY_NORTH, - SLAVE_AOSS, SLAVE_APPSS, - SLAVE_CAMERA_CFG, SLAVE_CLK_CTL, - SLAVE_CDSP_CFG, SLAVE_RBCPR_CX_CFG, - SLAVE_RBCPR_MMCX_CFG, SLAVE_RBCPR_MX_CFG, - SLAVE_CRYPTO_0_CFG, SLAVE_CX_RDPM, - SLAVE_DCC_CFG, SLAVE_DISPLAY_CFG, - SLAVE_GFX3D_CFG, SLAVE_HWKM, - SLAVE_IMEM_CFG, SLAVE_IPA_CFG, - SLAVE_IPC_ROUTER_CFG, SLAVE_LPASS, - SLAVE_CNOC_MSS, SLAVE_MX_RDPM, - SLAVE_PCIE_0_CFG, SLAVE_PCIE_1_CFG, - SLAVE_PDM, SLAVE_PIMEM_CFG, - SLAVE_PKA_WRAPPER_CFG, SLAVE_PMU_WRAPPER_CFG, - SLAVE_QDSS_CFG, SLAVE_QSPI_0, - SLAVE_QUP_0, SLAVE_QUP_1, - SLAVE_QUP_2, SLAVE_SDCC_2, - SLAVE_SDCC_4, SLAVE_SECURITY, - SLAVE_SPSS_CFG, SLAVE_TCSR, - SLAVE_TLMM, SLAVE_UFS_CARD_CFG, - SLAVE_UFS_MEM_CFG, SLAVE_USB3_0, - SLAVE_USB3_1, SLAVE_VENUS_CFG, - SLAVE_VSENSE_CTRL_CFG, SLAVE_A1NOC_CFG, - SLAVE_A2NOC_CFG, SLAVE_DDRSS_CFG, - SLAVE_CNOC_MNOC_CFG, SLAVE_SNOC_CFG, - SLAVE_BOOT_IMEM, SLAVE_IMEM, - SLAVE_PIMEM, SLAVE_SERVICE_CNOC, - SLAVE_QDSS_STM, SLAVE_TCU); -DEFINE_QNODE(qnm_gemnoc_pcie, MASTER_GEM_NOC_PCIE_SNOC, 1, 8, NULL, 2, - SLAVE_PCIE_0, SLAVE_PCIE_1); -DEFINE_QNODE(xm_qdss_dap, MASTER_QDSS_DAP, 1, 8, NULL, 56, - SLAVE_AHB2PHY_SOUTH, SLAVE_AHB2PHY_NORTH, - SLAVE_AOSS, SLAVE_APPSS, - SLAVE_CAMERA_CFG, SLAVE_CLK_CTL, - SLAVE_CDSP_CFG, SLAVE_RBCPR_CX_CFG, - SLAVE_RBCPR_MMCX_CFG, SLAVE_RBCPR_MX_CFG, - SLAVE_CRYPTO_0_CFG, SLAVE_CX_RDPM, - SLAVE_DCC_CFG, SLAVE_DISPLAY_CFG, - SLAVE_GFX3D_CFG, SLAVE_HWKM, - SLAVE_IMEM_CFG, SLAVE_IPA_CFG, - SLAVE_IPC_ROUTER_CFG, SLAVE_LPASS, - SLAVE_CNOC_MSS, SLAVE_MX_RDPM, - SLAVE_PCIE_0_CFG, SLAVE_PCIE_1_CFG, - SLAVE_PDM, SLAVE_PIMEM_CFG, - SLAVE_PKA_WRAPPER_CFG, SLAVE_PMU_WRAPPER_CFG, - SLAVE_QDSS_CFG, SLAVE_QSPI_0, - SLAVE_QUP_0, SLAVE_QUP_1, - SLAVE_QUP_2, SLAVE_SDCC_2, - SLAVE_SDCC_4, SLAVE_SECURITY, - SLAVE_SPSS_CFG, SLAVE_TCSR, - SLAVE_TLMM, SLAVE_UFS_CARD_CFG, - SLAVE_UFS_MEM_CFG, SLAVE_USB3_0, - SLAVE_USB3_1, SLAVE_VENUS_CFG, - SLAVE_VSENSE_CTRL_CFG, SLAVE_A1NOC_CFG, - SLAVE_A2NOC_CFG, SLAVE_DDRSS_CFG, - SLAVE_CNOC_MNOC_CFG, SLAVE_SNOC_CFG, - SLAVE_BOOT_IMEM, SLAVE_IMEM, - SLAVE_PIMEM, SLAVE_SERVICE_CNOC, - SLAVE_QDSS_STM, SLAVE_TCU); -DEFINE_QNODE(qnm_cnoc_dc_noc, MASTER_CNOC_DC_NOC, 1, 4, NULL, 2, - SLAVE_LLCC_CFG, SLAVE_GEM_NOC_CFG); -DEFINE_QNODE(alm_gpu_tcu, MASTER_GPU_TCU, 1, 8, &alm_gpu_tcu_qos, 2, - SLAVE_GEM_NOC_CNOC, SLAVE_LLCC); -DEFINE_QNODE(alm_sys_tcu, MASTER_SYS_TCU, 1, 8, &alm_sys_tcu_qos, 2, - SLAVE_GEM_NOC_CNOC, SLAVE_LLCC); -DEFINE_QNODE(chm_apps, MASTER_APPSS_PROC, 2, 32, NULL, 3, - SLAVE_GEM_NOC_CNOC, SLAVE_LLCC, - SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qnm_cmpnoc, MASTER_COMPUTE_NOC, 2, 32, &qnm_cmpnoc_qos, 2, - SLAVE_GEM_NOC_CNOC, SLAVE_LLCC); -DEFINE_QNODE(qnm_gemnoc_cfg, MASTER_GEM_NOC_CFG, 1, 4, NULL, 5, - SLAVE_MSS_PROC_MS_MPU_CFG, SLAVE_MCDMA_MS_MPU_CFG, - SLAVE_SERVICE_GEM_NOC_1, SLAVE_SERVICE_GEM_NOC_2, - SLAVE_SERVICE_GEM_NOC); -DEFINE_QNODE(qnm_gpu, MASTER_GFX3D, 2, 32, &qnm_gpu_qos, 2, - SLAVE_GEM_NOC_CNOC, SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_hf, MASTER_MNOC_HF_MEM_NOC, 2, 32, &qnm_mnoc_hf_qos, 1, - SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_sf, MASTER_MNOC_SF_MEM_NOC, 2, 32, &qnm_mnoc_sf_qos, 2, - SLAVE_GEM_NOC_CNOC, SLAVE_LLCC); -DEFINE_QNODE(qnm_pcie, MASTER_ANOC_PCIE_GEM_NOC, 1, 16, &qnm_pcie_qos, 2, - SLAVE_GEM_NOC_CNOC, SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_gc, MASTER_SNOC_GC_MEM_NOC, 1, 8, &qnm_snoc_gc_qos, 1, - SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_sf, MASTER_SNOC_SF_MEM_NOC, 1, 16, &qnm_snoc_sf_qos, 3, - SLAVE_GEM_NOC_CNOC, SLAVE_LLCC, - SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qhm_config_noc, MASTER_CNOC_LPASS_AG_NOC, 1, 4, NULL, 6, - SLAVE_LPASS_CORE_CFG, SLAVE_LPASS_LPI_CFG, - SLAVE_LPASS_MPU_CFG, SLAVE_LPASS_TOP_CFG, - SLAVE_SERVICES_LPASS_AML_NOC, SLAVE_SERVICE_LPASS_AG_NOC); -DEFINE_QNODE(llcc_mc, MASTER_LLCC, 4, 4, NULL, 1, - SLAVE_EBI1); -DEFINE_QNODE(qnm_camnoc_hf, MASTER_CAMNOC_HF, 2, 32, &qnm_camnoc_hf_qos, 1, - SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qnm_camnoc_icp, MASTER_CAMNOC_ICP, 1, 8, &qnm_camnoc_icp_qos, 1, - SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_camnoc_sf, MASTER_CAMNOC_SF, 2, 32, &qnm_camnoc_sf_qos, 1, - SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_mnoc_cfg, MASTER_CNOC_MNOC_CFG, 1, 4, NULL, 1, - SLAVE_SERVICE_MNOC); -DEFINE_QNODE(qnm_video0, MASTER_VIDEO_P0, 1, 32, &qnm_video0_qos, 1, - SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_video1, MASTER_VIDEO_P1, 1, 32, &qnm_video1_qos, 1, - SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_video_cvp, MASTER_VIDEO_PROC, 1, 32, &qnm_video_cvp_qos, 1, - SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, MASTER_MDP0, 1, 32, &qxm_mdp0_qos, 1, - SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_mdp1, MASTER_MDP1, 1, 32, &qxm_mdp1_qos, 1, - SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_rot, MASTER_ROTATOR, 1, 32, &qxm_rot_qos, 1, - SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qhm_nsp_noc_config, MASTER_CDSP_NOC_CFG, 1, 4, NULL, 1, - SLAVE_SERVICE_NSP_NOC); -DEFINE_QNODE(qxm_nsp, MASTER_CDSP_PROC, 2, 32, NULL, 1, - SLAVE_CDSP_MEM_NOC); -DEFINE_QNODE(qnm_aggre1_noc, MASTER_A1NOC_SNOC, 1, 16, NULL, 1, - SLAVE_SNOC_GEM_NOC_SF); -DEFINE_QNODE(qnm_aggre2_noc, MASTER_A2NOC_SNOC, 1, 16, NULL, 1, - SLAVE_SNOC_GEM_NOC_SF); -DEFINE_QNODE(qnm_snoc_cfg, MASTER_SNOC_CFG, 1, 4, NULL, 1, - SLAVE_SERVICE_SNOC); -DEFINE_QNODE(qxm_pimem, MASTER_PIMEM, 1, 8, &qxm_pimem_qos, 1, - SLAVE_SNOC_GEM_NOC_GC); -DEFINE_QNODE(xm_gic, MASTER_GIC, 1, 8, &xm_gic_qos, 1, - SLAVE_SNOC_GEM_NOC_GC); -DEFINE_QNODE(qnm_mnoc_hf_disp, MASTER_MNOC_HF_MEM_NOC_DISP, 2, 32, NULL, 1, - SLAVE_LLCC_DISP); -DEFINE_QNODE(qnm_mnoc_sf_disp, MASTER_MNOC_SF_MEM_NOC_DISP, 2, 32, NULL, 1, - SLAVE_LLCC_DISP); -DEFINE_QNODE(llcc_mc_disp, MASTER_LLCC_DISP, 4, 4, NULL, 1, - SLAVE_EBI1_DISP); -DEFINE_QNODE(qxm_mdp0_disp, MASTER_MDP0_DISP, 1, 32, NULL, 1, - SLAVE_MNOC_HF_MEM_NOC_DISP); -DEFINE_QNODE(qxm_mdp1_disp, MASTER_MDP1_DISP, 1, 32, NULL, 1, - SLAVE_MNOC_HF_MEM_NOC_DISP); -DEFINE_QNODE(qxm_rot_disp, MASTER_ROTATOR_DISP, 1, 32, NULL, 1, - SLAVE_MNOC_SF_MEM_NOC_DISP); +static struct qcom_icc_node qhm_qspi = { + .name = "qhm_qspi", + .id = MASTER_QSPI_0, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qhm_qspi_qos, + .num_links = 1, + .links = { SLAVE_A1NOC_SNOC }, +}; -DEFINE_QNODE(qns_a1noc_snoc, SLAVE_A1NOC_SNOC, 1, 16, NULL, 1, - MASTER_A1NOC_SNOC); -DEFINE_QNODE(srvc_aggre1_noc, SLAVE_SERVICE_A1NOC, 1, 4, NULL, 0); -DEFINE_QNODE(qns_a2noc_snoc, SLAVE_A2NOC_SNOC, 1, 16, NULL, 1, - MASTER_A2NOC_SNOC); -DEFINE_QNODE(qns_pcie_mem_noc, SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, NULL, 1, - MASTER_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(srvc_aggre2_noc, SLAVE_SERVICE_A2NOC, 1, 4, NULL, 0); -DEFINE_QNODE(qup0_core_slave, SLAVE_QUP_CORE_0, 1, 4, NULL, 0); -DEFINE_QNODE(qup1_core_slave, SLAVE_QUP_CORE_1, 1, 4, NULL, 0); -DEFINE_QNODE(qup2_core_slave, SLAVE_QUP_CORE_2, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_ahb2phy0, SLAVE_AHB2PHY_SOUTH, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_ahb2phy1, SLAVE_AHB2PHY_NORTH, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_aoss, SLAVE_AOSS, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_apss, SLAVE_APPSS, 1, 8, NULL, 0); -DEFINE_QNODE(qhs_camera_cfg, SLAVE_CAMERA_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_clk_ctl, SLAVE_CLK_CTL, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_compute_cfg, SLAVE_CDSP_CFG, 1, 4, NULL, 1, - MASTER_CDSP_NOC_CFG); -DEFINE_QNODE(qhs_cpr_cx, SLAVE_RBCPR_CX_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_cpr_mmcx, SLAVE_RBCPR_MMCX_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_cpr_mx, SLAVE_RBCPR_MX_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_crypto0_cfg, SLAVE_CRYPTO_0_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_cx_rdpm, SLAVE_CX_RDPM, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_dcc_cfg, SLAVE_DCC_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_display_cfg, SLAVE_DISPLAY_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_gpuss_cfg, SLAVE_GFX3D_CFG, 1, 8, NULL, 0); -DEFINE_QNODE(qhs_hwkm, SLAVE_HWKM, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_imem_cfg, SLAVE_IMEM_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_ipa, SLAVE_IPA_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_ipc_router, SLAVE_IPC_ROUTER_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_lpass_cfg, SLAVE_LPASS, 1, 4, NULL, 1, - MASTER_CNOC_LPASS_AG_NOC); -DEFINE_QNODE(qhs_mss_cfg, SLAVE_CNOC_MSS, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_mx_rdpm, SLAVE_MX_RDPM, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_pcie0_cfg, SLAVE_PCIE_0_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_pcie1_cfg, SLAVE_PCIE_1_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_pdm, SLAVE_PDM, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_pimem_cfg, SLAVE_PIMEM_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_pka_wrapper_cfg, SLAVE_PKA_WRAPPER_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_pmu_wrapper_cfg, SLAVE_PMU_WRAPPER_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_qdss_cfg, SLAVE_QDSS_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_qspi, SLAVE_QSPI_0, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_qup0, SLAVE_QUP_0, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_qup1, SLAVE_QUP_1, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_qup2, SLAVE_QUP_2, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_sdc2, SLAVE_SDCC_2, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_sdc4, SLAVE_SDCC_4, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_security, SLAVE_SECURITY, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_spss_cfg, SLAVE_SPSS_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_tcsr, SLAVE_TCSR, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_tlmm, SLAVE_TLMM, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_ufs_card_cfg, SLAVE_UFS_CARD_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_ufs_mem_cfg, SLAVE_UFS_MEM_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_usb3_0, SLAVE_USB3_0, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_usb3_1, SLAVE_USB3_1, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_venus_cfg, SLAVE_VENUS_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SLAVE_VSENSE_CTRL_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qns_a1_noc_cfg, SLAVE_A1NOC_CFG, 1, 4, NULL, 1, - MASTER_A1NOC_CFG); -DEFINE_QNODE(qns_a2_noc_cfg, SLAVE_A2NOC_CFG, 1, 4, NULL, 1, - MASTER_A2NOC_CFG); -DEFINE_QNODE(qns_ddrss_cfg, SLAVE_DDRSS_CFG, 1, 4, NULL, 1, - MASTER_CNOC_DC_NOC); -DEFINE_QNODE(qns_mnoc_cfg, SLAVE_CNOC_MNOC_CFG, 1, 4, NULL, 1, - MASTER_CNOC_MNOC_CFG); -DEFINE_QNODE(qns_snoc_cfg, SLAVE_SNOC_CFG, 1, 4, NULL, 1, - MASTER_SNOC_CFG); -DEFINE_QNODE(qxs_boot_imem, SLAVE_BOOT_IMEM, 1, 8, NULL, 0); -DEFINE_QNODE(qxs_imem, SLAVE_IMEM, 1, 8, NULL, 0); -DEFINE_QNODE(qxs_pimem, SLAVE_PIMEM, 1, 8, NULL, 0); -DEFINE_QNODE(srvc_cnoc, SLAVE_SERVICE_CNOC, 1, 4, NULL, 0); -DEFINE_QNODE(xs_pcie_0, SLAVE_PCIE_0, 1, 8, NULL, 0); -DEFINE_QNODE(xs_pcie_1, SLAVE_PCIE_1, 1, 8, NULL, 0); -DEFINE_QNODE(xs_qdss_stm, SLAVE_QDSS_STM, 1, 4, NULL, 0); -DEFINE_QNODE(xs_sys_tcu_cfg, SLAVE_TCU, 1, 8, NULL, 0); -DEFINE_QNODE(qhs_llcc, SLAVE_LLCC_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qns_gemnoc, SLAVE_GEM_NOC_CFG, 1, 4, NULL, 1, - MASTER_GEM_NOC_CFG); -DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_modem_ms_mpu_cfg, SLAVE_MCDMA_MS_MPU_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qns_gem_noc_cnoc, SLAVE_GEM_NOC_CNOC, 1, 16, NULL, 1, - MASTER_GEM_NOC_CNOC); -DEFINE_QNODE(qns_llcc, SLAVE_LLCC, 4, 16, NULL, 1, - MASTER_LLCC); -DEFINE_QNODE(qns_pcie, SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, NULL, 1, - MASTER_GEM_NOC_PCIE_SNOC); -DEFINE_QNODE(srvc_even_gemnoc, SLAVE_SERVICE_GEM_NOC_1, 1, 4, NULL, 0); -DEFINE_QNODE(srvc_odd_gemnoc, SLAVE_SERVICE_GEM_NOC_2, 1, 4, NULL, 0); -DEFINE_QNODE(srvc_sys_gemnoc, SLAVE_SERVICE_GEM_NOC, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_lpass_core, SLAVE_LPASS_CORE_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_lpass_lpi, SLAVE_LPASS_LPI_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_lpass_mpu, SLAVE_LPASS_MPU_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(qhs_lpass_top, SLAVE_LPASS_TOP_CFG, 1, 4, NULL, 0); -DEFINE_QNODE(srvc_niu_aml_noc, SLAVE_SERVICES_LPASS_AML_NOC, 1, 4, NULL, 0); -DEFINE_QNODE(srvc_niu_lpass_agnoc, SLAVE_SERVICE_LPASS_AG_NOC, 1, 4, NULL, 0); -DEFINE_QNODE(ebi, SLAVE_EBI1, 4, 4, NULL, 0); -DEFINE_QNODE(qns_mem_noc_hf, SLAVE_MNOC_HF_MEM_NOC, 2, 32, NULL, 1, - MASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_sf, SLAVE_MNOC_SF_MEM_NOC, 2, 32, NULL, 1, - MASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SLAVE_SERVICE_MNOC, 1, 4, NULL, 0); -DEFINE_QNODE(qns_nsp_gemnoc, SLAVE_CDSP_MEM_NOC, 2, 32, NULL, 1, - MASTER_COMPUTE_NOC); -DEFINE_QNODE(service_nsp_noc, SLAVE_SERVICE_NSP_NOC, 1, 4, NULL, 0); -DEFINE_QNODE(qns_gemnoc_gc, SLAVE_SNOC_GEM_NOC_GC, 1, 8, NULL, 1, - MASTER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_gemnoc_sf, SLAVE_SNOC_GEM_NOC_SF, 1, 16, NULL, 1, - MASTER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(srvc_snoc, SLAVE_SERVICE_SNOC, 1, 4, NULL, 0); -DEFINE_QNODE(qns_llcc_disp, SLAVE_LLCC_DISP, 4, 16, NULL, 1, - MASTER_LLCC_DISP); -DEFINE_QNODE(ebi_disp, SLAVE_EBI1_DISP, 4, 4, NULL, 0); -DEFINE_QNODE(qns_mem_noc_hf_disp, SLAVE_MNOC_HF_MEM_NOC_DISP, 2, 32, NULL, 1, - MASTER_MNOC_HF_MEM_NOC_DISP); -DEFINE_QNODE(qns_mem_noc_sf_disp, SLAVE_MNOC_SF_MEM_NOC_DISP, 2, 32, NULL, 1, - MASTER_MNOC_SF_MEM_NOC_DISP); +static struct qcom_icc_qosbox qhm_qup1_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x11000, }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; -DEFINE_QBCM(bcm_acv, "ACV", false, 0, 1, - &ebi); -DEFINE_QBCM(bcm_ce0, "CE0", false, 0, 1, - &qxm_crypto); -DEFINE_QBCM(bcm_cn0, "CN0", true, 0, 2, - &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie); -DEFINE_QBCM(bcm_cn1, "CN1", false, 0, 47, - &xm_qdss_dap, &qhs_ahb2phy0, &qhs_ahb2phy1, - &qhs_aoss, &qhs_apss, &qhs_camera_cfg, - &qhs_clk_ctl, &qhs_compute_cfg, &qhs_cpr_cx, - &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, - &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_display_cfg, - &qhs_gpuss_cfg, &qhs_hwkm, &qhs_imem_cfg, - &qhs_ipa, &qhs_ipc_router, &qhs_mss_cfg, - &qhs_mx_rdpm, &qhs_pcie0_cfg, &qhs_pcie1_cfg, - &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, &qhs_pmu_wrapper_cfg, - &qhs_qdss_cfg, &qhs_qup0, &qhs_qup1, - &qhs_qup2, &qhs_security, &qhs_spss_cfg, - &qhs_tcsr, &qhs_tlmm, &qhs_ufs_card_cfg, - &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, - &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg, - &qns_a2_noc_cfg, &qns_ddrss_cfg, &qns_mnoc_cfg, - &qns_snoc_cfg, &srvc_cnoc); -DEFINE_QBCM(bcm_cn2, "CN2", false, 0, 5, - &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, - &qhs_sdc2, &qhs_sdc4); -DEFINE_QBCM(bcm_co0, "CO0", false, 0, 1, - &qns_nsp_gemnoc); -DEFINE_QBCM(bcm_co3, "CO3", false, 0, 1, - &qxm_nsp); -DEFINE_QBCM(bcm_mc0, "MC0", true, 0, 1, - &ebi); -DEFINE_QBCM(bcm_mm0, "MM0", true, 0, 1, - &qns_mem_noc_hf); -DEFINE_QBCM(bcm_mm1, "MM1", false, 0, 3, - &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1); -DEFINE_QBCM(bcm_mm4, "MM4", false, 0, 1, - &qns_mem_noc_sf); -DEFINE_QBCM(bcm_mm5, "MM5", false, 0, 6, - &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, - &qnm_video1, &qnm_video_cvp, &qxm_rot); -DEFINE_QBCM(bcm_qup0, "QUP0", false, 0, 1, - &qup0_core_slave); -DEFINE_QBCM(bcm_qup1, "QUP1", false, 0, 1, - &qup1_core_slave); -DEFINE_QBCM(bcm_qup2, "QUP2", false, 0, 1, - &qup2_core_slave); -DEFINE_QBCM(bcm_sh0, "SH0", true, 0, 1, - &qns_llcc); -DEFINE_QBCM(bcm_sh2, "SH2", false, 0, 2, - &alm_gpu_tcu, &alm_sys_tcu); -DEFINE_QBCM(bcm_sh3, "SH3", false, 0, 1, - &qnm_cmpnoc); -DEFINE_QBCM(bcm_sh4, "SH4", false, 0, 1, - &chm_apps); -DEFINE_QBCM(bcm_sn0, "SN0", true, 0, 1, - &qns_gemnoc_sf); -DEFINE_QBCM(bcm_sn2, "SN2", false, 0, 1, - &qns_gemnoc_gc); -DEFINE_QBCM(bcm_sn3, "SN3", false, 0, 1, - &qxs_pimem); -DEFINE_QBCM(bcm_sn4, "SN4", false, 0, 1, - &xs_qdss_stm); -DEFINE_QBCM(bcm_sn5, "SN5", false, 0, 1, - &xm_pcie3_0); -DEFINE_QBCM(bcm_sn6, "SN6", false, 0, 1, - &xm_pcie3_1); -DEFINE_QBCM(bcm_sn7, "SN7", false, 0, 1, - &qnm_aggre1_noc); -DEFINE_QBCM(bcm_sn8, "SN8", false, 0, 1, - &qnm_aggre2_noc); -DEFINE_QBCM(bcm_sn14, "SN14", false, 0, 1, - &qns_pcie_mem_noc); -DEFINE_QBCM(bcm_acv_disp, "ACV", false, 1, 1, - &ebi_disp); -DEFINE_QBCM(bcm_mc0_disp, "MC0", false, 1, 1, - &ebi_disp); -DEFINE_QBCM(bcm_mm0_disp, "MM0", false, 1, 1, - &qns_mem_noc_hf_disp); -DEFINE_QBCM(bcm_mm1_disp, "MM1", false, 1, 2, - &qxm_mdp0_disp, &qxm_mdp1_disp); -DEFINE_QBCM(bcm_mm4_disp, "MM4", false, 1, 1, - &qns_mem_noc_sf_disp); -DEFINE_QBCM(bcm_mm5_disp, "MM5", false, 1, 1, - &qxm_rot_disp); -DEFINE_QBCM(bcm_sh0_disp, "SH0", false, 1, 1, - &qns_llcc_disp); +static struct qcom_icc_node qhm_qup1 = { + .name = "qhm_qup1", + .id = MASTER_QUP_1, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qhm_qup1_qos, + .num_links = 1, + .links = { SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_a1noc_cfg = { + .name = "qnm_a1noc_cfg", + .id = MASTER_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_qosbox xm_sdc4_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x12000, }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + +static struct qcom_icc_node xm_sdc4 = { + .name = "xm_sdc4", + .id = MASTER_SDCC_4, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_sdc4_qos, + .num_links = 1, + .links = { SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_qosbox xm_ufs_mem_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x13000, }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .id = MASTER_UFS_MEM, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_ufs_mem_qos, + .num_links = 1, + .links = { SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_qosbox xm_usb3_0_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x14000, }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .id = MASTER_USB3_0, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_usb3_0_qos, + .num_links = 1, + .links = { SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_qosbox xm_usb3_1_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x15000, }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + +static struct qcom_icc_node xm_usb3_1 = { + .name = "xm_usb3_1", + .id = MASTER_USB3_1, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_usb3_1_qos, + .num_links = 1, + .links = { SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_qosbox qhm_qdss_bam_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x18000, }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qhm_qdss_bam_qos, + .num_links = 1, + .links = { SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_qosbox qhm_qup0_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x19000, }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + +static struct qcom_icc_node qhm_qup0 = { + .name = "qhm_qup0", + .id = MASTER_QUP_0, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qhm_qup0_qos, + .num_links = 1, + .links = { SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_qosbox qhm_qup2_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x1a000, }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + +static struct qcom_icc_node qhm_qup2 = { + .name = "qhm_qup2", + .id = MASTER_QUP_2, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qhm_qup2_qos, + .num_links = 1, + .links = { SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_a2noc_cfg = { + .name = "qnm_a2noc_cfg", + .id = MASTER_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_qosbox qxm_crypto_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x1d000, }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 1, + }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = MASTER_CRYPTO, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qxm_crypto_qos, + .num_links = 1, + .links = { SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_qosbox qxm_ipa_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x10000, }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 1, + }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .id = MASTER_IPA, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qxm_ipa_qos, + .num_links = 1, + .links = { SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_qosbox xm_pcie3_0_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x13000, }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + +static struct qcom_icc_node xm_pcie3_0 = { + .name = "xm_pcie3_0", + .id = MASTER_PCIE_0, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_pcie3_0_qos, + .num_links = 1, + .links = { SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_qosbox xm_pcie3_1_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x14000, }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + +static struct qcom_icc_node xm_pcie3_1 = { + .name = "xm_pcie3_1", + .id = MASTER_PCIE_1, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_pcie3_1_qos, + .num_links = 1, + .links = { SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_qosbox xm_qdss_etr_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x15000, }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .name = "xm_qdss_etr", + .id = MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_qdss_etr_qos, + .num_links = 1, + .links = { SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_qosbox xm_sdc2_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x16000, }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .id = MASTER_SDCC_2, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_sdc2_qos, + .num_links = 1, + .links = { SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_qosbox xm_ufs_card_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x17000, }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + +static struct qcom_icc_node xm_ufs_card = { + .name = "xm_ufs_card", + .id = MASTER_UFS_CARD, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_ufs_card_qos, + .num_links = 1, + .links = { SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qup0_core_master = { + .name = "qup0_core_master", + .id = MASTER_QUP_CORE_0, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_QUP_CORE_0 }, +}; + +static struct qcom_icc_node qup1_core_master = { + .name = "qup1_core_master", + .id = MASTER_QUP_CORE_1, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_QUP_CORE_1 }, +}; + +static struct qcom_icc_node qup2_core_master = { + .name = "qup2_core_master", + .id = MASTER_QUP_CORE_2, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_QUP_CORE_2 }, +}; + +static struct qcom_icc_node qnm_gemnoc_cnoc = { + .name = "qnm_gemnoc_cnoc", + .id = MASTER_GEM_NOC_CNOC, + .channels = 1, + .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 56, + .links = { SLAVE_AHB2PHY_SOUTH, SLAVE_AHB2PHY_NORTH, + SLAVE_AOSS, SLAVE_APPSS, + SLAVE_CAMERA_CFG, SLAVE_CLK_CTL, + SLAVE_CDSP_CFG, SLAVE_RBCPR_CX_CFG, + SLAVE_RBCPR_MMCX_CFG, SLAVE_RBCPR_MX_CFG, + SLAVE_CRYPTO_0_CFG, SLAVE_CX_RDPM, + SLAVE_DCC_CFG, SLAVE_DISPLAY_CFG, + SLAVE_GFX3D_CFG, SLAVE_HWKM, + SLAVE_IMEM_CFG, SLAVE_IPA_CFG, + SLAVE_IPC_ROUTER_CFG, SLAVE_LPASS, + SLAVE_CNOC_MSS, SLAVE_MX_RDPM, + SLAVE_PCIE_0_CFG, SLAVE_PCIE_1_CFG, + SLAVE_PDM, SLAVE_PIMEM_CFG, + SLAVE_PKA_WRAPPER_CFG, SLAVE_PMU_WRAPPER_CFG, + SLAVE_QDSS_CFG, SLAVE_QSPI_0, + SLAVE_QUP_0, SLAVE_QUP_1, + SLAVE_QUP_2, SLAVE_SDCC_2, + SLAVE_SDCC_4, SLAVE_SECURITY, + SLAVE_SPSS_CFG, SLAVE_TCSR, + SLAVE_TLMM, SLAVE_UFS_CARD_CFG, + SLAVE_UFS_MEM_CFG, SLAVE_USB3_0, + SLAVE_USB3_1, SLAVE_VENUS_CFG, + SLAVE_VSENSE_CTRL_CFG, SLAVE_A1NOC_CFG, + SLAVE_A2NOC_CFG, SLAVE_DDRSS_CFG, + SLAVE_CNOC_MNOC_CFG, SLAVE_SNOC_CFG, + SLAVE_BOOT_IMEM, SLAVE_IMEM, + SLAVE_PIMEM, SLAVE_SERVICE_CNOC, + SLAVE_QDSS_STM, SLAVE_TCU }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie = { + .name = "qnm_gemnoc_pcie", + .id = MASTER_GEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 2, + .links = { SLAVE_PCIE_0, SLAVE_PCIE_1 }, +}; + +static struct qcom_icc_node xm_qdss_dap = { + .name = "xm_qdss_dap", + .id = MASTER_QDSS_DAP, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 56, + .links = { SLAVE_AHB2PHY_SOUTH, SLAVE_AHB2PHY_NORTH, + SLAVE_AOSS, SLAVE_APPSS, + SLAVE_CAMERA_CFG, SLAVE_CLK_CTL, + SLAVE_CDSP_CFG, SLAVE_RBCPR_CX_CFG, + SLAVE_RBCPR_MMCX_CFG, SLAVE_RBCPR_MX_CFG, + SLAVE_CRYPTO_0_CFG, SLAVE_CX_RDPM, + SLAVE_DCC_CFG, SLAVE_DISPLAY_CFG, + SLAVE_GFX3D_CFG, SLAVE_HWKM, + SLAVE_IMEM_CFG, SLAVE_IPA_CFG, + SLAVE_IPC_ROUTER_CFG, SLAVE_LPASS, + SLAVE_CNOC_MSS, SLAVE_MX_RDPM, + SLAVE_PCIE_0_CFG, SLAVE_PCIE_1_CFG, + SLAVE_PDM, SLAVE_PIMEM_CFG, + SLAVE_PKA_WRAPPER_CFG, SLAVE_PMU_WRAPPER_CFG, + SLAVE_QDSS_CFG, SLAVE_QSPI_0, + SLAVE_QUP_0, SLAVE_QUP_1, + SLAVE_QUP_2, SLAVE_SDCC_2, + SLAVE_SDCC_4, SLAVE_SECURITY, + SLAVE_SPSS_CFG, SLAVE_TCSR, + SLAVE_TLMM, SLAVE_UFS_CARD_CFG, + SLAVE_UFS_MEM_CFG, SLAVE_USB3_0, + SLAVE_USB3_1, SLAVE_VENUS_CFG, + SLAVE_VSENSE_CTRL_CFG, SLAVE_A1NOC_CFG, + SLAVE_A2NOC_CFG, SLAVE_DDRSS_CFG, + SLAVE_CNOC_MNOC_CFG, SLAVE_SNOC_CFG, + SLAVE_BOOT_IMEM, SLAVE_IMEM, + SLAVE_PIMEM, SLAVE_SERVICE_CNOC, + SLAVE_QDSS_STM, SLAVE_TCU }, +}; + +static struct qcom_icc_node qnm_cnoc_dc_noc = { + .name = "qnm_cnoc_dc_noc", + .id = MASTER_CNOC_DC_NOC, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 2, + .links = { SLAVE_LLCC_CFG, SLAVE_GEM_NOC_CFG }, +}; + +static struct qcom_icc_qosbox alm_gpu_tcu_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0xa0000, }, + .config = &(struct qos_config) { + .prio = 1, + .urg_fwd = 0, + }, +}; + +static struct qcom_icc_node alm_gpu_tcu = { + .name = "alm_gpu_tcu", + .id = MASTER_GPU_TCU, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &alm_gpu_tcu_qos, + .num_links = 2, + .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC }, +}; + +static struct qcom_icc_qosbox alm_sys_tcu_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0xa1000, }, + .config = &(struct qos_config) { + .prio = 6, + .urg_fwd = 0, + }, +}; + +static struct qcom_icc_node alm_sys_tcu = { + .name = "alm_sys_tcu", + .id = MASTER_SYS_TCU, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &alm_sys_tcu_qos, + .num_links = 2, + .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC }, +}; + +static struct qcom_icc_node chm_apps = { + .name = "chm_apps", + .id = MASTER_APPSS_PROC, + .channels = 2, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 3, + .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC, + SLAVE_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_qosbox qnm_cmpnoc_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 2, + .offsets = { 0x21000, 0x61000, }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + +static struct qcom_icc_node qnm_cmpnoc = { + .name = "qnm_cmpnoc", + .id = MASTER_COMPUTE_NOC, + .channels = 2, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qnm_cmpnoc_qos, + .num_links = 2, + .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_gemnoc_cfg = { + .name = "qnm_gemnoc_cfg", + .id = MASTER_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 5, + .links = { SLAVE_MSS_PROC_MS_MPU_CFG, SLAVE_MCDMA_MS_MPU_CFG, + SLAVE_SERVICE_GEM_NOC_1, SLAVE_SERVICE_GEM_NOC_2, + SLAVE_SERVICE_GEM_NOC }, +}; + +static struct qcom_icc_qosbox qnm_gpu_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 2, + .offsets = { 0x22000, 0x62000, }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 0, + }, +}; + +static struct qcom_icc_node qnm_gpu = { + .name = "qnm_gpu", + .id = MASTER_GFX3D, + .channels = 2, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qnm_gpu_qos, + .num_links = 2, + .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC }, +}; + +static struct qcom_icc_qosbox qnm_mnoc_hf_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 2, + .offsets = { 0x23000, 0x63000, }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .id = MASTER_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qnm_mnoc_hf_qos, + .num_links = 1, + .links = { SLAVE_LLCC }, +}; + +static struct qcom_icc_qosbox qnm_mnoc_sf_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 2, + .offsets = { 0x24000, 0x64000, }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .id = MASTER_MNOC_SF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qnm_mnoc_sf_qos, + .num_links = 2, + .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC }, +}; + +static struct qcom_icc_qosbox qnm_pcie_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0xa2000, }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 1, + }, +}; + +static struct qcom_icc_node qnm_pcie = { + .name = "qnm_pcie", + .id = MASTER_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qnm_pcie_qos, + .num_links = 2, + .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC }, +}; + +static struct qcom_icc_qosbox qnm_snoc_gc_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0xa3000, }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qnm_snoc_gc_qos, + .num_links = 1, + .links = { SLAVE_LLCC }, +}; + +static struct qcom_icc_qosbox qnm_snoc_sf_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0xa4000, }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .id = MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qnm_snoc_sf_qos, + .num_links = 3, + .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC, + SLAVE_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qhm_config_noc = { + .name = "qhm_config_noc", + .id = MASTER_CNOC_LPASS_AG_NOC, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 6, + .links = { SLAVE_LPASS_CORE_CFG, SLAVE_LPASS_LPI_CFG, + SLAVE_LPASS_MPU_CFG, SLAVE_LPASS_TOP_CFG, + SLAVE_SERVICES_LPASS_AML_NOC, SLAVE_SERVICE_LPASS_AG_NOC }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = MASTER_LLCC, + .channels = 4, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_EBI1 }, +}; + +static struct qcom_icc_qosbox qnm_camnoc_hf_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 2, + .offsets = { 0x10000, 0x10180, }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + +static struct qcom_icc_node qnm_camnoc_hf = { + .name = "qnm_camnoc_hf", + .id = MASTER_CAMNOC_HF, + .channels = 2, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qnm_camnoc_hf_qos, + .num_links = 1, + .links = { SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_qosbox qnm_camnoc_icp_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x11000, }, + .config = &(struct qos_config) { + .prio = 5, + .urg_fwd = 1, + }, +}; + +static struct qcom_icc_node qnm_camnoc_icp = { + .name = "qnm_camnoc_icp", + .id = MASTER_CAMNOC_ICP, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qnm_camnoc_icp_qos, + .num_links = 1, + .links = { SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_qosbox qnm_camnoc_sf_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 2, + .offsets = { 0x12000, 0x12080, }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + +static struct qcom_icc_node qnm_camnoc_sf = { + .name = "qnm_camnoc_sf", + .id = MASTER_CAMNOC_SF, + .channels = 2, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qnm_camnoc_sf_qos, + .num_links = 1, + .links = { SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mnoc_cfg = { + .name = "qnm_mnoc_cfg", + .id = MASTER_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_qosbox qnm_video0_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x14000, }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + +static struct qcom_icc_node qnm_video0 = { + .name = "qnm_video0", + .id = MASTER_VIDEO_P0, + .channels = 1, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qnm_video0_qos, + .num_links = 1, + .links = { SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_qosbox qnm_video1_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x14080, }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + +static struct qcom_icc_node qnm_video1 = { + .name = "qnm_video1", + .id = MASTER_VIDEO_P1, + .channels = 1, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qnm_video1_qos, + .num_links = 1, + .links = { SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_qosbox qnm_video_cvp_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x15000, }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + +static struct qcom_icc_node qnm_video_cvp = { + .name = "qnm_video_cvp", + .id = MASTER_VIDEO_PROC, + .channels = 1, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qnm_video_cvp_qos, + .num_links = 1, + .links = { SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_qosbox qxm_mdp0_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x16000, }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + +static struct qcom_icc_node qxm_mdp0 = { + .name = "qxm_mdp0", + .id = MASTER_MDP0, + .channels = 1, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qxm_mdp0_qos, + .num_links = 1, + .links = { SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_qosbox qxm_mdp1_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x16080, }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + +static struct qcom_icc_node qxm_mdp1 = { + .name = "qxm_mdp1", + .id = MASTER_MDP1, + .channels = 1, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qxm_mdp1_qos, + .num_links = 1, + .links = { SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_qosbox qxm_rot_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0x17000, }, + .config = &(struct qos_config) { + .prio = 0, + .urg_fwd = 1, + }, +}; + +static struct qcom_icc_node qxm_rot = { + .name = "qxm_rot", + .id = MASTER_ROTATOR, + .channels = 1, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qxm_rot_qos, + .num_links = 1, + .links = { SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_nsp_noc_config = { + .name = "qhm_nsp_noc_config", + .id = MASTER_CDSP_NOC_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_SERVICE_NSP_NOC }, +}; + +static struct qcom_icc_node qxm_nsp = { + .name = "qxm_nsp", + .id = MASTER_CDSP_PROC, + .channels = 2, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_CDSP_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .id = MASTER_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .id = MASTER_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_snoc_cfg = { + .name = "qnm_snoc_cfg", + .id = MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_qosbox qxm_pimem_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0xb000, }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 1, + }, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .id = MASTER_PIMEM, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &qxm_pimem_qos, + .num_links = 1, + .links = { SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_qosbox xm_gic_qos = { + .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], + .num_ports = 1, + .offsets = { 0xd000, }, + .config = &(struct qos_config) { + .prio = 2, + .urg_fwd = 0, + }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .id = MASTER_GIC, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .qosbox = &xm_gic_qos, + .num_links = 1, + .links = { SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node qnm_mnoc_hf_disp = { + .name = "qnm_mnoc_hf_disp", + .id = MASTER_MNOC_HF_MEM_NOC_DISP, + .channels = 2, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_LLCC_DISP }, +}; + +static struct qcom_icc_node qnm_mnoc_sf_disp = { + .name = "qnm_mnoc_sf_disp", + .id = MASTER_MNOC_SF_MEM_NOC_DISP, + .channels = 2, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_LLCC_DISP }, +}; + +static struct qcom_icc_node llcc_mc_disp = { + .name = "llcc_mc_disp", + .id = MASTER_LLCC_DISP, + .channels = 4, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_EBI1_DISP }, +}; + +static struct qcom_icc_node qxm_mdp0_disp = { + .name = "qxm_mdp0_disp", + .id = MASTER_MDP0_DISP, + .channels = 1, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_MNOC_HF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_node qxm_mdp1_disp = { + .name = "qxm_mdp1_disp", + .id = MASTER_MDP1_DISP, + .channels = 1, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_MNOC_HF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_node qxm_rot_disp = { + .name = "qxm_rot_disp", + .id = MASTER_ROTATOR_DISP, + .channels = 1, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_MNOC_SF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .id = SLAVE_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_A1NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre1_noc = { + .name = "srvc_aggre1_noc", + .id = SLAVE_SERVICE_A1NOC, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .id = SLAVE_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qns_pcie_mem_noc = { + .name = "qns_pcie_mem_noc", + .id = SLAVE_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc = { + .name = "srvc_aggre2_noc", + .id = SLAVE_SERVICE_A2NOC, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qup0_core_slave = { + .name = "qup0_core_slave", + .id = SLAVE_QUP_CORE_0, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qup1_core_slave = { + .name = "qup1_core_slave", + .id = SLAVE_QUP_CORE_1, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qup2_core_slave = { + .name = "qup2_core_slave", + .id = SLAVE_QUP_CORE_2, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ahb2phy0 = { + .name = "qhs_ahb2phy0", + .id = SLAVE_AHB2PHY_SOUTH, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ahb2phy1 = { + .name = "qhs_ahb2phy1", + .id = SLAVE_AHB2PHY_NORTH, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SLAVE_AOSS, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .id = SLAVE_APPSS, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .id = SLAVE_CAMERA_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_compute_cfg = { + .name = "qhs_compute_cfg", + .id = SLAVE_CDSP_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_CDSP_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .id = SLAVE_RBCPR_CX_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_cpr_mmcx = { + .name = "qhs_cpr_mmcx", + .id = SLAVE_RBCPR_MMCX_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_cpr_mx = { + .name = "qhs_cpr_mx", + .id = SLAVE_RBCPR_MX_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_cx_rdpm = { + .name = "qhs_cx_rdpm", + .id = SLAVE_CX_RDPM, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_dcc_cfg = { + .name = "qhs_dcc_cfg", + .id = SLAVE_DCC_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .id = SLAVE_DISPLAY_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .id = SLAVE_GFX3D_CFG, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_hwkm = { + .name = "qhs_hwkm", + .id = SLAVE_HWKM, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ipc_router = { + .name = "qhs_ipc_router", + .id = SLAVE_IPC_ROUTER_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_lpass_cfg = { + .name = "qhs_lpass_cfg", + .id = SLAVE_LPASS, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_CNOC_LPASS_AG_NOC }, +}; + +static struct qcom_icc_node qhs_mss_cfg = { + .name = "qhs_mss_cfg", + .id = SLAVE_CNOC_MSS, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_mx_rdpm = { + .name = "qhs_mx_rdpm", + .id = SLAVE_MX_RDPM, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pcie0_cfg = { + .name = "qhs_pcie0_cfg", + .id = SLAVE_PCIE_0_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pcie1_cfg = { + .name = "qhs_pcie1_cfg", + .id = SLAVE_PCIE_1_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SLAVE_PDM, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .id = SLAVE_PIMEM_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pka_wrapper_cfg = { + .name = "qhs_pka_wrapper_cfg", + .id = SLAVE_PKA_WRAPPER_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pmu_wrapper_cfg = { + .name = "qhs_pmu_wrapper_cfg", + .id = SLAVE_PMU_WRAPPER_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qspi = { + .name = "qhs_qspi", + .id = SLAVE_QSPI_0, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qup0 = { + .name = "qhs_qup0", + .id = SLAVE_QUP_0, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qup1 = { + .name = "qhs_qup1", + .id = SLAVE_QUP_1, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qup2 = { + .name = "qhs_qup2", + .id = SLAVE_QUP_2, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .id = SLAVE_SDCC_2, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_sdc4 = { + .name = "qhs_sdc4", + .id = SLAVE_SDCC_4, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_security = { + .name = "qhs_security", + .id = SLAVE_SECURITY, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_spss_cfg = { + .name = "qhs_spss_cfg", + .id = SLAVE_SPSS_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SLAVE_TCSR, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_tlmm = { + .name = "qhs_tlmm", + .id = SLAVE_TLMM, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ufs_card_cfg = { + .name = "qhs_ufs_card_cfg", + .id = SLAVE_UFS_CARD_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .id = SLAVE_UFS_MEM_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_usb3_0 = { + .name = "qhs_usb3_0", + .id = SLAVE_USB3_0, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_usb3_1 = { + .name = "qhs_usb3_1", + .id = SLAVE_USB3_1, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .id = SLAVE_VENUS_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .id = SLAVE_VSENSE_CTRL_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qns_a1_noc_cfg = { + .name = "qns_a1_noc_cfg", + .id = SLAVE_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qns_a2_noc_cfg = { + .name = "qns_a2_noc_cfg", + .id = SLAVE_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qns_ddrss_cfg = { + .name = "qns_ddrss_cfg", + .id = SLAVE_DDRSS_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qns_mnoc_cfg = { + .name = "qns_mnoc_cfg", + .id = SLAVE_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qns_snoc_cfg = { + .name = "qns_snoc_cfg", + .id = SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qxs_boot_imem = { + .name = "qxs_boot_imem", + .id = SLAVE_BOOT_IMEM, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SLAVE_IMEM, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .id = SLAVE_PIMEM, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node srvc_cnoc = { + .name = "srvc_cnoc", + .id = SLAVE_SERVICE_CNOC, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node xs_pcie_0 = { + .name = "xs_pcie_0", + .id = SLAVE_PCIE_0, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node xs_pcie_1 = { + .name = "xs_pcie_1", + .id = SLAVE_PCIE_1, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SLAVE_TCU, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_llcc = { + .name = "qhs_llcc", + .id = SLAVE_LLCC_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qns_gemnoc = { + .name = "qns_gemnoc", + .id = SLAVE_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_GEM_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { + .name = "qhs_mdsp_ms_mpu_cfg", + .id = SLAVE_MSS_PROC_MS_MPU_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_modem_ms_mpu_cfg = { + .name = "qhs_modem_ms_mpu_cfg", + .id = SLAVE_MCDMA_MS_MPU_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qns_gem_noc_cnoc = { + .name = "qns_gem_noc_cnoc", + .id = SLAVE_GEM_NOC_CNOC, + .channels = 1, + .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_GEM_NOC_CNOC }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SLAVE_LLCC, + .channels = 4, + .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_pcie = { + .name = "qns_pcie", + .id = SLAVE_MEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_GEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node srvc_even_gemnoc = { + .name = "srvc_even_gemnoc", + .id = SLAVE_SERVICE_GEM_NOC_1, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node srvc_odd_gemnoc = { + .name = "srvc_odd_gemnoc", + .id = SLAVE_SERVICE_GEM_NOC_2, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node srvc_sys_gemnoc = { + .name = "srvc_sys_gemnoc", + .id = SLAVE_SERVICE_GEM_NOC, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_lpass_core = { + .name = "qhs_lpass_core", + .id = SLAVE_LPASS_CORE_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_lpass_lpi = { + .name = "qhs_lpass_lpi", + .id = SLAVE_LPASS_LPI_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_lpass_mpu = { + .name = "qhs_lpass_mpu", + .id = SLAVE_LPASS_MPU_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_lpass_top = { + .name = "qhs_lpass_top", + .id = SLAVE_LPASS_TOP_CFG, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node srvc_niu_aml_noc = { + .name = "srvc_niu_aml_noc", + .id = SLAVE_SERVICES_LPASS_AML_NOC, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node srvc_niu_lpass_agnoc = { + .name = "srvc_niu_lpass_agnoc", + .id = SLAVE_SERVICE_LPASS_AG_NOC, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SLAVE_EBI1, + .channels = 4, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .id = SLAVE_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_sf = { + .name = "qns_mem_noc_sf", + .id = SLAVE_MNOC_SF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .id = SLAVE_SERVICE_MNOC, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qns_nsp_gemnoc = { + .name = "qns_nsp_gemnoc", + .id = SLAVE_CDSP_MEM_NOC, + .channels = 2, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node service_nsp_noc = { + .name = "service_nsp_noc", + .id = SLAVE_SERVICE_NSP_NOC, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qns_gemnoc_gc = { + .name = "qns_gemnoc_gc", + .id = SLAVE_SNOC_GEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .id = SLAVE_SNOC_GEM_NOC_SF, + .channels = 1, + .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qns_llcc_disp = { + .name = "qns_llcc_disp", + .id = SLAVE_LLCC_DISP, + .channels = 4, + .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_LLCC_DISP }, +}; + +static struct qcom_icc_node ebi_disp = { + .name = "ebi_disp", + .id = SLAVE_EBI1_DISP, + .channels = 4, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qns_mem_noc_hf_disp = { + .name = "qns_mem_noc_hf_disp", + .id = SLAVE_MNOC_HF_MEM_NOC_DISP, + .channels = 2, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_MNOC_HF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_node qns_mem_noc_sf_disp = { + .name = "qns_mem_noc_sf_disp", + .id = SLAVE_MNOC_SF_MEM_NOC_DISP, + .channels = 2, + .buswidth = 32, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_MNOC_SF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .voter_idx = 0, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .voter_idx = 0, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .voter_idx = 0, + .keepalive = true, + .num_nodes = 2, + .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie }, +}; + +static struct qcom_icc_bcm bcm_cn1 = { + .name = "CN1", + .voter_idx = 0, + .num_nodes = 47, + .nodes = { &xm_qdss_dap, &qhs_ahb2phy0, + &qhs_ahb2phy1, &qhs_aoss, + &qhs_apss, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_compute_cfg, + &qhs_cpr_cx, &qhs_cpr_mmcx, + &qhs_cpr_mx, &qhs_crypto0_cfg, + &qhs_cx_rdpm, &qhs_dcc_cfg, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_hwkm, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_mss_cfg, &qhs_mx_rdpm, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, + &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, + &qhs_qup0, &qhs_qup1, + &qhs_qup2, &qhs_security, + &qhs_spss_cfg, &qhs_tcsr, + &qhs_tlmm, &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, &qhs_usb3_0, + &qhs_usb3_1, &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg, + &qns_a2_noc_cfg, &qns_ddrss_cfg, + &qns_mnoc_cfg, &qns_snoc_cfg, + &srvc_cnoc }, +}; + +static struct qcom_icc_bcm bcm_cn2 = { + .name = "CN2", + .voter_idx = 0, + .num_nodes = 5, + .nodes = { &qhs_lpass_cfg, &qhs_pdm, + &qhs_qspi, &qhs_sdc2, + &qhs_sdc4 }, +}; + +static struct qcom_icc_bcm bcm_co0 = { + .name = "CO0", + .voter_idx = 0, + .num_nodes = 1, + .nodes = { &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_co3 = { + .name = "CO3", + .voter_idx = 0, + .num_nodes = 1, + .nodes = { &qxm_nsp }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .voter_idx = 0, + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .voter_idx = 0, + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .voter_idx = 0, + .num_nodes = 3, + .nodes = { &qnm_camnoc_hf, &qxm_mdp0, + &qxm_mdp1 }, +}; + +static struct qcom_icc_bcm bcm_mm4 = { + .name = "MM4", + .voter_idx = 0, + .num_nodes = 1, + .nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_mm5 = { + .name = "MM5", + .voter_idx = 0, + .num_nodes = 6, + .nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf, + &qnm_video0, &qnm_video1, + &qnm_video_cvp, &qxm_rot }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .voter_idx = 0, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup0_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup1 = { + .name = "QUP1", + .voter_idx = 0, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup2 = { + .name = "QUP2", + .voter_idx = 0, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup2_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .voter_idx = 0, + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh2 = { + .name = "SH2", + .voter_idx = 0, + .num_nodes = 2, + .nodes = { &alm_gpu_tcu, &alm_sys_tcu }, +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .voter_idx = 0, + .num_nodes = 1, + .nodes = { &qnm_cmpnoc }, +}; + +static struct qcom_icc_bcm bcm_sh4 = { + .name = "SH4", + .voter_idx = 0, + .num_nodes = 1, + .nodes = { &chm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .voter_idx = 0, + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .voter_idx = 0, + .num_nodes = 1, + .nodes = { &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .voter_idx = 0, + .num_nodes = 1, + .nodes = { &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .voter_idx = 0, + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn5 = { + .name = "SN5", + .voter_idx = 0, + .num_nodes = 1, + .nodes = { &xm_pcie3_0 }, +}; + +static struct qcom_icc_bcm bcm_sn6 = { + .name = "SN6", + .voter_idx = 0, + .num_nodes = 1, + .nodes = { &xm_pcie3_1 }, +}; + +static struct qcom_icc_bcm bcm_sn7 = { + .name = "SN7", + .voter_idx = 0, + .num_nodes = 1, + .nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn8 = { + .name = "SN8", + .voter_idx = 0, + .num_nodes = 1, + .nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn14 = { + .name = "SN14", + .voter_idx = 0, + .num_nodes = 1, + .nodes = { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_acv_disp = { + .name = "ACV", + .voter_idx = 1, + .num_nodes = 1, + .nodes = { &ebi_disp }, +}; + +static struct qcom_icc_bcm bcm_mc0_disp = { + .name = "MC0", + .voter_idx = 1, + .num_nodes = 1, + .nodes = { &ebi_disp }, +}; + +static struct qcom_icc_bcm bcm_mm0_disp = { + .name = "MM0", + .voter_idx = 1, + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf_disp }, +}; + +static struct qcom_icc_bcm bcm_mm1_disp = { + .name = "MM1", + .voter_idx = 1, + .num_nodes = 2, + .nodes = { &qxm_mdp0_disp, &qxm_mdp1_disp }, +}; + +static struct qcom_icc_bcm bcm_mm4_disp = { + .name = "MM4", + .voter_idx = 1, + .num_nodes = 1, + .nodes = { &qns_mem_noc_sf_disp }, +}; + +static struct qcom_icc_bcm bcm_mm5_disp = { + .name = "MM5", + .voter_idx = 1, + .num_nodes = 1, + .nodes = { &qxm_rot_disp }, +}; + +static struct qcom_icc_bcm bcm_sh0_disp = { + .name = "SH0", + .voter_idx = 1, + .num_nodes = 1, + .nodes = { &qns_llcc_disp }, +}; static struct qcom_icc_bcm *aggre1_noc_bcms[] = { }; diff --git a/drivers/platform/msm/msm-geni-se.c b/drivers/platform/msm/msm-geni-se.c index d0df2021e9a1..3437be6ac037 100644 --- a/drivers/platform/msm/msm-geni-se.c +++ b/drivers/platform/msm/msm-geni-se.c @@ -29,8 +29,7 @@ #define GENI_SE_DMA_PTR_H(ptr) 0 #endif -/* Convert BCM threshold to actual frequency x 4 */ -#define CONV_TO_BW(x) (x*20000*4) +#define CONV_TO_BW(x) (x*4) #define NUM_LOG_PAGES 2 #define MAX_CLK_PERF_LEVEL 32 static unsigned long default_bus_bw_set[] = {0, 19200000, 50000000, diff --git a/drivers/spi/spi-msm-geni.c b/drivers/spi/spi-msm-geni.c index b58cf69bfec9..bbea33938fb3 100644 --- a/drivers/spi/spi-msm-geni.c +++ b/drivers/spi/spi-msm-geni.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ @@ -83,7 +83,6 @@ #define TIMESTAMP_AFTER BIT(3) #define POST_CMD_DELAY BIT(4) -#define SPI_CORE2X_VOTE (5000) /* GSI CONFIG0 TRE Params */ /* Flags bit fields */ #define GSI_LOOPBACK_EN (BIT(0)) diff --git a/drivers/tty/serial/msm_geni_serial.c b/drivers/tty/serial/msm_geni_serial.c index 28014d0e904b..0f43b939a4db 100644 --- a/drivers/tty/serial/msm_geni_serial.c +++ b/drivers/tty/serial/msm_geni_serial.c @@ -106,8 +106,6 @@ #define DEF_FIFO_DEPTH_WORDS (16) #define DEF_TX_WM (2) #define DEF_FIFO_WIDTH_BITS (32) -#define UART_CORE2X_VOTE (5000) -#define UART_CONSOLE_CORE2X_VOTE (960) #define WAKEBYTE_TIMEOUT_MSEC (2000) #define WAIT_XFER_MAX_ITER (2) diff --git a/include/linux/msm-geni-se.h b/include/linux/msm-geni-se.h index 40f4d672449a..9689d0c2c075 100644 --- a/include/linux/msm-geni-se.h +++ b/include/linux/msm-geni-se.h @@ -336,7 +336,6 @@ struct se_geni_rsc { #define RX_GENI_GP_IRQ_EXT (GENMASK(13, 12)) #define DEFAULT_BUS_WIDTH (4) -#define DEFAULT_SE_CLK (19200000) /* GSI TRE fields */ /* Packing fields */ @@ -366,6 +365,13 @@ if (print) { \ } \ } while (0) +/* In KHz */ +#define DEFAULT_SE_CLK 19200 +#define I2C_CORE2X_VOTE 19200 +#define I3C_CORE2X_VOTE 19200 +#define SPI_CORE2X_VOTE 100000 +#define UART_CORE2X_VOTE 100000 +#define UART_CONSOLE_CORE2X_VOTE 19200 #if IS_ENABLED(CONFIG_MSM_GENI_SE) /**