From 3a4a44c0e6bbf182492ef250a95008cf775206b9 Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Mon, 7 Sep 2020 23:15:22 +0530 Subject: [PATCH] ARM: dts: msm: update DCVS node mapping table for shima target Update DCVS node mapping table for L3 and ddr for shima target. Change-Id: Id76c399c05b23895041c41ca533083928f644ebc --- qcom/shima.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index f1ce0c989a2b..6124ff7c837e 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -2176,7 +2176,7 @@ llcc_bw_opp_table: llcc-bw-opp-table { compatible = "operating-points-v2"; BW_OPP_ENTRY( 150, 32); /* 4576 MB/s */ - BW_OPP_ENTRY( 300, 32); /* 9154 MB/s */ + BW_OPP_ENTRY( 300, 32); /* 9155 MB/s */ BW_OPP_ENTRY( 466, 32); /* 14220 MB/s */ BW_OPP_ENTRY( 600, 32); /* 18310 MB/s */ BW_OPP_ENTRY( 806, 32); /* 24596 MB/s */ @@ -2404,7 +2404,7 @@ < 691200 556800000 >, < 940800 652800000 >, < 1171200 844800000 >, - < 1516800 1065600000 >, + < 1516800 1056000000 >, < 1670400 1305600000 >, < 1804800 1420800000 >; }; @@ -2423,7 +2423,7 @@ < 1094400 556800000 >, < 1267200 806400000 >, < 1766400 1190400000 >, - < 2227200 1401600000 >, + < 2169600 1401600000 >, < 2707200 1420800000 >; }; @@ -2660,7 +2660,7 @@ qcom,ddr-type = ; qcom,core-dev-table = < 2361600 MHZ_TO_MBPS( 300, 4) >, - < 2707200 MHZ_TO_MBPS(2033, 4) >; + < 2707200 MHZ_TO_MBPS(2133, 4) >; }; ddr5-map {