mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 18:51:56 -04:00
Merge git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (43 commits) [POWERPC] Use little-endian bit from firmware ibm,pa-features property [POWERPC] Make sure smp_processor_id works very early in boot [POWERPC] U4 DART improvements [POWERPC] todc: add support for Time-Of-Day-Clock [POWERPC] Make lparcfg.c work when both iseries and pseries are selected [POWERPC] Fix idr locking in init_new_context [POWERPC] mpc7448hpc2 (taiga) board config file [POWERPC] Add tsi108 pci and platform device data register function [POWERPC] Add general support for mpc7448hpc2 (Taiga) platform [POWERPC] Correct the MAX_CONTEXT definition powerpc: minor cleanups for mpc86xx [POWERPC] Make sure we select CONFIG_NEW_LEDS if ADB_PMU_LED is set [POWERPC] Simplify the code defining the 64-bit CPU features [POWERPC] powerpc: kconfig warning fix [POWERPC] Consolidate some of kernel/misc*.S [POWERPC] Remove unused function call_with_mmu_off [POWERPC] update asm-powerpc/time.h [POWERPC] Clean up it_lp_queue.h [POWERPC] Skip the "copy down" of the kernel if it is already at zero. [POWERPC] Add the use of the firmware soft-reset-nmi to kdump. ...
This commit is contained in:
Linus Torvalds
commit
3aa590c6b7
77 changed files with 4086 additions and 1110 deletions
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@ -117,38 +117,30 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
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|||
#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
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#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
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||||
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/*
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* Add the 64-bit processor unique features in the top half of the word;
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* on 32-bit, make the names available but defined to be 0.
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*/
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#ifdef __powerpc64__
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/* Add the 64b processor unique features in the top half of the word */
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#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
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#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
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#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
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#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
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#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
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#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
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#define CPU_FTR_CTRL ASM_CONST(0x0000008000000000)
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#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
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#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
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#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
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#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000)
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#define CPU_FTR_PAUSE_ZERO ASM_CONST(0x0000200000000000)
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#define CPU_FTR_PURR ASM_CONST(0x0000400000000000)
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#define LONG_ASM_CONST(x) ASM_CONST(x)
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#else
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/* ensure on 32b processors the flags are available for compiling but
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* don't do anything */
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#define CPU_FTR_SLB ASM_CONST(0x0)
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#define CPU_FTR_16M_PAGE ASM_CONST(0x0)
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#define CPU_FTR_TLBIEL ASM_CONST(0x0)
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#define CPU_FTR_NOEXECUTE ASM_CONST(0x0)
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#define CPU_FTR_IABR ASM_CONST(0x0)
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#define CPU_FTR_MMCRA ASM_CONST(0x0)
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#define CPU_FTR_CTRL ASM_CONST(0x0)
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#define CPU_FTR_SMT ASM_CONST(0x0)
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#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0)
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#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0)
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#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0)
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#define CPU_FTR_PURR ASM_CONST(0x0)
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#define LONG_ASM_CONST(x) 0
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#endif
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#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
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#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
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#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
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#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
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#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
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#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
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#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
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#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
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#define CPU_FTR_COHERENT_ICACHE LONG_ASM_CONST(0x0000020000000000)
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#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
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#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
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#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
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#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
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#ifndef __ASSEMBLY__
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#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
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@ -29,20 +29,20 @@
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struct HvLpEvent;
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#define ITMaxLpQueues 8
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#define IT_LP_MAX_QUEUES 8
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#define NotUsed 0 // Queue will not be used by PLIC
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#define DedicatedIo 1 // Queue dedicated to IO processor specified
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#define DedicatedLp 2 // Queue dedicated to LP specified
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#define Shared 3 // Queue shared for both IO and LP
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#define IT_LP_NOT_USED 0 /* Queue will not be used by PLIC */
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#define IT_LP_DEDICATED_IO 1 /* Queue dedicated to IO processor specified */
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#define IT_LP_DEDICATED_LP 2 /* Queue dedicated to LP specified */
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#define IT_LP_SHARED 3 /* Queue shared for both IO and LP */
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#define LpEventStackSize 4096
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#define LpEventMaxSize 256
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#define LpEventAlign 64
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#define IT_LP_EVENT_STACK_SIZE 4096
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#define IT_LP_EVENT_MAX_SIZE 256
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#define IT_LP_EVENT_ALIGN 64
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struct hvlpevent_queue {
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/*
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* The xSlicCurEventPtr is the pointer to the next event stack entry
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* The hq_current_event is the pointer to the next event stack entry
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* that will become valid. The OS must peek at this entry to determine
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* if it is valid. PLIC will set the valid indicator as the very last
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* store into that entry.
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@ -52,23 +52,23 @@ struct hvlpevent_queue {
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* location again.
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*
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* If the event stack fills and there are overflow events, then PLIC
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* will set the xPlicOverflowIntPending flag in which case the OS will
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* will set the hq_overflow_pending flag in which case the OS will
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* have to fetch the additional LP events once they have drained the
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* event stack.
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*
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* The first 16-bytes are known by both the OS and PLIC. The remainder
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* of the cache line is for use by the OS.
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*/
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u8 xPlicOverflowIntPending;// 0x00 Overflow events are pending
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u8 xPlicStatus; // 0x01 DedicatedIo or DedicatedLp or NotUsed
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u16 xSlicLogicalProcIndex; // 0x02 Logical Proc Index for correlation
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u8 xPlicRsvd[12]; // 0x04
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char *xSlicCurEventPtr; // 0x10
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char *xSlicLastValidEventPtr; // 0x18
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char *xSlicEventStackPtr; // 0x20
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u8 xIndex; // 0x28 unique sequential index.
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u8 xSlicRsvd[3]; // 0x29-2b
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spinlock_t lock;
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u8 hq_overflow_pending; /* 0x00 Overflow events are pending */
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u8 hq_status; /* 0x01 DedicatedIo or DedicatedLp or NotUsed */
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u16 hq_proc_index; /* 0x02 Logical Proc Index for correlation */
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u8 hq_reserved1[12]; /* 0x04 */
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char *hq_current_event; /* 0x10 */
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char *hq_last_event; /* 0x18 */
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char *hq_event_stack; /* 0x20 */
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u8 hq_index; /* 0x28 unique sequential index. */
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u8 hq_reserved2[3]; /* 0x29-2b */
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spinlock_t hq_lock;
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};
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extern struct hvlpevent_queue hvlpevent_queue;
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@ -15,6 +15,8 @@
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#define KDUMP_TRAMPOLINE_START 0x0100
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#define KDUMP_TRAMPOLINE_END 0x3000
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#define KDUMP_MIN_TCE_ENTRIES 2048
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#else /* !CONFIG_CRASH_DUMP */
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#define PHYSICAL_START 0x0
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@ -112,9 +112,13 @@ static inline void crash_setup_regs(struct pt_regs *newregs,
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#ifdef __powerpc64__
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extern void kexec_smp_wait(void); /* get and clear naca physid, wait for
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master to copy new code to 0 */
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extern void __init kexec_setup(void);
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extern int crashing_cpu;
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extern void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *));
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extern cpumask_t cpus_in_sr;
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static inline int kexec_sr_activated(int cpu)
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{
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return cpu_isset(cpu,cpus_in_sr);
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}
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#endif /* __powerpc64 __ */
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struct kimage;
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@ -124,10 +128,13 @@ extern int default_machine_kexec_prepare(struct kimage *image);
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extern void default_machine_crash_shutdown(struct pt_regs *regs);
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extern void machine_kexec_simple(struct kimage *image);
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extern void crash_kexec_secondary(struct pt_regs *regs);
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extern int overlaps_crashkernel(unsigned long start, unsigned long size);
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extern void reserve_crashkernel(void);
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#else /* !CONFIG_KEXEC */
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static inline int kexec_sr_activated(int cpu) { return 0; }
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static inline void crash_kexec_secondary(struct pt_regs *regs) { }
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static inline int overlaps_crashkernel(unsigned long start, unsigned long size)
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{
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@ -81,6 +81,8 @@ struct machdep_calls {
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void (*tce_free)(struct iommu_table *tbl,
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long index,
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long npages);
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unsigned long (*tce_get)(struct iommu_table *tbl,
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long index);
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void (*tce_flush)(struct iommu_table *tbl);
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void (*iommu_dev_setup)(struct pci_dev *dev);
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void (*iommu_bus_setup)(struct pci_bus *bus);
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@ -238,7 +238,6 @@ extern int hash_huge_page(struct mm_struct *mm, unsigned long access,
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unsigned long ea, unsigned long vsid, int local,
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unsigned long trap);
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extern void htab_finish_init(void);
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extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
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unsigned long pstart, unsigned long mode,
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int psize);
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@ -25,8 +25,13 @@ static inline void enter_lazy_tlb(struct mm_struct *mm,
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{
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}
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/*
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* The proto-VSID space has 2^35 - 1 segments available for user mappings.
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* Each segment contains 2^28 bytes. Each context maps 2^44 bytes,
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* so we can support 2^19-1 contexts (19 == 35 + 28 - 44).
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*/
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#define NO_CONTEXT 0
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#define MAX_CONTEXT (0x100000-1)
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#define MAX_CONTEXT ((1UL << 19) - 1)
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extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
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extern void destroy_context(struct mm_struct *mm);
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|
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@ -15,15 +15,10 @@
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#ifndef __ASM_POWERPC_MPC86xx_H__
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#define __ASM_POWERPC_MPC86xx_H__
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#include <linux/config.h>
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#include <asm/mmu.h>
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#ifdef CONFIG_PPC_86xx
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#ifdef CONFIG_MPC8641_HPCN
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#include <platforms/86xx/mpc8641_hpcn.h>
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#endif
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#define _IO_BASE isa_io_base
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#define _ISA_MEM_BASE isa_mem_base
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#ifdef CONFIG_PCI
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|
|
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|||
|
|
@ -181,6 +181,9 @@ extern int rtas_set_rtc_time(struct rtc_time *rtc_time);
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extern unsigned int rtas_busy_delay_time(int status);
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extern unsigned int rtas_busy_delay(int status);
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extern int early_init_dt_scan_rtas(unsigned long node,
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const char *uname, int depth, void *data);
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extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
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|
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/* Error types logged. */
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|
|
|
|||
|
|
@ -18,8 +18,9 @@
|
|||
#include <linux/percpu.h>
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||||
|
||||
#include <asm/processor.h>
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#ifdef CONFIG_PPC64
|
||||
#ifdef CONFIG_PPC_ISERIES
|
||||
#include <asm/paca.h>
|
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#include <asm/firmware.h>
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||||
#include <asm/iseries/hv_call.h>
|
||||
#endif
|
||||
|
||||
|
|
@ -177,7 +178,8 @@ static inline void set_dec(int val)
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|||
#ifdef CONFIG_PPC_ISERIES
|
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int cur_dec;
|
||||
|
||||
if (get_lppaca()->shared_proc) {
|
||||
if (firmware_has_feature(FW_FEATURE_ISERIES) &&
|
||||
get_lppaca()->shared_proc) {
|
||||
get_lppaca()->virtual_decr = val;
|
||||
cur_dec = get_dec();
|
||||
if (cur_dec > val)
|
||||
|
|
|
|||
487
include/asm-powerpc/todc.h
Normal file
487
include/asm-powerpc/todc.h
Normal file
|
|
@ -0,0 +1,487 @@
|
|||
/*
|
||||
* Definitions for the M48Txx and mc146818 series of Time of day/Real Time
|
||||
* Clock chips.
|
||||
*
|
||||
* Author: Mark A. Greer <mgreer@mvista.com>
|
||||
*
|
||||
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Support for the M48T37/M48T59/.../mc146818 Real Time Clock chips.
|
||||
* Purpose is to make one generic file that handles all of these chips instead
|
||||
* of every platform implementing the same code over & over again.
|
||||
*/
|
||||
|
||||
#ifndef __PPC_KERNEL_TODC_H
|
||||
#define __PPC_KERNEL_TODC_H
|
||||
|
||||
typedef struct {
|
||||
uint rtc_type; /* your particular chip */
|
||||
|
||||
/*
|
||||
* Following are the addresses of the AS0, AS1, and DATA registers
|
||||
* of these chips. Note that these are board-specific.
|
||||
*/
|
||||
unsigned int nvram_as0;
|
||||
unsigned int nvram_as1;
|
||||
unsigned int nvram_data;
|
||||
|
||||
/*
|
||||
* Define bits to stop external set of regs from changing so
|
||||
* the chip can be read/written reliably.
|
||||
*/
|
||||
unsigned char enable_read;
|
||||
unsigned char enable_write;
|
||||
|
||||
/*
|
||||
* Following is the number of AS0 address bits. This is normally
|
||||
* 8 but some bad hardware routes address lines incorrectly.
|
||||
*/
|
||||
int as0_bits;
|
||||
|
||||
int nvram_size; /* Size of NVRAM on chip */
|
||||
int sw_flags; /* Software control flags */
|
||||
|
||||
/* Following are the register offsets for the particular chip */
|
||||
int year;
|
||||
int month;
|
||||
int day_of_month;
|
||||
int day_of_week;
|
||||
int hours;
|
||||
int minutes;
|
||||
int seconds;
|
||||
int control_b;
|
||||
int control_a;
|
||||
int watchdog;
|
||||
int interrupts;
|
||||
int alarm_date;
|
||||
int alarm_hour;
|
||||
int alarm_minutes;
|
||||
int alarm_seconds;
|
||||
int century;
|
||||
int flags;
|
||||
|
||||
/*
|
||||
* Some RTC chips have their NVRAM buried behind a addr/data pair of
|
||||
* regs on the first level/clock registers. The following fields
|
||||
* are the addresses for those addr/data regs.
|
||||
*/
|
||||
int nvram_addr_reg;
|
||||
int nvram_data_reg;
|
||||
} todc_info_t;
|
||||
|
||||
/*
|
||||
* Define the types of TODC/RTC variants that are supported in
|
||||
* arch/ppc/kernel/todc_time.c
|
||||
* Make a new one of these for any chip somehow differs from what's already
|
||||
* defined. That way, if you ever need to put in code to touch those
|
||||
* bits/registers in todc_time.c, you can put it inside an
|
||||
* 'if (todc_info->rtc_type == TODC_TYPE_XXX)' so you won't break
|
||||
* anyone else.
|
||||
*/
|
||||
#define TODC_TYPE_MK48T35 1
|
||||
#define TODC_TYPE_MK48T37 2
|
||||
#define TODC_TYPE_MK48T59 3
|
||||
#define TODC_TYPE_DS1693 4 /* Dallas DS1693 RTC */
|
||||
#define TODC_TYPE_DS1743 5 /* Dallas DS1743 RTC */
|
||||
#define TODC_TYPE_DS1746 6 /* Dallas DS1746 RTC */
|
||||
#define TODC_TYPE_DS1747 7 /* Dallas DS1747 RTC */
|
||||
#define TODC_TYPE_DS1501 8 /* Dallas DS1501 RTC */
|
||||
#define TODC_TYPE_DS1643 9 /* Dallas DS1643 RTC */
|
||||
#define TODC_TYPE_PC97307 10 /* PC97307 internal RTC */
|
||||
#define TODC_TYPE_DS1557 11 /* Dallas DS1557 RTC */
|
||||
#define TODC_TYPE_DS17285 12 /* Dallas DS17285 RTC */
|
||||
#define TODC_TYPE_DS1553 13 /* Dallas DS1553 RTC */
|
||||
#define TODC_TYPE_MC146818 100 /* Leave room for m48txx's */
|
||||
|
||||
/*
|
||||
* Bit to clear/set to enable reads/writes to the chip
|
||||
*/
|
||||
#define TODC_MK48TXX_CNTL_A_R 0x40
|
||||
#define TODC_MK48TXX_CNTL_A_W 0x80
|
||||
#define TODC_MK48TXX_DAY_CB 0x80
|
||||
|
||||
#define TODC_DS1501_CNTL_B_TE 0x80
|
||||
|
||||
/*
|
||||
* Define flag bits used by todc routines.
|
||||
*/
|
||||
#define TODC_FLAG_2_LEVEL_NVRAM 0x00000001
|
||||
|
||||
/*
|
||||
* Define the values for the various RTC's that should to into the todc_info
|
||||
* table.
|
||||
* Note: The XXX_NVRAM_SIZE, XXX_NVRAM_ADDR_REG, and XXX_NVRAM_DATA_REG only
|
||||
* matter if XXX_SW_FLAGS has TODC_FLAG_2_LEVEL_NVRAM set.
|
||||
*/
|
||||
#define TODC_TYPE_MK48T35_NVRAM_SIZE 0x7ff8
|
||||
#define TODC_TYPE_MK48T35_SW_FLAGS 0
|
||||
#define TODC_TYPE_MK48T35_YEAR 0x7fff
|
||||
#define TODC_TYPE_MK48T35_MONTH 0x7ffe
|
||||
#define TODC_TYPE_MK48T35_DOM 0x7ffd /* Day of Month */
|
||||
#define TODC_TYPE_MK48T35_DOW 0x7ffc /* Day of Week */
|
||||
#define TODC_TYPE_MK48T35_HOURS 0x7ffb
|
||||
#define TODC_TYPE_MK48T35_MINUTES 0x7ffa
|
||||
#define TODC_TYPE_MK48T35_SECONDS 0x7ff9
|
||||
#define TODC_TYPE_MK48T35_CNTL_B 0x7ff9
|
||||
#define TODC_TYPE_MK48T35_CNTL_A 0x7ff8
|
||||
#define TODC_TYPE_MK48T35_WATCHDOG 0x0000
|
||||
#define TODC_TYPE_MK48T35_INTERRUPTS 0x0000
|
||||
#define TODC_TYPE_MK48T35_ALARM_DATE 0x0000
|
||||
#define TODC_TYPE_MK48T35_ALARM_HOUR 0x0000
|
||||
#define TODC_TYPE_MK48T35_ALARM_MINUTES 0x0000
|
||||
#define TODC_TYPE_MK48T35_ALARM_SECONDS 0x0000
|
||||
#define TODC_TYPE_MK48T35_CENTURY 0x0000
|
||||
#define TODC_TYPE_MK48T35_FLAGS 0x0000
|
||||
#define TODC_TYPE_MK48T35_NVRAM_ADDR_REG 0
|
||||
#define TODC_TYPE_MK48T35_NVRAM_DATA_REG 0
|
||||
|
||||
#define TODC_TYPE_MK48T37_NVRAM_SIZE 0x7ff0
|
||||
#define TODC_TYPE_MK48T37_SW_FLAGS 0
|
||||
#define TODC_TYPE_MK48T37_YEAR 0x7fff
|
||||
#define TODC_TYPE_MK48T37_MONTH 0x7ffe
|
||||
#define TODC_TYPE_MK48T37_DOM 0x7ffd /* Day of Month */
|
||||
#define TODC_TYPE_MK48T37_DOW 0x7ffc /* Day of Week */
|
||||
#define TODC_TYPE_MK48T37_HOURS 0x7ffb
|
||||
#define TODC_TYPE_MK48T37_MINUTES 0x7ffa
|
||||
#define TODC_TYPE_MK48T37_SECONDS 0x7ff9
|
||||
#define TODC_TYPE_MK48T37_CNTL_B 0x7ff9
|
||||
#define TODC_TYPE_MK48T37_CNTL_A 0x7ff8
|
||||
#define TODC_TYPE_MK48T37_WATCHDOG 0x7ff7
|
||||
#define TODC_TYPE_MK48T37_INTERRUPTS 0x7ff6
|
||||
#define TODC_TYPE_MK48T37_ALARM_DATE 0x7ff5
|
||||
#define TODC_TYPE_MK48T37_ALARM_HOUR 0x7ff4
|
||||
#define TODC_TYPE_MK48T37_ALARM_MINUTES 0x7ff3
|
||||
#define TODC_TYPE_MK48T37_ALARM_SECONDS 0x7ff2
|
||||
#define TODC_TYPE_MK48T37_CENTURY 0x7ff1
|
||||
#define TODC_TYPE_MK48T37_FLAGS 0x7ff0
|
||||
#define TODC_TYPE_MK48T37_NVRAM_ADDR_REG 0
|
||||
#define TODC_TYPE_MK48T37_NVRAM_DATA_REG 0
|
||||
|
||||
#define TODC_TYPE_MK48T59_NVRAM_SIZE 0x1ff0
|
||||
#define TODC_TYPE_MK48T59_SW_FLAGS 0
|
||||
#define TODC_TYPE_MK48T59_YEAR 0x1fff
|
||||
#define TODC_TYPE_MK48T59_MONTH 0x1ffe
|
||||
#define TODC_TYPE_MK48T59_DOM 0x1ffd /* Day of Month */
|
||||
#define TODC_TYPE_MK48T59_DOW 0x1ffc /* Day of Week */
|
||||
#define TODC_TYPE_MK48T59_HOURS 0x1ffb
|
||||
#define TODC_TYPE_MK48T59_MINUTES 0x1ffa
|
||||
#define TODC_TYPE_MK48T59_SECONDS 0x1ff9
|
||||
#define TODC_TYPE_MK48T59_CNTL_B 0x1ff9
|
||||
#define TODC_TYPE_MK48T59_CNTL_A 0x1ff8
|
||||
#define TODC_TYPE_MK48T59_WATCHDOG 0x1fff
|
||||
#define TODC_TYPE_MK48T59_INTERRUPTS 0x1fff
|
||||
#define TODC_TYPE_MK48T59_ALARM_DATE 0x1fff
|
||||
#define TODC_TYPE_MK48T59_ALARM_HOUR 0x1fff
|
||||
#define TODC_TYPE_MK48T59_ALARM_MINUTES 0x1fff
|
||||
#define TODC_TYPE_MK48T59_ALARM_SECONDS 0x1fff
|
||||
#define TODC_TYPE_MK48T59_CENTURY 0x1fff
|
||||
#define TODC_TYPE_MK48T59_FLAGS 0x1fff
|
||||
#define TODC_TYPE_MK48T59_NVRAM_ADDR_REG 0
|
||||
#define TODC_TYPE_MK48T59_NVRAM_DATA_REG 0
|
||||
|
||||
#define TODC_TYPE_DS1501_NVRAM_SIZE 0x100
|
||||
#define TODC_TYPE_DS1501_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM
|
||||
#define TODC_TYPE_DS1501_YEAR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x06)
|
||||
#define TODC_TYPE_DS1501_MONTH (TODC_TYPE_DS1501_NVRAM_SIZE + 0x05)
|
||||
#define TODC_TYPE_DS1501_DOM (TODC_TYPE_DS1501_NVRAM_SIZE + 0x04)
|
||||
#define TODC_TYPE_DS1501_DOW (TODC_TYPE_DS1501_NVRAM_SIZE + 0x03)
|
||||
#define TODC_TYPE_DS1501_HOURS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x02)
|
||||
#define TODC_TYPE_DS1501_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x01)
|
||||
#define TODC_TYPE_DS1501_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x00)
|
||||
#define TODC_TYPE_DS1501_CNTL_B (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
|
||||
#define TODC_TYPE_DS1501_CNTL_A (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
|
||||
#define TODC_TYPE_DS1501_WATCHDOG (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
|
||||
#define TODC_TYPE_DS1501_INTERRUPTS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
|
||||
#define TODC_TYPE_DS1501_ALARM_DATE (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0b)
|
||||
#define TODC_TYPE_DS1501_ALARM_HOUR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0a)
|
||||
#define TODC_TYPE_DS1501_ALARM_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x09)
|
||||
#define TODC_TYPE_DS1501_ALARM_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x08)
|
||||
#define TODC_TYPE_DS1501_CENTURY (TODC_TYPE_DS1501_NVRAM_SIZE + 0x07)
|
||||
#define TODC_TYPE_DS1501_FLAGS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
|
||||
#define TODC_TYPE_DS1501_NVRAM_ADDR_REG 0x10
|
||||
#define TODC_TYPE_DS1501_NVRAM_DATA_REG 0x13
|
||||
|
||||
#define TODC_TYPE_DS1553_NVRAM_SIZE 0x1ff0
|
||||
#define TODC_TYPE_DS1553_SW_FLAGS 0
|
||||
#define TODC_TYPE_DS1553_YEAR 0x1fff
|
||||
#define TODC_TYPE_DS1553_MONTH 0x1ffe
|
||||
#define TODC_TYPE_DS1553_DOM 0x1ffd /* Day of Month */
|
||||
#define TODC_TYPE_DS1553_DOW 0x1ffc /* Day of Week */
|
||||
#define TODC_TYPE_DS1553_HOURS 0x1ffb
|
||||
#define TODC_TYPE_DS1553_MINUTES 0x1ffa
|
||||
#define TODC_TYPE_DS1553_SECONDS 0x1ff9
|
||||
#define TODC_TYPE_DS1553_CNTL_B 0x1ff9
|
||||
#define TODC_TYPE_DS1553_CNTL_A 0x1ff8 /* control_a R/W regs */
|
||||
#define TODC_TYPE_DS1553_WATCHDOG 0x1ff7
|
||||
#define TODC_TYPE_DS1553_INTERRUPTS 0x1ff6
|
||||
#define TODC_TYPE_DS1553_ALARM_DATE 0x1ff5
|
||||
#define TODC_TYPE_DS1553_ALARM_HOUR 0x1ff4
|
||||
#define TODC_TYPE_DS1553_ALARM_MINUTES 0x1ff3
|
||||
#define TODC_TYPE_DS1553_ALARM_SECONDS 0x1ff2
|
||||
#define TODC_TYPE_DS1553_CENTURY 0x1ff8
|
||||
#define TODC_TYPE_DS1553_FLAGS 0x1ff0
|
||||
#define TODC_TYPE_DS1553_NVRAM_ADDR_REG 0
|
||||
#define TODC_TYPE_DS1553_NVRAM_DATA_REG 0
|
||||
|
||||
#define TODC_TYPE_DS1557_NVRAM_SIZE 0x7fff0
|
||||
#define TODC_TYPE_DS1557_SW_FLAGS 0
|
||||
#define TODC_TYPE_DS1557_YEAR 0x7ffff
|
||||
#define TODC_TYPE_DS1557_MONTH 0x7fffe
|
||||
#define TODC_TYPE_DS1557_DOM 0x7fffd /* Day of Month */
|
||||
#define TODC_TYPE_DS1557_DOW 0x7fffc /* Day of Week */
|
||||
#define TODC_TYPE_DS1557_HOURS 0x7fffb
|
||||
#define TODC_TYPE_DS1557_MINUTES 0x7fffa
|
||||
#define TODC_TYPE_DS1557_SECONDS 0x7fff9
|
||||
#define TODC_TYPE_DS1557_CNTL_B 0x7fff9
|
||||
#define TODC_TYPE_DS1557_CNTL_A 0x7fff8 /* control_a R/W regs */
|
||||
#define TODC_TYPE_DS1557_WATCHDOG 0x7fff7
|
||||
#define TODC_TYPE_DS1557_INTERRUPTS 0x7fff6
|
||||
#define TODC_TYPE_DS1557_ALARM_DATE 0x7fff5
|
||||
#define TODC_TYPE_DS1557_ALARM_HOUR 0x7fff4
|
||||
#define TODC_TYPE_DS1557_ALARM_MINUTES 0x7fff3
|
||||
#define TODC_TYPE_DS1557_ALARM_SECONDS 0x7fff2
|
||||
#define TODC_TYPE_DS1557_CENTURY 0x7fff8
|
||||
#define TODC_TYPE_DS1557_FLAGS 0x7fff0
|
||||
#define TODC_TYPE_DS1557_NVRAM_ADDR_REG 0
|
||||
#define TODC_TYPE_DS1557_NVRAM_DATA_REG 0
|
||||
|
||||
#define TODC_TYPE_DS1643_NVRAM_SIZE 0x1ff8
|
||||
#define TODC_TYPE_DS1643_SW_FLAGS 0
|
||||
#define TODC_TYPE_DS1643_YEAR 0x1fff
|
||||
#define TODC_TYPE_DS1643_MONTH 0x1ffe
|
||||
#define TODC_TYPE_DS1643_DOM 0x1ffd /* Day of Month */
|
||||
#define TODC_TYPE_DS1643_DOW 0x1ffc /* Day of Week */
|
||||
#define TODC_TYPE_DS1643_HOURS 0x1ffb
|
||||
#define TODC_TYPE_DS1643_MINUTES 0x1ffa
|
||||
#define TODC_TYPE_DS1643_SECONDS 0x1ff9
|
||||
#define TODC_TYPE_DS1643_CNTL_B 0x1ff9
|
||||
#define TODC_TYPE_DS1643_CNTL_A 0x1ff8 /* control_a R/W regs */
|
||||
#define TODC_TYPE_DS1643_WATCHDOG 0x1fff
|
||||
#define TODC_TYPE_DS1643_INTERRUPTS 0x1fff
|
||||
#define TODC_TYPE_DS1643_ALARM_DATE 0x1fff
|
||||
#define TODC_TYPE_DS1643_ALARM_HOUR 0x1fff
|
||||
#define TODC_TYPE_DS1643_ALARM_MINUTES 0x1fff
|
||||
#define TODC_TYPE_DS1643_ALARM_SECONDS 0x1fff
|
||||
#define TODC_TYPE_DS1643_CENTURY 0x1ff8
|
||||
#define TODC_TYPE_DS1643_FLAGS 0x1fff
|
||||
#define TODC_TYPE_DS1643_NVRAM_ADDR_REG 0
|
||||
#define TODC_TYPE_DS1643_NVRAM_DATA_REG 0
|
||||
|
||||
#define TODC_TYPE_DS1693_NVRAM_SIZE 0 /* Not handled yet */
|
||||
#define TODC_TYPE_DS1693_SW_FLAGS 0
|
||||
#define TODC_TYPE_DS1693_YEAR 0x09
|
||||
#define TODC_TYPE_DS1693_MONTH 0x08
|
||||
#define TODC_TYPE_DS1693_DOM 0x07 /* Day of Month */
|
||||
#define TODC_TYPE_DS1693_DOW 0x06 /* Day of Week */
|
||||
#define TODC_TYPE_DS1693_HOURS 0x04
|
||||
#define TODC_TYPE_DS1693_MINUTES 0x02
|
||||
#define TODC_TYPE_DS1693_SECONDS 0x00
|
||||
#define TODC_TYPE_DS1693_CNTL_B 0x0b
|
||||
#define TODC_TYPE_DS1693_CNTL_A 0x0a
|
||||
#define TODC_TYPE_DS1693_WATCHDOG 0xff
|
||||
#define TODC_TYPE_DS1693_INTERRUPTS 0xff
|
||||
#define TODC_TYPE_DS1693_ALARM_DATE 0x49
|
||||
#define TODC_TYPE_DS1693_ALARM_HOUR 0x05
|
||||
#define TODC_TYPE_DS1693_ALARM_MINUTES 0x03
|
||||
#define TODC_TYPE_DS1693_ALARM_SECONDS 0x01
|
||||
#define TODC_TYPE_DS1693_CENTURY 0x48
|
||||
#define TODC_TYPE_DS1693_FLAGS 0xff
|
||||
#define TODC_TYPE_DS1693_NVRAM_ADDR_REG 0
|
||||
#define TODC_TYPE_DS1693_NVRAM_DATA_REG 0
|
||||
|
||||
#define TODC_TYPE_DS1743_NVRAM_SIZE 0x1ff8
|
||||
#define TODC_TYPE_DS1743_SW_FLAGS 0
|
||||
#define TODC_TYPE_DS1743_YEAR 0x1fff
|
||||
#define TODC_TYPE_DS1743_MONTH 0x1ffe
|
||||
#define TODC_TYPE_DS1743_DOM 0x1ffd /* Day of Month */
|
||||
#define TODC_TYPE_DS1743_DOW 0x1ffc /* Day of Week */
|
||||
#define TODC_TYPE_DS1743_HOURS 0x1ffb
|
||||
#define TODC_TYPE_DS1743_MINUTES 0x1ffa
|
||||
#define TODC_TYPE_DS1743_SECONDS 0x1ff9
|
||||
#define TODC_TYPE_DS1743_CNTL_B 0x1ff9
|
||||
#define TODC_TYPE_DS1743_CNTL_A 0x1ff8 /* control_a R/W regs */
|
||||
#define TODC_TYPE_DS1743_WATCHDOG 0x1fff
|
||||
#define TODC_TYPE_DS1743_INTERRUPTS 0x1fff
|
||||
#define TODC_TYPE_DS1743_ALARM_DATE 0x1fff
|
||||
#define TODC_TYPE_DS1743_ALARM_HOUR 0x1fff
|
||||
#define TODC_TYPE_DS1743_ALARM_MINUTES 0x1fff
|
||||
#define TODC_TYPE_DS1743_ALARM_SECONDS 0x1fff
|
||||
#define TODC_TYPE_DS1743_CENTURY 0x1ff8
|
||||
#define TODC_TYPE_DS1743_FLAGS 0x1fff
|
||||
#define TODC_TYPE_DS1743_NVRAM_ADDR_REG 0
|
||||
#define TODC_TYPE_DS1743_NVRAM_DATA_REG 0
|
||||
|
||||
#define TODC_TYPE_DS1746_NVRAM_SIZE 0x1fff8
|
||||
#define TODC_TYPE_DS1746_SW_FLAGS 0
|
||||
#define TODC_TYPE_DS1746_YEAR 0x1ffff
|
||||
#define TODC_TYPE_DS1746_MONTH 0x1fffe
|
||||
#define TODC_TYPE_DS1746_DOM 0x1fffd /* Day of Month */
|
||||
#define TODC_TYPE_DS1746_DOW 0x1fffc /* Day of Week */
|
||||
#define TODC_TYPE_DS1746_HOURS 0x1fffb
|
||||
#define TODC_TYPE_DS1746_MINUTES 0x1fffa
|
||||
#define TODC_TYPE_DS1746_SECONDS 0x1fff9
|
||||
#define TODC_TYPE_DS1746_CNTL_B 0x1fff9
|
||||
#define TODC_TYPE_DS1746_CNTL_A 0x1fff8 /* control_a R/W regs */
|
||||
#define TODC_TYPE_DS1746_WATCHDOG 0x00000
|
||||
#define TODC_TYPE_DS1746_INTERRUPTS 0x00000
|
||||
#define TODC_TYPE_DS1746_ALARM_DATE 0x00000
|
||||
#define TODC_TYPE_DS1746_ALARM_HOUR 0x00000
|
||||
#define TODC_TYPE_DS1746_ALARM_MINUTES 0x00000
|
||||
#define TODC_TYPE_DS1746_ALARM_SECONDS 0x00000
|
||||
#define TODC_TYPE_DS1746_CENTURY 0x00000
|
||||
#define TODC_TYPE_DS1746_FLAGS 0x00000
|
||||
#define TODC_TYPE_DS1746_NVRAM_ADDR_REG 0
|
||||
#define TODC_TYPE_DS1746_NVRAM_DATA_REG 0
|
||||
|
||||
#define TODC_TYPE_DS1747_NVRAM_SIZE 0x7fff8
|
||||
#define TODC_TYPE_DS1747_SW_FLAGS 0
|
||||
#define TODC_TYPE_DS1747_YEAR 0x7ffff
|
||||
#define TODC_TYPE_DS1747_MONTH 0x7fffe
|
||||
#define TODC_TYPE_DS1747_DOM 0x7fffd /* Day of Month */
|
||||
#define TODC_TYPE_DS1747_DOW 0x7fffc /* Day of Week */
|
||||
#define TODC_TYPE_DS1747_HOURS 0x7fffb
|
||||
#define TODC_TYPE_DS1747_MINUTES 0x7fffa
|
||||
#define TODC_TYPE_DS1747_SECONDS 0x7fff9
|
||||
#define TODC_TYPE_DS1747_CNTL_B 0x7fff9
|
||||
#define TODC_TYPE_DS1747_CNTL_A 0x7fff8 /* control_a R/W regs */
|
||||
#define TODC_TYPE_DS1747_WATCHDOG 0x00000
|
||||
#define TODC_TYPE_DS1747_INTERRUPTS 0x00000
|
||||
#define TODC_TYPE_DS1747_ALARM_DATE 0x00000
|
||||
#define TODC_TYPE_DS1747_ALARM_HOUR 0x00000
|
||||
#define TODC_TYPE_DS1747_ALARM_MINUTES 0x00000
|
||||
#define TODC_TYPE_DS1747_ALARM_SECONDS 0x00000
|
||||
#define TODC_TYPE_DS1747_CENTURY 0x00000
|
||||
#define TODC_TYPE_DS1747_FLAGS 0x00000
|
||||
#define TODC_TYPE_DS1747_NVRAM_ADDR_REG 0
|
||||
#define TODC_TYPE_DS1747_NVRAM_DATA_REG 0
|
||||
|
||||
#define TODC_TYPE_DS17285_NVRAM_SIZE (0x1000-0x80) /* 4Kx8 NVRAM (minus RTC regs) */
|
||||
#define TODC_TYPE_DS17285_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM
|
||||
#define TODC_TYPE_DS17285_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x00)
|
||||
#define TODC_TYPE_DS17285_ALARM_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x01)
|
||||
#define TODC_TYPE_DS17285_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x02)
|
||||
#define TODC_TYPE_DS17285_ALARM_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x03)
|
||||
#define TODC_TYPE_DS17285_HOURS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x04)
|
||||
#define TODC_TYPE_DS17285_ALARM_HOUR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x05)
|
||||
#define TODC_TYPE_DS17285_DOW (TODC_TYPE_DS17285_NVRAM_SIZE + 0x06)
|
||||
#define TODC_TYPE_DS17285_DOM (TODC_TYPE_DS17285_NVRAM_SIZE + 0x07)
|
||||
#define TODC_TYPE_DS17285_MONTH (TODC_TYPE_DS17285_NVRAM_SIZE + 0x08)
|
||||
#define TODC_TYPE_DS17285_YEAR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x09)
|
||||
#define TODC_TYPE_DS17285_CNTL_A (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0A)
|
||||
#define TODC_TYPE_DS17285_CNTL_B (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0B)
|
||||
#define TODC_TYPE_DS17285_CNTL_C (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0C)
|
||||
#define TODC_TYPE_DS17285_CNTL_D (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0D)
|
||||
#define TODC_TYPE_DS17285_WATCHDOG 0
|
||||
#define TODC_TYPE_DS17285_INTERRUPTS 0
|
||||
#define TODC_TYPE_DS17285_ALARM_DATE 0
|
||||
#define TODC_TYPE_DS17285_CENTURY 0
|
||||
#define TODC_TYPE_DS17285_FLAGS 0
|
||||
#define TODC_TYPE_DS17285_NVRAM_ADDR_REG 0x50
|
||||
#define TODC_TYPE_DS17285_NVRAM_DATA_REG 0x53
|
||||
|
||||
#define TODC_TYPE_MC146818_NVRAM_SIZE 0 /* XXXX */
|
||||
#define TODC_TYPE_MC146818_SW_FLAGS 0
|
||||
#define TODC_TYPE_MC146818_YEAR 0x09
|
||||
#define TODC_TYPE_MC146818_MONTH 0x08
|
||||
#define TODC_TYPE_MC146818_DOM 0x07 /* Day of Month */
|
||||
#define TODC_TYPE_MC146818_DOW 0x06 /* Day of Week */
|
||||
#define TODC_TYPE_MC146818_HOURS 0x04
|
||||
#define TODC_TYPE_MC146818_MINUTES 0x02
|
||||
#define TODC_TYPE_MC146818_SECONDS 0x00
|
||||
#define TODC_TYPE_MC146818_CNTL_B 0x0a
|
||||
#define TODC_TYPE_MC146818_CNTL_A 0x0b /* control_a R/W regs */
|
||||
#define TODC_TYPE_MC146818_WATCHDOG 0
|
||||
#define TODC_TYPE_MC146818_INTERRUPTS 0x0c
|
||||
#define TODC_TYPE_MC146818_ALARM_DATE 0xff
|
||||
#define TODC_TYPE_MC146818_ALARM_HOUR 0x05
|
||||
#define TODC_TYPE_MC146818_ALARM_MINUTES 0x03
|
||||
#define TODC_TYPE_MC146818_ALARM_SECONDS 0x01
|
||||
#define TODC_TYPE_MC146818_CENTURY 0xff
|
||||
#define TODC_TYPE_MC146818_FLAGS 0xff
|
||||
#define TODC_TYPE_MC146818_NVRAM_ADDR_REG 0
|
||||
#define TODC_TYPE_MC146818_NVRAM_DATA_REG 0
|
||||
|
||||
#define TODC_TYPE_PC97307_NVRAM_SIZE 0 /* No NVRAM? */
|
||||
#define TODC_TYPE_PC97307_SW_FLAGS 0
|
||||
#define TODC_TYPE_PC97307_YEAR 0x09
|
||||
#define TODC_TYPE_PC97307_MONTH 0x08
|
||||
#define TODC_TYPE_PC97307_DOM 0x07 /* Day of Month */
|
||||
#define TODC_TYPE_PC97307_DOW 0x06 /* Day of Week */
|
||||
#define TODC_TYPE_PC97307_HOURS 0x04
|
||||
#define TODC_TYPE_PC97307_MINUTES 0x02
|
||||
#define TODC_TYPE_PC97307_SECONDS 0x00
|
||||
#define TODC_TYPE_PC97307_CNTL_B 0x0a
|
||||
#define TODC_TYPE_PC97307_CNTL_A 0x0b /* control_a R/W regs */
|
||||
#define TODC_TYPE_PC97307_WATCHDOG 0x0c
|
||||
#define TODC_TYPE_PC97307_INTERRUPTS 0x0d
|
||||
#define TODC_TYPE_PC97307_ALARM_DATE 0xff
|
||||
#define TODC_TYPE_PC97307_ALARM_HOUR 0x05
|
||||
#define TODC_TYPE_PC97307_ALARM_MINUTES 0x03
|
||||
#define TODC_TYPE_PC97307_ALARM_SECONDS 0x01
|
||||
#define TODC_TYPE_PC97307_CENTURY 0xff
|
||||
#define TODC_TYPE_PC97307_FLAGS 0xff
|
||||
#define TODC_TYPE_PC97307_NVRAM_ADDR_REG 0
|
||||
#define TODC_TYPE_PC97307_NVRAM_DATA_REG 0
|
||||
|
||||
/*
|
||||
* Define macros to allocate and init the todc_info_t table that will
|
||||
* be used by the todc_time.c routines.
|
||||
*/
|
||||
#define TODC_ALLOC() \
|
||||
static todc_info_t todc_info_alloc; \
|
||||
todc_info_t *todc_info = &todc_info_alloc;
|
||||
|
||||
#define TODC_INIT(clock_type, as0, as1, data, bits) { \
|
||||
todc_info->rtc_type = clock_type; \
|
||||
\
|
||||
todc_info->nvram_as0 = (unsigned int)(as0); \
|
||||
todc_info->nvram_as1 = (unsigned int)(as1); \
|
||||
todc_info->nvram_data = (unsigned int)(data); \
|
||||
\
|
||||
todc_info->as0_bits = (bits); \
|
||||
\
|
||||
todc_info->nvram_size = clock_type ##_NVRAM_SIZE; \
|
||||
todc_info->sw_flags = clock_type ##_SW_FLAGS; \
|
||||
\
|
||||
todc_info->year = clock_type ##_YEAR; \
|
||||
todc_info->month = clock_type ##_MONTH; \
|
||||
todc_info->day_of_month = clock_type ##_DOM; \
|
||||
todc_info->day_of_week = clock_type ##_DOW; \
|
||||
todc_info->hours = clock_type ##_HOURS; \
|
||||
todc_info->minutes = clock_type ##_MINUTES; \
|
||||
todc_info->seconds = clock_type ##_SECONDS; \
|
||||
todc_info->control_b = clock_type ##_CNTL_B; \
|
||||
todc_info->control_a = clock_type ##_CNTL_A; \
|
||||
todc_info->watchdog = clock_type ##_WATCHDOG; \
|
||||
todc_info->interrupts = clock_type ##_INTERRUPTS; \
|
||||
todc_info->alarm_date = clock_type ##_ALARM_DATE; \
|
||||
todc_info->alarm_hour = clock_type ##_ALARM_HOUR; \
|
||||
todc_info->alarm_minutes = clock_type ##_ALARM_MINUTES; \
|
||||
todc_info->alarm_seconds = clock_type ##_ALARM_SECONDS; \
|
||||
todc_info->century = clock_type ##_CENTURY; \
|
||||
todc_info->flags = clock_type ##_FLAGS; \
|
||||
\
|
||||
todc_info->nvram_addr_reg = clock_type ##_NVRAM_ADDR_REG; \
|
||||
todc_info->nvram_data_reg = clock_type ##_NVRAM_DATA_REG; \
|
||||
}
|
||||
|
||||
extern todc_info_t *todc_info;
|
||||
|
||||
unsigned char todc_direct_read_val(int addr);
|
||||
void todc_direct_write_val(int addr, unsigned char val);
|
||||
unsigned char todc_m48txx_read_val(int addr);
|
||||
void todc_m48txx_write_val(int addr, unsigned char val);
|
||||
unsigned char todc_mc146818_read_val(int addr);
|
||||
void todc_mc146818_write_val(int addr, unsigned char val);
|
||||
|
||||
long todc_time_init(void);
|
||||
void todc_get_rtc_time(struct rtc_time *);
|
||||
int todc_set_rtc_time(struct rtc_time *);
|
||||
void todc_calibrate_decr(void);
|
||||
|
||||
#endif /* __PPC_KERNEL_TODC_H */
|
||||
109
include/asm-powerpc/tsi108.h
Normal file
109
include/asm-powerpc/tsi108.h
Normal file
|
|
@ -0,0 +1,109 @@
|
|||
/*
|
||||
* include/asm-ppc/tsi108.h
|
||||
*
|
||||
* common routine and memory layout for Tundra TSI108(Grendel) host bridge
|
||||
* memory controller.
|
||||
*
|
||||
* Author: Jacob Pan (jacob.pan@freescale.com)
|
||||
* Alex Bounine (alexandreb@tundra.com)
|
||||
* 2004 (c) Freescale Semiconductor Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
#ifndef __PPC_KERNEL_TSI108_H
|
||||
#define __PPC_KERNEL_TSI108_H
|
||||
|
||||
#include <asm/pci-bridge.h>
|
||||
|
||||
/* Size of entire register space */
|
||||
#define TSI108_REG_SIZE (0x10000)
|
||||
|
||||
/* Sizes of register spaces for individual blocks */
|
||||
#define TSI108_HLP_SIZE 0x1000
|
||||
#define TSI108_PCI_SIZE 0x1000
|
||||
#define TSI108_CLK_SIZE 0x1000
|
||||
#define TSI108_PB_SIZE 0x1000
|
||||
#define TSI108_SD_SIZE 0x1000
|
||||
#define TSI108_DMA_SIZE 0x1000
|
||||
#define TSI108_ETH_SIZE 0x1000
|
||||
#define TSI108_I2C_SIZE 0x400
|
||||
#define TSI108_MPIC_SIZE 0x400
|
||||
#define TSI108_UART0_SIZE 0x200
|
||||
#define TSI108_GPIO_SIZE 0x200
|
||||
#define TSI108_UART1_SIZE 0x200
|
||||
|
||||
/* Offsets within Tsi108(A) CSR space for individual blocks */
|
||||
#define TSI108_HLP_OFFSET 0x0000
|
||||
#define TSI108_PCI_OFFSET 0x1000
|
||||
#define TSI108_CLK_OFFSET 0x2000
|
||||
#define TSI108_PB_OFFSET 0x3000
|
||||
#define TSI108_SD_OFFSET 0x4000
|
||||
#define TSI108_DMA_OFFSET 0x5000
|
||||
#define TSI108_ETH_OFFSET 0x6000
|
||||
#define TSI108_I2C_OFFSET 0x7000
|
||||
#define TSI108_MPIC_OFFSET 0x7400
|
||||
#define TSI108_UART0_OFFSET 0x7800
|
||||
#define TSI108_GPIO_OFFSET 0x7A00
|
||||
#define TSI108_UART1_OFFSET 0x7C00
|
||||
|
||||
/* Tsi108 registers used by common code components */
|
||||
#define TSI108_PCI_CSR (0x004)
|
||||
#define TSI108_PCI_IRP_CFG_CTL (0x180)
|
||||
#define TSI108_PCI_IRP_STAT (0x184)
|
||||
#define TSI108_PCI_IRP_ENABLE (0x188)
|
||||
#define TSI108_PCI_IRP_INTAD (0x18C)
|
||||
|
||||
#define TSI108_PCI_IRP_STAT_P_INT (0x00400000)
|
||||
#define TSI108_PCI_IRP_ENABLE_P_INT (0x00400000)
|
||||
|
||||
#define TSI108_CG_PWRUP_STATUS (0x234)
|
||||
|
||||
#define TSI108_PB_ISR (0x00C)
|
||||
#define TSI108_PB_ERRCS (0x404)
|
||||
#define TSI108_PB_AERR (0x408)
|
||||
|
||||
#define TSI108_PB_ERRCS_ES (1 << 1)
|
||||
#define TSI108_PB_ISR_PBS_RD_ERR (1 << 8)
|
||||
|
||||
#define TSI108_PCI_CFG_BASE_PHYS (0xfb000000)
|
||||
#define TSI108_PCI_CFG_SIZE (0x01000000)
|
||||
/* Global variables */
|
||||
|
||||
extern u32 tsi108_pci_cfg_base;
|
||||
/* Exported functions */
|
||||
|
||||
extern int tsi108_bridge_init(struct pci_controller *hose, uint phys_csr_base);
|
||||
extern unsigned long tsi108_get_mem_size(void);
|
||||
extern unsigned long tsi108_get_cpu_clk(void);
|
||||
extern unsigned long tsi108_get_sdc_clk(void);
|
||||
extern int tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfn,
|
||||
int offset, int len, u32 val);
|
||||
extern int tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn,
|
||||
int offset, int len, u32 * val);
|
||||
extern void tsi108_clear_pci_error(u32 pci_cfg_base);
|
||||
|
||||
extern phys_addr_t get_csrbase(void);
|
||||
|
||||
typedef struct {
|
||||
u32 regs; /* hw registers base address */
|
||||
u32 phyregs; /* phy registers base address */
|
||||
u16 phy; /* phy address */
|
||||
u16 irq_num; /* irq number */
|
||||
u8 mac_addr[6]; /* phy mac address */
|
||||
} hw_info;
|
||||
|
||||
extern u32 get_vir_csrbase(void);
|
||||
extern u32 tsi108_csr_vir_base;
|
||||
|
||||
extern inline u32 tsi108_read_reg(u32 reg_offset)
|
||||
{
|
||||
return in_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset));
|
||||
}
|
||||
|
||||
extern inline void tsi108_write_reg(u32 reg_offset, u32 val)
|
||||
{
|
||||
out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val);
|
||||
}
|
||||
|
||||
#endif /* __PPC_KERNEL_TSI108_H */
|
||||
|
|
@ -42,7 +42,8 @@ extern void __init udbg_init_debug_lpar(void);
|
|||
extern void __init udbg_init_pmac_realmode(void);
|
||||
extern void __init udbg_init_maple_realmode(void);
|
||||
extern void __init udbg_init_iseries(void);
|
||||
extern void __init udbg_init_rtas(void);
|
||||
extern void __init udbg_init_rtas_panel(void);
|
||||
extern void __init udbg_init_rtas_console(void);
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* _ASM_POWERPC_UDBG_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue