From 3aec0f023763445282560dc077de209ec3d2a533 Mon Sep 17 00:00:00 2001
From: Shyam Kumar Thella <sthella@qti.qualcomm.com>
Date: Thu, 19 Nov 2020 16:39:29 +0530
Subject: [PATCH] ARM: dts: msm: Add PMIC support for monaco

Add an SPMI arbiter device to communicate with PMICs attached to
the SPMI bus. Add top level SPMI slave device for pm5100 and also some
of the peripheral devices within the SPMI slave.

Change-Id: Ifd73a8fc3418911c85343c2201a6e36c7915e72c
---
 qcom/monaco.dtsi | 19 ++++++++++++++++
 qcom/pm5100.dtsi | 56 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 75 insertions(+)
 create mode 100644 qcom/pm5100.dtsi

diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi
index f15bcb2b78b3..27dbb3c6e971 100644
--- a/qcom/monaco.dtsi
+++ b/qcom/monaco.dtsi
@@ -535,6 +535,25 @@
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
+
+	spmi_bus: qcom,spmi@1c40000 {
+		compatible = "qcom,spmi-pmic-arb";
+		reg = <0x1c40000 0x1100>,
+			<0x1e00000 0x2000000>,
+			<0x3e00000 0x100000>,
+			<0x3f00000 0xa0000>,
+			<0x1c0a000 0x26000>;
+		reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+		interrupt-names = "periph_irq";
+		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,ee = <0>;
+		qcom,channel = <0>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+		interrupt-controller;
+		#interrupt-cells = <4>;
+		cell-index = <0>;
+	};
 };
 
 #include "monaco-pinctrl.dtsi"
diff --git a/qcom/pm5100.dtsi b/qcom/pm5100.dtsi
new file mode 100644
index 000000000000..8a163724775f
--- /dev/null
+++ b/qcom/pm5100.dtsi
@@ -0,0 +1,56 @@
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/qcom,qpnp-power-on.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+	#address-cells = <2>;
+	#size-cells = <0>;
+	interrupt-controller;
+	#interrupt-cells = <4>;
+
+	qcom,pm5100@0 {
+		compatible = "qcom,spmi-pmic";
+		reg = <0 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pon_hlos@1300 {
+			compatible = "qcom,qpnp-power-on";
+			reg = <0x1300>;
+			interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>,
+				     <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
+			interrupt-names = "kpdpwr", "resin";
+
+			qcom,pon_1 {
+				qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
+				linux,code = <KEY_POWER>;
+			};
+
+			qcom,pon_2 {
+				qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
+				linux,code = <KEY_VOLUMEDOWN>;
+			};
+		};
+
+		pm5100_tz: qcom,temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm5100_gpios: pinctrl@8800 {
+			compatible = "qcom,pm5100-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pm5100_rtc: qcom,pm5100_rtc {
+			compatible = "qcom,pm8941-rtc";
+			interrupts = <0x0 0x65 0x1 IRQ_TYPE_NONE>;
+		};
+	};
+};