From 3b2249f3cc878713e3f601272bdaa44d35287593 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Fri, 12 Feb 2021 12:52:29 +0530 Subject: [PATCH] ARM: dts: msm: Add DPC property for SM8150 Add "dynamic-power-coefficient" property to all cores. The "capacity-dmips-mhz" and "dynamic-power-coefficient" are used to build Energy Model which in turn used by EAS to take placement decisions. Change-Id: I9cc9f97116b5aa9cdf9f3b6e250b30a170db910c --- qcom/sm8150.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 012119a96c3a..5bde3d947bf8 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -54,6 +54,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0 4>; L2_0: l2-cache { @@ -75,6 +76,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_1>; qcom,freq-domain = <&cpufreq_hw 0 4>; L2_1: l2-cache { @@ -91,6 +93,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_2>; qcom,freq-domain = <&cpufreq_hw 0 4>; L2_2: l2-cache { @@ -107,6 +110,7 @@ enable-method = "psci"; cpu-idle-states = <&SLVR_RAIL_OFF>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_3>; qcom,freq-domain = <&cpufreq_hw 0 4>; L2_3: l2-cache { @@ -123,6 +127,7 @@ enable-method = "psci"; cpu-idle-states = <&GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <374>; next-level-cache = <&L2_4>; qcom,freq-domain = <&cpufreq_hw 1 4>; L2_4: l2-cache { @@ -139,6 +144,7 @@ enable-method = "psci"; cpu-idle-states = <&GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <374>; next-level-cache = <&L2_5>; qcom,freq-domain = <&cpufreq_hw 1 4>; L2_5: l2-cache { @@ -155,6 +161,7 @@ enable-method = "psci"; cpu-idle-states = <&GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <374>; next-level-cache = <&L2_6>; qcom,freq-domain = <&cpufreq_hw 1 4>; L2_6: l2-cache { @@ -171,6 +178,7 @@ enable-method = "psci"; cpu-idle-states = <&GOLD_RAIL_OFF>; capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <431>; next-level-cache = <&L2_7>; qcom,freq-domain = <&cpufreq_hw 2 4>; L2_7: l2-cache {