From 06b49539333e00ae80cbfa5828b3c89c30988333 Mon Sep 17 00:00:00 2001 From: Nitesh Gupta Date: Mon, 26 Apr 2021 23:16:03 +0530 Subject: [PATCH] ARM: dts: msm: add MHI register space info for PCIe on SM8150 Add MHI register space information for PCIe so feature such as displaying ASPM stats is possible on SM8150. Change-Id: Ic16e20be3224ba2cdff337e72d9907b6bbbb2d1e --- qcom/sm8150-pcie.dtsi | 12 ++++++++---- qcom/sm8150-v2.dtsi | 6 ++++-- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/qcom/sm8150-pcie.dtsi b/qcom/sm8150-pcie.dtsi index 367c832e495b..204f8a90c28a 100644 --- a/qcom/sm8150-pcie.dtsi +++ b/qcom/sm8150-pcie.dtsi @@ -12,10 +12,12 @@ <0x60001000 0x1000>, <0x60100000 0x100000>, <0x60200000 0x100000>, - <0x60300000 0x3d00000>; + <0x60300000 0x3d00000>, + <0x01c06000 0x1000>; reg-names = "parf", "phy", "dm_core", "elbi", - "iatu", "conf", "io", "bars"; + "iatu", "conf", "io", "bars", + "mhi"; #address-cells = <3>; #size-cells = <2>; @@ -282,10 +284,12 @@ <0x40001000 0x1000>, <0x40100000 0x100000>, <0x40200000 0x100000>, - <0x40300000 0x1fd00000>; + <0x40300000 0x1fd00000>, + <0x01c0e000 0x1000>; reg-names = "parf", "phy", "dm_core", "elbi", - "iatu", "conf", "io", "bars"; + "iatu", "conf", "io", "bars", + "mhi"; #address-cells = <3>; #size-cells = <2>; diff --git a/qcom/sm8150-v2.dtsi b/qcom/sm8150-v2.dtsi index 89f7cf5c1bfc..cf27fe93f154 100644 --- a/qcom/sm8150-v2.dtsi +++ b/qcom/sm8150-v2.dtsi @@ -50,7 +50,8 @@ <0x60001000 0x1000>, <0x60100000 0x100000>, <0x60200000 0x100000>, - <0x60300000 0x3d00000>; + <0x60300000 0x3d00000>, + <0x01c03000 0x1000>; qcom,pcie-phy-ver = <2110>; @@ -160,7 +161,8 @@ <0x40001000 0x1000>, <0x40100000 0x100000>, <0x40200000 0x100000>, - <0x40300000 0x1fd00000>; + <0x40300000 0x1fd00000>, + <0x01c0b000 0x1000>; qcom,pcie-phy-ver = <2109>;