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clk: socfpga: stratix10: add additional clocks needed for the NAND IP

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The nand_clk is actually called the nand_x_clk and the parent is the
l4_mp_clk, not the l4_main_clk. The nand_clk is a child of the
nand_x_clk and has a fixed divider of 4. The same is true for the
nand_ecc_clk.

Signed-off-by: Dinh Nguyen <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
This commit is contained in:
Dinh Nguyen 2019-06-24 16:47:10 -05:00 • committed by Stephen Boyd
commit 3b5015c4d8
2 changed files with 8 additions and 2 deletions
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4
include/dt-bindings/clock/stratix10-clock.h
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@ -79,6 +79,8 @@
#define STRATIX10_USB_CLK 59
#define STRATIX10_SPI_M_CLK 60
#define STRATIX10_NAND_CLK 61
#define STRATIX10_NUM_CLKS 62
#define STRATIX10_NAND_X_CLK 62
#define STRATIX10_NAND_ECC_CLK 63
#define STRATIX10_NUM_CLKS 64
#endif /* __STRATIX10_CLOCK_H */