From 3bb69233399a69fa89d35a39f90e77bcd7cbabc7 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Wed, 24 Feb 2021 10:05:52 +0530 Subject: [PATCH] clk: qcom: Update halt_check flags for UFS axi clocks Update the halt_check flags to BRANCH_HALT_VOTED for UFS axi clocks. Change-Id: Icafcb0041947a64efe828801edfe62215556ddaf Signed-off-by: Veera Vegivada --- drivers/clk/qcom/gcc-scshrike.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/gcc-scshrike.c b/drivers/clk/qcom/gcc-scshrike.c index d1c780f6c356..31ffa4a4f87d 100644 --- a/drivers/clk/qcom/gcc-scshrike.c +++ b/drivers/clk/qcom/gcc-scshrike.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */ #include @@ -1933,7 +1933,7 @@ static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { static struct clk_branch gcc_aggre_ufs_card_2_axi_clk = { .halt_reg = 0xa20c0, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_VOTED, .hwcg_reg = 0xa20c0, .hwcg_bit = 1, .clkr = { @@ -1953,7 +1953,7 @@ static struct clk_branch gcc_aggre_ufs_card_2_axi_clk = { static struct clk_branch gcc_aggre_ufs_card_axi_clk = { .halt_reg = 0x750c0, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_VOTED, .hwcg_reg = 0x750c0, .hwcg_bit = 1, .clkr = { @@ -1973,7 +1973,7 @@ static struct clk_branch gcc_aggre_ufs_card_axi_clk = { static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = { .halt_reg = 0x750c0, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_VOTED, .hwcg_reg = 0x750c0, .hwcg_bit = 1, .clkr = { @@ -1993,7 +1993,7 @@ static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = { static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { .halt_reg = 0x770c0, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_VOTED, .hwcg_reg = 0x770c0, .hwcg_bit = 1, .clkr = { @@ -2013,7 +2013,7 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { .halt_reg = 0x770c0, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_VOTED, .hwcg_reg = 0x770c0, .hwcg_bit = 1, .clkr = {