mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-30 03:27:44 -04:00
PCI changes for the v4.1 merge window:
Enumeration
- Read capability list as dwords, not bytes (Sean O. Stalley)
Resource management
- Don't check for PNP overlaps with unassigned PCI BARs (Bjorn Helgaas)
- Mark invalid BARs as unassigned (Bjorn Helgaas)
- Show driver, BAR#, and resource on pci_ioremap_bar() failure (Bjorn Helgaas)
- Fail pci_ioremap_bar() on unassigned resources (Bjorn Helgaas)
- Assign resources before drivers claim devices (Yijing Wang)
- Claim bus resources before pci_bus_add_devices() (Yijing Wang)
Power management
- Optimize device state transition delays (Aaron Lu)
- Don't clear ASPM bits when the FADT declares it's unsupported (Matthew Garrett)
Virtualization
- Add ACS quirks for Intel 1G NICs (Alex Williamson)
IOMMU
- Add ptr to OF node arg to of_iommu_configure() (Murali Karicheri)
- Move of_dma_configure() to device.c to help re-use (Murali Karicheri)
- Fix size when dma-range is not used (Murali Karicheri)
- Add helper functions pci_get[put]_host_bridge_device() (Murali Karicheri)
- Add of_pci_dma_configure() to update DMA configuration (Murali Karicheri)
- Update DMA configuration from DT (Murali Karicheri)
- dma-mapping: limit IOMMU mapping size (Murali Karicheri)
- Calculate device DMA masks based on DT dma-range size (Murali Karicheri)
ARM Versatile host bridge driver
- Check for devm_ioremap_resource() failures (Jisheng Zhang)
Broadcom iProc host bridge driver
- Add Broadcom iProc PCIe driver (Ray Jui)
Marvell MVEBU host bridge driver
- Add suspend/resume support (Thomas Petazzoni)
Renesas R-Car host bridge driver
- Fix position of MSI enable bit (Nobuhiro Iwamatsu)
- Write zeroes to reserved PCIEPARL bits (Nobuhiro Iwamatsu)
- Change PCIEPARL and PCIEPARH to PCIEPALR and PCIEPAUR (Nobuhiro Iwamatsu)
- Verify that mem_res is 64K-aligned (Nobuhiro Iwamatsu)
Samsung Exynos host bridge driver
- Fix INTx enablement statement termination error (Jaehoon Chung)
Miscellaneous
- Make a shareable UUID for PCI firmware ACPI _DSM (Aaron Lu)
- Clarify policy for vendor IDs in pci.txt (Michael S. Tsirkin)
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVK/X+AAoJEFmIoMA60/r8hlkP/0e1GhAWA3DGR/+O2OPIkJ2w
dQVgv5IN5KXGExT9RHiDL/Ib2PhDvdVI26sinjtkw/FcjyzoWVsPDUzCYudQaPSr
zwzZto7dBzfv+exDN2LOqoSscCORAehApmTgYVg29cofJmKlO2ctDtpem1OT0MQ9
CMRMoBHhRe4FF3VJPOBPDXYpS89TObrY600aMDGk4S2uBboZI3aeYiTNLXJyh6fX
vRg3TWnTfQHoZINW/YOqao/WbrRixZbO6q4n2IqhI6i/uaAc1IEALk9im8/2ri/s
mgb/K5Elq+j4yUGnbFRz62pj/YxwnQKwVO4Nc7P66zENgoOXtv+OGRhlS4+d00/n
ux0+BkoxJdaL8HQ/b7+uPydiD85lbERM+B2+LQQ7JN+HI+UEcQ0PsK2hSQKb3njD
uEkktlKZViiqALijpL+vKRFe8U4GRE4KUfVsKHhhPPvY5sQTAZ3DrR36e1zKz2pA
YJjtaHYW0S/tfoEzi3EnPistbJw5sT0/Waj31QTKb/P0Fr7pHnJfcwV7+unXbKla
Osz8m6ELIqxhnuzhjlbayh4MKn49n1ZlwkwCnBdjgLQy0KZtxsWZoBg8LeGU077c
TJXukRfl3H8LvpqGMYaxOyw7yUeKobEWy+Ylo5asFnfFw9h6zvW+Sc97jtBCrm4/
OZa7rKdPQGGMbQFMvDc2
=vEVs
-----END PGP SIGNATURE-----
Merge tag 'pci-v4.1-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI changes from Bjorn Helgaas:
"Enumeration
- Read capability list as dwords, not bytes (Sean O. Stalley)
Resource management
- Don't check for PNP overlaps with unassigned PCI BARs (Bjorn Helgaas)
- Mark invalid BARs as unassigned (Bjorn Helgaas)
- Show driver, BAR#, and resource on pci_ioremap_bar() failure (Bjorn Helgaas)
- Fail pci_ioremap_bar() on unassigned resources (Bjorn Helgaas)
- Assign resources before drivers claim devices (Yijing Wang)
- Claim bus resources before pci_bus_add_devices() (Yijing Wang)
Power management
- Optimize device state transition delays (Aaron Lu)
- Don't clear ASPM bits when the FADT declares it's unsupported (Matthew Garrett)
Virtualization
- Add ACS quirks for Intel 1G NICs (Alex Williamson)
IOMMU
- Add ptr to OF node arg to of_iommu_configure() (Murali Karicheri)
- Move of_dma_configure() to device.c to help re-use (Murali Karicheri)
- Fix size when dma-range is not used (Murali Karicheri)
- Add helper functions pci_get[put]_host_bridge_device() (Murali Karicheri)
- Add of_pci_dma_configure() to update DMA configuration (Murali Karicheri)
- Update DMA configuration from DT (Murali Karicheri)
- dma-mapping: limit IOMMU mapping size (Murali Karicheri)
- Calculate device DMA masks based on DT dma-range size (Murali Karicheri)
ARM Versatile host bridge driver
- Check for devm_ioremap_resource() failures (Jisheng Zhang)
Broadcom iProc host bridge driver
- Add Broadcom iProc PCIe driver (Ray Jui)
Marvell MVEBU host bridge driver
- Add suspend/resume support (Thomas Petazzoni)
Renesas R-Car host bridge driver
- Fix position of MSI enable bit (Nobuhiro Iwamatsu)
- Write zeroes to reserved PCIEPARL bits (Nobuhiro Iwamatsu)
- Change PCIEPARL and PCIEPARH to PCIEPALR and PCIEPAUR (Nobuhiro Iwamatsu)
- Verify that mem_res is 64K-aligned (Nobuhiro Iwamatsu)
Samsung Exynos host bridge driver
- Fix INTx enablement statement termination error (Jaehoon Chung)
Miscellaneous
- Make a shareable UUID for PCI firmware ACPI _DSM (Aaron Lu)
- Clarify policy for vendor IDs in pci.txt (Michael S. Tsirkin)"
* tag 'pci-v4.1-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (36 commits)
PCI: Read capability list as dwords, not bytes
PCI: layerscape: Simplify platform_get_resource_byname() failure checking
PCI: keystone: Don't dereference possible NULL pointer
PCI: versatile: Check for devm_ioremap_resource() failures
PCI: Don't clear ASPM bits when the FADT declares it's unsupported
PCI: Clarify policy for vendor IDs in pci.txt
PCI/ACPI: Optimize device state transition delays
PCI: Export pci_find_host_bridge() for use inside PCI core
PCI: Make a shareable UUID for PCI firmware ACPI _DSM
PCI: Fix typo in Thunderbolt kernel message
PCI: exynos: Fix INTx enablement statement termination error
PCI: iproc: Add Broadcom iProc PCIe support
PCI: iproc: Add DT docs for Broadcom iProc PCIe driver
PCI: Export symbols required for loadable host driver modules
PCI: Add ACS quirks for Intel 1G NICs
PCI: mvebu: Add suspend/resume support
PCI: Cleanup control flow
sparc/PCI: Claim bus resources before pci_bus_add_devices()
PCI: Assign resources before drivers claim devices (pci_scan_root_bus())
PCI: Fail pci_ioremap_bar() on unassigned resources
...
This commit is contained in:
Linus Torvalds
commit
3be1b98e07
61 changed files with 1007 additions and 228 deletions
|
|
@ -16,13 +16,27 @@ static struct pci_bus *find_pci_root_bus(struct pci_bus *bus)
|
|||
return bus;
|
||||
}
|
||||
|
||||
static struct pci_host_bridge *find_pci_host_bridge(struct pci_bus *bus)
|
||||
struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus)
|
||||
{
|
||||
struct pci_bus *root_bus = find_pci_root_bus(bus);
|
||||
|
||||
return to_pci_host_bridge(root_bus->bridge);
|
||||
}
|
||||
|
||||
struct device *pci_get_host_bridge_device(struct pci_dev *dev)
|
||||
{
|
||||
struct pci_bus *root_bus = find_pci_root_bus(dev->bus);
|
||||
struct device *bridge = root_bus->bridge;
|
||||
|
||||
kobject_get(&bridge->kobj);
|
||||
return bridge;
|
||||
}
|
||||
|
||||
void pci_put_host_bridge_device(struct device *dev)
|
||||
{
|
||||
kobject_put(&dev->kobj);
|
||||
}
|
||||
|
||||
void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
|
||||
void (*release_fn)(struct pci_host_bridge *),
|
||||
void *release_data)
|
||||
|
|
@ -34,7 +48,7 @@ void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
|
|||
void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
|
||||
struct resource *res)
|
||||
{
|
||||
struct pci_host_bridge *bridge = find_pci_host_bridge(bus);
|
||||
struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
|
||||
struct resource_entry *window;
|
||||
resource_size_t offset = 0;
|
||||
|
||||
|
|
@ -59,7 +73,7 @@ static bool region_contains(struct pci_bus_region *region1,
|
|||
void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
|
||||
struct pci_bus_region *region)
|
||||
{
|
||||
struct pci_host_bridge *bridge = find_pci_host_bridge(bus);
|
||||
struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
|
||||
struct resource_entry *window;
|
||||
resource_size_t offset = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -106,4 +106,23 @@ config PCI_VERSATILE
|
|||
bool "ARM Versatile PB PCI controller"
|
||||
depends on ARCH_VERSATILE
|
||||
|
||||
config PCIE_IPROC
|
||||
tristate "Broadcom iProc PCIe controller"
|
||||
depends on OF && ARM
|
||||
default n
|
||||
help
|
||||
This enables the iProc PCIe core controller support for Broadcom's
|
||||
iProc family of SoCs. An appropriate bus interface driver also needs
|
||||
to be enabled
|
||||
|
||||
config PCIE_IPROC_PLATFORM
|
||||
tristate "Broadcom iProc PCIe platform bus driver"
|
||||
depends on ARCH_BCM_IPROC || (ARM && COMPILE_TEST)
|
||||
depends on OF
|
||||
select PCIE_IPROC
|
||||
default ARCH_BCM_IPROC
|
||||
help
|
||||
Say Y here if you want to use the Broadcom iProc PCIe controller
|
||||
through the generic platform bus interface
|
||||
|
||||
endmenu
|
||||
|
|
|
|||
|
|
@ -13,3 +13,5 @@ obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
|
|||
obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
|
||||
obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
|
||||
obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
|
||||
obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
|
||||
obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
|
||||
|
|
|
|||
|
|
@ -396,7 +396,7 @@ static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp)
|
|||
|
||||
/* enable INTX interrupt */
|
||||
val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
|
||||
IRQ_INTC_ASSERT | IRQ_INTD_ASSERT,
|
||||
IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
|
||||
exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -496,11 +496,12 @@ int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
|
|||
|
||||
/* Index 1 is the application reg. space address */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
ks_pcie->app = *res;
|
||||
ks_pcie->va_app_base = devm_ioremap_resource(pp->dev, res);
|
||||
if (IS_ERR(ks_pcie->va_app_base))
|
||||
return PTR_ERR(ks_pcie->va_app_base);
|
||||
|
||||
ks_pcie->app = *res;
|
||||
|
||||
/* Create legacy IRQ domain */
|
||||
ks_pcie->legacy_irq_domain =
|
||||
irq_domain_add_linear(ks_pcie->legacy_intc_np,
|
||||
|
|
|
|||
|
|
@ -127,14 +127,11 @@ static int __init ls_pcie_probe(struct platform_device *pdev)
|
|||
pcie->dev = &pdev->dev;
|
||||
|
||||
dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
|
||||
if (!dbi_base) {
|
||||
dev_err(&pdev->dev, "missing *regs* space\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
|
||||
if (IS_ERR(pcie->dbi))
|
||||
if (IS_ERR(pcie->dbi)) {
|
||||
dev_err(&pdev->dev, "missing *regs* space\n");
|
||||
return PTR_ERR(pcie->dbi);
|
||||
}
|
||||
|
||||
pcie->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
|
||||
"fsl,pcie-scfg");
|
||||
|
|
|
|||
|
|
@ -129,6 +129,7 @@ struct mvebu_pcie_port {
|
|||
size_t memwin_size;
|
||||
phys_addr_t iowin_base;
|
||||
size_t iowin_size;
|
||||
u32 saved_pcie_stat;
|
||||
};
|
||||
|
||||
static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
|
||||
|
|
@ -899,6 +900,35 @@ static void mvebu_pcie_msi_enable(struct mvebu_pcie *pcie)
|
|||
pcie->msi->dev = &pcie->pdev->dev;
|
||||
}
|
||||
|
||||
static int mvebu_pcie_suspend(struct device *dev)
|
||||
{
|
||||
struct mvebu_pcie *pcie;
|
||||
int i;
|
||||
|
||||
pcie = dev_get_drvdata(dev);
|
||||
for (i = 0; i < pcie->nports; i++) {
|
||||
struct mvebu_pcie_port *port = pcie->ports + i;
|
||||
port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mvebu_pcie_resume(struct device *dev)
|
||||
{
|
||||
struct mvebu_pcie *pcie;
|
||||
int i;
|
||||
|
||||
pcie = dev_get_drvdata(dev);
|
||||
for (i = 0; i < pcie->nports; i++) {
|
||||
struct mvebu_pcie_port *port = pcie->ports + i;
|
||||
mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF);
|
||||
mvebu_pcie_setup_hw(port);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mvebu_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct mvebu_pcie *pcie;
|
||||
|
|
@ -1056,6 +1086,8 @@ static int mvebu_pcie_probe(struct platform_device *pdev)
|
|||
mvebu_pcie_msi_enable(pcie);
|
||||
mvebu_pcie_enable(pcie);
|
||||
|
||||
platform_set_drvdata(pdev, pcie);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1068,12 +1100,18 @@ static const struct of_device_id mvebu_pcie_of_match_table[] = {
|
|||
};
|
||||
MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
|
||||
|
||||
static struct dev_pm_ops mvebu_pcie_pm_ops = {
|
||||
.suspend_noirq = mvebu_pcie_suspend,
|
||||
.resume_noirq = mvebu_pcie_resume,
|
||||
};
|
||||
|
||||
static struct platform_driver mvebu_pcie_driver = {
|
||||
.driver = {
|
||||
.name = "mvebu-pcie",
|
||||
.of_match_table = mvebu_pcie_of_match_table,
|
||||
/* driver unloading/unbinding currently not supported */
|
||||
.suppress_bind_attrs = true,
|
||||
.pm = &mvebu_pcie_pm_ops,
|
||||
},
|
||||
.probe = mvebu_pcie_probe,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -301,6 +301,9 @@ static int rcar_pci_probe(struct platform_device *pdev)
|
|||
if (!mem_res || !mem_res->start)
|
||||
return -ENODEV;
|
||||
|
||||
if (mem_res->start & 0xFFFF)
|
||||
return -EINVAL;
|
||||
|
||||
priv = devm_kzalloc(&pdev->dev,
|
||||
sizeof(struct rcar_pci_priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
|
|
|
|||
|
|
@ -138,19 +138,19 @@ static int versatile_pci_probe(struct platform_device *pdev)
|
|||
LIST_HEAD(pci_res);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res)
|
||||
return -ENODEV;
|
||||
versatile_pci_base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(versatile_pci_base))
|
||||
return PTR_ERR(versatile_pci_base);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
if (!res)
|
||||
return -ENODEV;
|
||||
versatile_cfg_base[0] = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(versatile_cfg_base[0]))
|
||||
return PTR_ERR(versatile_cfg_base[0]);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
|
||||
if (!res)
|
||||
return -ENODEV;
|
||||
versatile_cfg_base[1] = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(versatile_cfg_base[1]))
|
||||
return PTR_ERR(versatile_cfg_base[1]);
|
||||
|
||||
ret = versatile_pci_parse_request_of_pci_ranges(&pdev->dev, &pci_res);
|
||||
if (ret)
|
||||
|
|
@ -214,6 +214,7 @@ static int versatile_pci_probe(struct platform_device *pdev)
|
|||
|
||||
pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
|
||||
pci_assign_unassigned_bus_resources(bus);
|
||||
pci_bus_add_devices(bus);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
108
drivers/pci/host/pcie-iproc-platform.c
Normal file
108
drivers/pci/host/pcie-iproc-platform.c
Normal file
|
|
@ -0,0 +1,108 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_pci.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/phy/phy.h>
|
||||
|
||||
#include "pcie-iproc.h"
|
||||
|
||||
static int iproc_pcie_pltfm_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct iproc_pcie *pcie;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct resource reg;
|
||||
resource_size_t iobase = 0;
|
||||
LIST_HEAD(res);
|
||||
int ret;
|
||||
|
||||
pcie = devm_kzalloc(&pdev->dev, sizeof(struct iproc_pcie), GFP_KERNEL);
|
||||
if (!pcie)
|
||||
return -ENOMEM;
|
||||
|
||||
pcie->dev = &pdev->dev;
|
||||
platform_set_drvdata(pdev, pcie);
|
||||
|
||||
ret = of_address_to_resource(np, 0, ®);
|
||||
if (ret < 0) {
|
||||
dev_err(pcie->dev, "unable to obtain controller resources\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pcie->base = devm_ioremap(pcie->dev, reg.start, resource_size(®));
|
||||
if (!pcie->base) {
|
||||
dev_err(pcie->dev, "unable to map controller registers\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* PHY use is optional */
|
||||
pcie->phy = devm_phy_get(&pdev->dev, "pcie-phy");
|
||||
if (IS_ERR(pcie->phy)) {
|
||||
if (PTR_ERR(pcie->phy) == -EPROBE_DEFER)
|
||||
return -EPROBE_DEFER;
|
||||
pcie->phy = NULL;
|
||||
}
|
||||
|
||||
ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &iobase);
|
||||
if (ret) {
|
||||
dev_err(pcie->dev,
|
||||
"unable to get PCI host bridge resources\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pcie->resources = &res;
|
||||
|
||||
ret = iproc_pcie_setup(pcie);
|
||||
if (ret) {
|
||||
dev_err(pcie->dev, "PCIe controller setup failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int iproc_pcie_pltfm_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct iproc_pcie *pcie = platform_get_drvdata(pdev);
|
||||
|
||||
return iproc_pcie_remove(pcie);
|
||||
}
|
||||
|
||||
static const struct of_device_id iproc_pcie_of_match_table[] = {
|
||||
{ .compatible = "brcm,iproc-pcie", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, iproc_pcie_of_match_table);
|
||||
|
||||
static struct platform_driver iproc_pcie_pltfm_driver = {
|
||||
.driver = {
|
||||
.name = "iproc-pcie",
|
||||
.of_match_table = of_match_ptr(iproc_pcie_of_match_table),
|
||||
},
|
||||
.probe = iproc_pcie_pltfm_probe,
|
||||
.remove = iproc_pcie_pltfm_remove,
|
||||
};
|
||||
module_platform_driver(iproc_pcie_pltfm_driver);
|
||||
|
||||
MODULE_AUTHOR("Ray Jui <[email protected]>");
|
||||
MODULE_DESCRIPTION("Broadcom iPROC PCIe platform driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
268
drivers/pci/host/pcie-iproc.c
Normal file
268
drivers/pci/host/pcie-iproc.c
Normal file
|
|
@ -0,0 +1,268 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
|
||||
* Copyright (C) 2015 Broadcom Corporatcommon ion
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/msi.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mbus.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_pci.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/phy/phy.h>
|
||||
|
||||
#include "pcie-iproc.h"
|
||||
|
||||
#define CLK_CONTROL_OFFSET 0x000
|
||||
#define EP_MODE_SURVIVE_PERST_SHIFT 1
|
||||
#define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
|
||||
#define RC_PCIE_RST_OUTPUT_SHIFT 0
|
||||
#define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
|
||||
|
||||
#define CFG_IND_ADDR_OFFSET 0x120
|
||||
#define CFG_IND_ADDR_MASK 0x00001ffc
|
||||
|
||||
#define CFG_IND_DATA_OFFSET 0x124
|
||||
|
||||
#define CFG_ADDR_OFFSET 0x1f8
|
||||
#define CFG_ADDR_BUS_NUM_SHIFT 20
|
||||
#define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
|
||||
#define CFG_ADDR_DEV_NUM_SHIFT 15
|
||||
#define CFG_ADDR_DEV_NUM_MASK 0x000f8000
|
||||
#define CFG_ADDR_FUNC_NUM_SHIFT 12
|
||||
#define CFG_ADDR_FUNC_NUM_MASK 0x00007000
|
||||
#define CFG_ADDR_REG_NUM_SHIFT 2
|
||||
#define CFG_ADDR_REG_NUM_MASK 0x00000ffc
|
||||
#define CFG_ADDR_CFG_TYPE_SHIFT 0
|
||||
#define CFG_ADDR_CFG_TYPE_MASK 0x00000003
|
||||
|
||||
#define CFG_DATA_OFFSET 0x1fc
|
||||
|
||||
#define SYS_RC_INTX_EN 0x330
|
||||
#define SYS_RC_INTX_MASK 0xf
|
||||
|
||||
static inline struct iproc_pcie *sys_to_pcie(struct pci_sys_data *sys)
|
||||
{
|
||||
return sys->private_data;
|
||||
}
|
||||
|
||||
/**
|
||||
* Note access to the configuration registers are protected at the higher layer
|
||||
* by 'pci_lock' in drivers/pci/access.c
|
||||
*/
|
||||
static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
|
||||
unsigned int devfn,
|
||||
int where)
|
||||
{
|
||||
struct pci_sys_data *sys = bus->sysdata;
|
||||
struct iproc_pcie *pcie = sys_to_pcie(sys);
|
||||
unsigned slot = PCI_SLOT(devfn);
|
||||
unsigned fn = PCI_FUNC(devfn);
|
||||
unsigned busno = bus->number;
|
||||
u32 val;
|
||||
|
||||
/* root complex access */
|
||||
if (busno == 0) {
|
||||
if (slot >= 1)
|
||||
return NULL;
|
||||
writel(where & CFG_IND_ADDR_MASK,
|
||||
pcie->base + CFG_IND_ADDR_OFFSET);
|
||||
return (pcie->base + CFG_IND_DATA_OFFSET);
|
||||
}
|
||||
|
||||
if (fn > 1)
|
||||
return NULL;
|
||||
|
||||
/* EP device access */
|
||||
val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
|
||||
(slot << CFG_ADDR_DEV_NUM_SHIFT) |
|
||||
(fn << CFG_ADDR_FUNC_NUM_SHIFT) |
|
||||
(where & CFG_ADDR_REG_NUM_MASK) |
|
||||
(1 & CFG_ADDR_CFG_TYPE_MASK);
|
||||
writel(val, pcie->base + CFG_ADDR_OFFSET);
|
||||
|
||||
return (pcie->base + CFG_DATA_OFFSET);
|
||||
}
|
||||
|
||||
static struct pci_ops iproc_pcie_ops = {
|
||||
.map_bus = iproc_pcie_map_cfg_bus,
|
||||
.read = pci_generic_config_read32,
|
||||
.write = pci_generic_config_write32,
|
||||
};
|
||||
|
||||
static void iproc_pcie_reset(struct iproc_pcie *pcie)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
* Configure the PCIe controller as root complex and send a downstream
|
||||
* reset
|
||||
*/
|
||||
val = EP_MODE_SURVIVE_PERST | RC_PCIE_RST_OUTPUT;
|
||||
writel(val, pcie->base + CLK_CONTROL_OFFSET);
|
||||
udelay(250);
|
||||
val &= ~EP_MODE_SURVIVE_PERST;
|
||||
writel(val, pcie->base + CLK_CONTROL_OFFSET);
|
||||
msleep(250);
|
||||
}
|
||||
|
||||
static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus)
|
||||
{
|
||||
u8 hdr_type;
|
||||
u32 link_ctrl;
|
||||
u16 pos, link_status;
|
||||
int link_is_active = 0;
|
||||
|
||||
/* make sure we are not in EP mode */
|
||||
pci_bus_read_config_byte(bus, 0, PCI_HEADER_TYPE, &hdr_type);
|
||||
if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {
|
||||
dev_err(pcie->dev, "in EP mode, hdr=%#02x\n", hdr_type);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
/* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
|
||||
pci_bus_write_config_word(bus, 0, PCI_CLASS_DEVICE,
|
||||
PCI_CLASS_BRIDGE_PCI);
|
||||
|
||||
/* check link status to see if link is active */
|
||||
pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
|
||||
pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, &link_status);
|
||||
if (link_status & PCI_EXP_LNKSTA_NLW)
|
||||
link_is_active = 1;
|
||||
|
||||
if (!link_is_active) {
|
||||
/* try GEN 1 link speed */
|
||||
#define PCI_LINK_STATUS_CTRL_2_OFFSET 0x0dc
|
||||
#define PCI_TARGET_LINK_SPEED_MASK 0xf
|
||||
#define PCI_TARGET_LINK_SPEED_GEN2 0x2
|
||||
#define PCI_TARGET_LINK_SPEED_GEN1 0x1
|
||||
pci_bus_read_config_dword(bus, 0,
|
||||
PCI_LINK_STATUS_CTRL_2_OFFSET,
|
||||
&link_ctrl);
|
||||
if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) ==
|
||||
PCI_TARGET_LINK_SPEED_GEN2) {
|
||||
link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK;
|
||||
link_ctrl |= PCI_TARGET_LINK_SPEED_GEN1;
|
||||
pci_bus_write_config_dword(bus, 0,
|
||||
PCI_LINK_STATUS_CTRL_2_OFFSET,
|
||||
link_ctrl);
|
||||
msleep(100);
|
||||
|
||||
pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
|
||||
pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA,
|
||||
&link_status);
|
||||
if (link_status & PCI_EXP_LNKSTA_NLW)
|
||||
link_is_active = 1;
|
||||
}
|
||||
}
|
||||
|
||||
dev_info(pcie->dev, "link: %s\n", link_is_active ? "UP" : "DOWN");
|
||||
|
||||
return link_is_active ? 0 : -ENODEV;
|
||||
}
|
||||
|
||||
static void iproc_pcie_enable(struct iproc_pcie *pcie)
|
||||
{
|
||||
writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN);
|
||||
}
|
||||
|
||||
int iproc_pcie_setup(struct iproc_pcie *pcie)
|
||||
{
|
||||
int ret;
|
||||
struct pci_bus *bus;
|
||||
|
||||
if (!pcie || !pcie->dev || !pcie->base)
|
||||
return -EINVAL;
|
||||
|
||||
if (pcie->phy) {
|
||||
ret = phy_init(pcie->phy);
|
||||
if (ret) {
|
||||
dev_err(pcie->dev, "unable to initialize PCIe PHY\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = phy_power_on(pcie->phy);
|
||||
if (ret) {
|
||||
dev_err(pcie->dev, "unable to power on PCIe PHY\n");
|
||||
goto err_exit_phy;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
iproc_pcie_reset(pcie);
|
||||
|
||||
pcie->sysdata.private_data = pcie;
|
||||
|
||||
bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops,
|
||||
&pcie->sysdata, pcie->resources);
|
||||
if (!bus) {
|
||||
dev_err(pcie->dev, "unable to create PCI root bus\n");
|
||||
ret = -ENOMEM;
|
||||
goto err_power_off_phy;
|
||||
}
|
||||
pcie->root_bus = bus;
|
||||
|
||||
ret = iproc_pcie_check_link(pcie, bus);
|
||||
if (ret) {
|
||||
dev_err(pcie->dev, "no PCIe EP device detected\n");
|
||||
goto err_rm_root_bus;
|
||||
}
|
||||
|
||||
iproc_pcie_enable(pcie);
|
||||
|
||||
pci_scan_child_bus(bus);
|
||||
pci_assign_unassigned_bus_resources(bus);
|
||||
pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
|
||||
pci_bus_add_devices(bus);
|
||||
|
||||
return 0;
|
||||
|
||||
err_rm_root_bus:
|
||||
pci_stop_root_bus(bus);
|
||||
pci_remove_root_bus(bus);
|
||||
|
||||
err_power_off_phy:
|
||||
if (pcie->phy)
|
||||
phy_power_off(pcie->phy);
|
||||
err_exit_phy:
|
||||
if (pcie->phy)
|
||||
phy_exit(pcie->phy);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(iproc_pcie_setup);
|
||||
|
||||
int iproc_pcie_remove(struct iproc_pcie *pcie)
|
||||
{
|
||||
pci_stop_root_bus(pcie->root_bus);
|
||||
pci_remove_root_bus(pcie->root_bus);
|
||||
|
||||
if (pcie->phy) {
|
||||
phy_power_off(pcie->phy);
|
||||
phy_exit(pcie->phy);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(iproc_pcie_remove);
|
||||
|
||||
MODULE_AUTHOR("Ray Jui <[email protected]>");
|
||||
MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
42
drivers/pci/host/pcie-iproc.h
Normal file
42
drivers/pci/host/pcie-iproc.h
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Copyright (C) 2014-2015 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _PCIE_IPROC_H
|
||||
#define _PCIE_IPROC_H
|
||||
|
||||
#define IPROC_PCIE_MAX_NUM_IRQS 6
|
||||
|
||||
/**
|
||||
* iProc PCIe device
|
||||
* @dev: pointer to device data structure
|
||||
* @base: PCIe host controller I/O register base
|
||||
* @resources: linked list of all PCI resources
|
||||
* @sysdata: Per PCI controller data
|
||||
* @root_bus: pointer to root bus
|
||||
* @phy: optional PHY device that controls the Serdes
|
||||
* @irqs: interrupt IDs
|
||||
*/
|
||||
struct iproc_pcie {
|
||||
struct device *dev;
|
||||
void __iomem *base;
|
||||
struct list_head *resources;
|
||||
struct pci_sys_data sysdata;
|
||||
struct pci_bus *root_bus;
|
||||
struct phy *phy;
|
||||
int irqs[IPROC_PCIE_MAX_NUM_IRQS];
|
||||
};
|
||||
|
||||
int iproc_pcie_setup(struct iproc_pcie *pcie);
|
||||
int iproc_pcie_remove(struct iproc_pcie *pcie);
|
||||
|
||||
#endif /* _PCIE_IPROC_H */
|
||||
|
|
@ -64,8 +64,8 @@
|
|||
#define LAR_ENABLE (1 << 1)
|
||||
|
||||
/* PCIe address reg & mask */
|
||||
#define PCIEPARL(x) (0x03400 + ((x) * 0x20))
|
||||
#define PCIEPARH(x) (0x03404 + ((x) * 0x20))
|
||||
#define PCIEPALR(x) (0x03400 + ((x) * 0x20))
|
||||
#define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
|
||||
#define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
|
||||
#define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
|
||||
#define PAR_ENABLE (1 << 31)
|
||||
|
|
@ -341,8 +341,9 @@ static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie)
|
|||
else
|
||||
res_start = res->start;
|
||||
|
||||
rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPARH(win));
|
||||
rcar_pci_write_reg(pcie, lower_32_bits(res_start), PCIEPARL(win));
|
||||
rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
|
||||
rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
|
||||
PCIEPALR(win));
|
||||
|
||||
/* First resource is for IO */
|
||||
mask = PAR_ENABLE;
|
||||
|
|
@ -501,7 +502,7 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
|
|||
|
||||
/* Enable MSI */
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI))
|
||||
rcar_pci_write_reg(pcie, 0x101f0000, PCIEMSITXR);
|
||||
rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
|
||||
|
||||
/* Finish initialization - establish a PCI Express link */
|
||||
rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
|
||||
|
|
|
|||
|
|
@ -738,7 +738,7 @@ static void ibm_unconfigure_device(struct pci_func *func)
|
|||
*/
|
||||
static u8 bus_structure_fixup(u8 busno)
|
||||
{
|
||||
struct pci_bus *bus;
|
||||
struct pci_bus *bus, *b;
|
||||
struct pci_dev *dev;
|
||||
u16 l;
|
||||
|
||||
|
|
@ -765,7 +765,11 @@ static u8 bus_structure_fixup(u8 busno)
|
|||
(l != 0x0000) && (l != 0xffff)) {
|
||||
debug("%s - Inside bus_structure_fixup()\n",
|
||||
__func__);
|
||||
pci_scan_bus(busno, ibmphp_pci_bus->ops, NULL);
|
||||
b = pci_scan_bus(busno, ibmphp_pci_bus->ops, NULL);
|
||||
if (!b)
|
||||
continue;
|
||||
|
||||
pci_bus_add_devices(b);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -18,6 +18,15 @@
|
|||
#include <linux/pm_qos.h>
|
||||
#include "pci.h"
|
||||
|
||||
/*
|
||||
* The UUID is defined in the PCI Firmware Specification available here:
|
||||
* https://www.pcisig.com/members/downloads/pcifw_r3_1_13Dec10.pdf
|
||||
*/
|
||||
const u8 pci_acpi_dsm_uuid[] = {
|
||||
0xd0, 0x37, 0xc9, 0xe5, 0x53, 0x35, 0x7a, 0x4d,
|
||||
0x91, 0x17, 0xea, 0x4d, 0x19, 0xc3, 0x43, 0x4d
|
||||
};
|
||||
|
||||
phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle)
|
||||
{
|
||||
acpi_status status = AE_NOT_EXIST;
|
||||
|
|
@ -531,11 +540,32 @@ static struct pci_platform_pm_ops acpi_pci_platform_pm = {
|
|||
|
||||
void acpi_pci_add_bus(struct pci_bus *bus)
|
||||
{
|
||||
union acpi_object *obj;
|
||||
struct pci_host_bridge *bridge;
|
||||
|
||||
if (acpi_pci_disabled || !bus->bridge)
|
||||
return;
|
||||
|
||||
acpi_pci_slot_enumerate(bus);
|
||||
acpiphp_enumerate_slots(bus);
|
||||
|
||||
/*
|
||||
* For a host bridge, check its _DSM for function 8 and if
|
||||
* that is available, mark it in pci_host_bridge.
|
||||
*/
|
||||
if (!pci_is_root_bus(bus))
|
||||
return;
|
||||
|
||||
obj = acpi_evaluate_dsm(ACPI_HANDLE(bus->bridge), pci_acpi_dsm_uuid, 3,
|
||||
RESET_DELAY_DSM, NULL);
|
||||
if (!obj)
|
||||
return;
|
||||
|
||||
if (obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 1) {
|
||||
bridge = pci_find_host_bridge(bus);
|
||||
bridge->ignore_reset_delay = 1;
|
||||
}
|
||||
ACPI_FREE(obj);
|
||||
}
|
||||
|
||||
void acpi_pci_remove_bus(struct pci_bus *bus)
|
||||
|
|
@ -561,6 +591,57 @@ static struct acpi_device *acpi_pci_find_companion(struct device *dev)
|
|||
check_children);
|
||||
}
|
||||
|
||||
/**
|
||||
* pci_acpi_optimize_delay - optimize PCI D3 and D3cold delay from ACPI
|
||||
* @pdev: the PCI device whose delay is to be updated
|
||||
* @adev: the companion ACPI device of this PCI device
|
||||
*
|
||||
* Update the d3_delay and d3cold_delay of a PCI device from the ACPI _DSM
|
||||
* control method of either the device itself or the PCI host bridge.
|
||||
*
|
||||
* Function 8, "Reset Delay," applies to the entire hierarchy below a PCI
|
||||
* host bridge. If it returns one, the OS may assume that all devices in
|
||||
* the hierarchy have already completed power-on reset delays.
|
||||
*
|
||||
* Function 9, "Device Readiness Durations," applies only to the object
|
||||
* where it is located. It returns delay durations required after various
|
||||
* events if the device requires less time than the spec requires. Delays
|
||||
* from this function take precedence over the Reset Delay function.
|
||||
*
|
||||
* These _DSM functions are defined by the draft ECN of January 28, 2014,
|
||||
* titled "ACPI additions for FW latency optimizations."
|
||||
*/
|
||||
static void pci_acpi_optimize_delay(struct pci_dev *pdev,
|
||||
acpi_handle handle)
|
||||
{
|
||||
struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
|
||||
int value;
|
||||
union acpi_object *obj, *elements;
|
||||
|
||||
if (bridge->ignore_reset_delay)
|
||||
pdev->d3cold_delay = 0;
|
||||
|
||||
obj = acpi_evaluate_dsm(handle, pci_acpi_dsm_uuid, 3,
|
||||
FUNCTION_DELAY_DSM, NULL);
|
||||
if (!obj)
|
||||
return;
|
||||
|
||||
if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 5) {
|
||||
elements = obj->package.elements;
|
||||
if (elements[0].type == ACPI_TYPE_INTEGER) {
|
||||
value = (int)elements[0].integer.value / 1000;
|
||||
if (value < PCI_PM_D3COLD_WAIT)
|
||||
pdev->d3cold_delay = value;
|
||||
}
|
||||
if (elements[3].type == ACPI_TYPE_INTEGER) {
|
||||
value = (int)elements[3].integer.value / 1000;
|
||||
if (value < PCI_PM_D3_WAIT)
|
||||
pdev->d3_delay = value;
|
||||
}
|
||||
}
|
||||
ACPI_FREE(obj);
|
||||
}
|
||||
|
||||
static void pci_acpi_setup(struct device *dev)
|
||||
{
|
||||
struct pci_dev *pci_dev = to_pci_dev(dev);
|
||||
|
|
@ -569,6 +650,8 @@ static void pci_acpi_setup(struct device *dev)
|
|||
if (!adev)
|
||||
return;
|
||||
|
||||
pci_acpi_optimize_delay(pci_dev, adev->handle);
|
||||
|
||||
pci_acpi_add_pm_notifier(adev, pci_dev);
|
||||
if (!adev->wakeup.flags.valid)
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -31,8 +31,6 @@
|
|||
#include <linux/pci-acpi.h>
|
||||
#include "pci.h"
|
||||
|
||||
#define DEVICE_LABEL_DSM 0x07
|
||||
|
||||
#ifdef CONFIG_DMI
|
||||
enum smbios_attr_enum {
|
||||
SMBIOS_ATTR_NONE = 0,
|
||||
|
|
@ -148,11 +146,6 @@ static inline void pci_remove_smbiosname_file(struct pci_dev *pdev)
|
|||
#endif
|
||||
|
||||
#ifdef CONFIG_ACPI
|
||||
static const char device_label_dsm_uuid[] = {
|
||||
0xD0, 0x37, 0xC9, 0xE5, 0x53, 0x35, 0x7A, 0x4D,
|
||||
0x91, 0x17, 0xEA, 0x4D, 0x19, 0xC3, 0x43, 0x4D
|
||||
};
|
||||
|
||||
enum acpi_attr_enum {
|
||||
ACPI_ATTR_LABEL_SHOW,
|
||||
ACPI_ATTR_INDEX_SHOW,
|
||||
|
|
@ -179,7 +172,7 @@ static int dsm_get_label(struct device *dev, char *buf,
|
|||
if (!handle)
|
||||
return -1;
|
||||
|
||||
obj = acpi_evaluate_dsm(handle, device_label_dsm_uuid, 0x2,
|
||||
obj = acpi_evaluate_dsm(handle, pci_acpi_dsm_uuid, 0x2,
|
||||
DEVICE_LABEL_DSM, NULL);
|
||||
if (!obj)
|
||||
return -1;
|
||||
|
|
@ -219,7 +212,7 @@ static bool device_has_dsm(struct device *dev)
|
|||
if (!handle)
|
||||
return false;
|
||||
|
||||
return !!acpi_check_dsm(handle, device_label_dsm_uuid, 0x2,
|
||||
return !!acpi_check_dsm(handle, pci_acpi_dsm_uuid, 0x2,
|
||||
1 << DEVICE_LABEL_DSM);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -126,15 +126,16 @@ EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
|
|||
#ifdef CONFIG_HAS_IOMEM
|
||||
void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
|
||||
{
|
||||
struct resource *res = &pdev->resource[bar];
|
||||
|
||||
/*
|
||||
* Make sure the BAR is actually a memory resource, not an IO resource
|
||||
*/
|
||||
if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
|
||||
WARN_ON(1);
|
||||
if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
|
||||
dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res);
|
||||
return NULL;
|
||||
}
|
||||
return ioremap_nocache(pci_resource_start(pdev, bar),
|
||||
pci_resource_len(pdev, bar));
|
||||
return ioremap_nocache(res->start, resource_size(res));
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_ioremap_bar);
|
||||
#endif
|
||||
|
|
@ -145,19 +146,22 @@ static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
|
|||
u8 pos, int cap, int *ttl)
|
||||
{
|
||||
u8 id;
|
||||
u16 ent;
|
||||
|
||||
pci_bus_read_config_byte(bus, devfn, pos, &pos);
|
||||
|
||||
while ((*ttl)--) {
|
||||
pci_bus_read_config_byte(bus, devfn, pos, &pos);
|
||||
if (pos < 0x40)
|
||||
break;
|
||||
pos &= ~3;
|
||||
pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
|
||||
&id);
|
||||
pci_bus_read_config_word(bus, devfn, pos, &ent);
|
||||
|
||||
id = ent & 0xff;
|
||||
if (id == 0xff)
|
||||
break;
|
||||
if (id == cap)
|
||||
return pos;
|
||||
pos += PCI_CAP_LIST_NEXT;
|
||||
pos = (ent >> 8);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -2492,6 +2496,7 @@ u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
|
|||
*pinp = pin;
|
||||
return PCI_SLOT(dev->devfn);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_common_swizzle);
|
||||
|
||||
/**
|
||||
* pci_release_region - Release a PCI bar
|
||||
|
|
|
|||
|
|
@ -321,4 +321,6 @@ static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
|
|||
}
|
||||
#endif
|
||||
|
||||
struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
|
||||
|
||||
#endif /* DRIVERS_PCI_H */
|
||||
|
|
|
|||
|
|
@ -782,24 +782,6 @@ void pci_disable_link_state(struct pci_dev *pdev, int state)
|
|||
}
|
||||
EXPORT_SYMBOL(pci_disable_link_state);
|
||||
|
||||
void pcie_clear_aspm(struct pci_bus *bus)
|
||||
{
|
||||
struct pci_dev *child;
|
||||
|
||||
if (aspm_force)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Clear any ASPM setup that the firmware has carried out on this bus
|
||||
*/
|
||||
list_for_each_entry(child, &bus->devices, bus_list) {
|
||||
__pci_disable_link_state(child, PCIE_LINK_STATE_L0S |
|
||||
PCIE_LINK_STATE_L1 |
|
||||
PCIE_LINK_STATE_CLKPM,
|
||||
false, true);
|
||||
}
|
||||
}
|
||||
|
||||
static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp)
|
||||
{
|
||||
int i;
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
#include <linux/delay.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/of_pci.h>
|
||||
#include <linux/pci_hotplug.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/module.h>
|
||||
|
|
@ -1520,6 +1521,7 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
|
|||
dev->dev.dma_mask = &dev->dma_mask;
|
||||
dev->dev.dma_parms = &dev->dma_parms;
|
||||
dev->dev.coherent_dma_mask = 0xffffffffull;
|
||||
of_pci_dma_configure(dev);
|
||||
|
||||
pci_set_dma_max_seg_size(dev, 65536);
|
||||
pci_set_dma_seg_boundary(dev, 0xffffffff);
|
||||
|
|
@ -1993,6 +1995,7 @@ err_out:
|
|||
kfree(b);
|
||||
return NULL;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_create_root_bus);
|
||||
|
||||
int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
|
||||
{
|
||||
|
|
@ -2087,7 +2090,6 @@ struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
|
|||
if (!found)
|
||||
pci_bus_update_busn_res_end(b, max);
|
||||
|
||||
pci_bus_add_devices(b);
|
||||
return b;
|
||||
}
|
||||
EXPORT_SYMBOL(pci_scan_root_bus);
|
||||
|
|
@ -2123,7 +2125,6 @@ struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
|
|||
b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
|
||||
if (b) {
|
||||
pci_scan_child_bus(b);
|
||||
pci_bus_add_devices(b);
|
||||
} else {
|
||||
pci_free_resource_list(&resources);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3182,7 +3182,7 @@ static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
|
|||
|| nhi->subsystem_vendor != 0x2222
|
||||
|| nhi->subsystem_device != 0x1111)
|
||||
goto out;
|
||||
dev_info(&dev->dev, "quirk: wating for thunderbolt to reestablish pci tunnels...\n");
|
||||
dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
|
||||
device_pm_wait_for_dev(&dev->dev, &nhi->dev);
|
||||
out:
|
||||
pci_dev_put(nhi);
|
||||
|
|
@ -3822,6 +3822,38 @@ static const struct pci_dev_acs_enabled {
|
|||
{ PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
|
||||
/* 82580 */
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
|
||||
/* 82576 */
|
||||
{ PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
|
||||
/* 82575 */
|
||||
{ PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
|
||||
/* I350 */
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
|
||||
/* 82571 (Quads omitted due to non-ACS switch) */
|
||||
{ PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
|
||||
{ PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
|
||||
/* Intel PCH root ports */
|
||||
{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
|
||||
{ 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
|
||||
{ 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
|
||||
|
|
|
|||
|
|
@ -139,6 +139,7 @@ void pci_stop_root_bus(struct pci_bus *bus)
|
|||
/* stop the host bridge */
|
||||
device_release_driver(&host_bridge->dev);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_stop_root_bus);
|
||||
|
||||
void pci_remove_root_bus(struct pci_bus *bus)
|
||||
{
|
||||
|
|
@ -158,3 +159,4 @@ void pci_remove_root_bus(struct pci_bus *bus)
|
|||
/* remove the host bridge */
|
||||
device_unregister(&host_bridge->dev);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_remove_root_bus);
|
||||
|
|
|
|||
|
|
@ -1750,3 +1750,4 @@ void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
|
|||
__pci_bus_assign_resources(bus, &add_list, NULL);
|
||||
BUG_ON(!list_empty(&add_list));
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);
|
||||
|
|
|
|||
|
|
@ -65,3 +65,4 @@ void pci_fixup_irqs(u8 (*swizzle)(struct pci_dev *, u8 *),
|
|||
for_each_pci_dev(dev)
|
||||
pdev_fixup_irq(dev, swizzle, map_irq);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_fixup_irqs);
|
||||
|
|
|
|||
|
|
@ -120,6 +120,7 @@ int pci_claim_resource(struct pci_dev *dev, int resource)
|
|||
if (!root) {
|
||||
dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
|
||||
resource, res);
|
||||
res->flags |= IORESOURCE_UNSET;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
@ -127,6 +128,7 @@ int pci_claim_resource(struct pci_dev *dev, int resource)
|
|||
if (conflict) {
|
||||
dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
|
||||
resource, res, conflict->name, conflict);
|
||||
res->flags |= IORESOURCE_UNSET;
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue