mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 01:23:00 -04:00
Blackfin arch: to do some consolidation of common code and common name spaces
now all BLKFIN should be BFIN, should be no functional changes. Signed-off-by: Robin Getz <[email protected]> Signed-off-by: Bryan Wu <[email protected]>
This commit is contained in:
Robin Getz
Bryan Wu
parent
a298049180
commit
3bebca2d20
31 changed files with 289 additions and 391 deletions
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@ -48,9 +48,9 @@ extern void blackfin_dflush_page(void *);
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static inline void flush_icache_range(unsigned start, unsigned end)
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{
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#if defined(CONFIG_BLKFIN_DCACHE) && defined(CONFIG_BLKFIN_CACHE)
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#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_ICACHE)
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# if defined(CONFIG_BLKFIN_WT)
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# if defined(CONFIG_BFIN_WT)
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blackfin_icache_flush_range((start), (end));
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# else
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blackfin_icache_dcache_flush_range((start), (end));
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@ -58,10 +58,10 @@ static inline void flush_icache_range(unsigned start, unsigned end)
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#else
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# if defined(CONFIG_BLKFIN_CACHE)
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# if defined(CONFIG_BFIN_ICACHE)
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blackfin_icache_flush_range((start), (end));
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# endif
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# if defined(CONFIG_BLKFIN_DCACHE)
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# if defined(CONFIG_BFIN_DCACHE)
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blackfin_dcache_flush_range((start), (end));
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# endif
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@ -74,12 +74,12 @@ do { memcpy(dst, src, len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len)
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#if defined(CONFIG_BLKFIN_DCACHE)
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#if defined(CONFIG_BFIN_DCACHE)
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# define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end))
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#else
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# define invalidate_dcache_range(start,end) do { } while (0)
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#endif
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#if defined(CONFIG_BLKFIN_DCACHE) && defined(CONFIG_BLKFIN_WB)
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#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_WB)
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# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end))
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# define flush_dcache_page(page) blackfin_dflush_page(page_address(page))
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#else
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@ -87,4 +87,4 @@ do { memcpy(dst, src, len); \
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# define flush_dcache_page(page) do { } while (0)
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#endif
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#endif /* _BLACKFIN_CACHEFLUSH_H */
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#endif /* _BLACKFIN_ICACHEFLUSH_H */
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@ -1,18 +1,93 @@
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/************************************************************************
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/*
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* File: include/asm-blackfin/cplb.h
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* Based on: include/asm-blackfin/mach-bf537/bf537.h
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* Author: Robin Getz <rgetz@blackfin.uclinux.org>
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*
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* cplb.h
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* Created: 2000
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* Description: Common CPLB definitions for CPLB init
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*
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* (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.
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* Modified:
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* Copyright 2004-2007 Analog Devices Inc.
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*
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************************************************************************/
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/* Defines necessary for cplb initialisation routines. */
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _CPLB_H
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#define _CPLB_H
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# include <asm/blackfin.h>
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#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
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#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
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#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
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#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
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/*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/
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#if ANOMALY_05000158
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#define ANOMALY_05000158_WORKAROUND 0x200
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#else
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#define ANOMALY_05000158_WORKAROUND 0x0
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#endif
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#define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
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#ifdef CONFIG_BFIN_WB /*Write Back Policy */
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#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON)
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#else /*Write Through */
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#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
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#endif
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#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
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#define SDRAM_DNON_CHBL (CPLB_COMMON)
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#define SDRAM_EBIU (CPLB_COMMON)
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#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
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#define SIZE_1K 0x00000400 /* 1K */
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#define SIZE_4K 0x00001000 /* 4K */
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#define SIZE_1M 0x00100000 /* 1M */
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#define SIZE_4M 0x00400000 /* 4M */
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#define MAX_CPLBS (16 * 2)
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/*
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* Number of required data CPLB switchtable entries
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* MEMSIZE / 4 (we mostly install 4M page size CPLBs
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* approx 16 for smaller 1MB page size CPLBs for allignment purposes
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* 1 for L1 Data Memory
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* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
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* 1 for ASYNC Memory
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*/
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#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
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/*
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* Number of required instruction CPLB switchtable entries
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* MEMSIZE / 4 (we mostly install 4M page size CPLBs
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* approx 12 for smaller 1MB page size CPLBs for allignment purposes
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* 1 for L1 Instruction Memory
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* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
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*/
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#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
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#define CPLB_ENABLE_ICACHE_P 0
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#define CPLB_ENABLE_DCACHE_P 1
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#define CPLB_ENABLE_DCACHE2_P 2
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@ -39,8 +114,6 @@
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#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
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#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
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#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
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#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
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#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
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#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
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@ -52,12 +52,12 @@
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/***************************/
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#define BLKFIN_DSUBBANKS 4
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#define BLKFIN_DWAYS 2
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#define BLKFIN_DLINES 64
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#define BLKFIN_ISUBBANKS 4
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#define BLKFIN_IWAYS 4
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#define BLKFIN_ILINES 32
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#define BFIN_DSUBBANKS 4
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#define BFIN_DWAYS 2
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#define BFIN_DLINES 64
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#define BFIN_ISUBBANKS 4
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#define BFIN_IWAYS 4
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#define BFIN_ILINES 32
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#define WAY0_L 0x1
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#define WAY1_L 0x2
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@ -167,10 +167,10 @@
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#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
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#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
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/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
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/*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/
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#define ANOMALY_05000158_WORKAROUND 0x200
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#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
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#ifdef CONFIG_BFIN_WB /*Write Back Policy */
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#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
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| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
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#else /*Write Through */
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@ -51,10 +51,10 @@
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/* Level 1 Memory */
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#ifdef CONFIG_BLKFIN_CACHE
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#define BLKFIN_ICACHESIZE (16*1024)
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#ifdef CONFIG_BFIN_ICACHE
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#define BFIN_ICACHESIZE (16*1024)
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#else
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#define BLKFIN_ICACHESIZE (0*1024)
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#define BFIN_ICACHESIZE (0*1024)
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#endif
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/* Memory Map for ADSP-BF533 processors */
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@ -64,35 +64,35 @@
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#define L1_DATA_A_START 0xFF800000
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#define L1_DATA_B_START 0xFF900000
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#ifdef CONFIG_BLKFIN_CACHE
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#ifdef CONFIG_BFIN_ICACHE
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#define L1_CODE_LENGTH (0x14000 - 0x4000)
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#else
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#define L1_CODE_LENGTH 0x14000
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#endif
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#ifdef CONFIG_BLKFIN_DCACHE
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#ifdef CONFIG_BFIN_DCACHE
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#ifdef CONFIG_BLKFIN_DCACHE_BANKA
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#ifdef CONFIG_BFIN_DCACHE_BANKA
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#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
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#define L1_DATA_B_LENGTH 0x8000
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#define BLKFIN_DCACHESIZE (16*1024)
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#define BLKFIN_DSUPBANKS 1
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#define BFIN_DCACHESIZE (16*1024)
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#define BFIN_DSUPBANKS 1
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#else
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#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
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#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
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#define BLKFIN_DCACHESIZE (32*1024)
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#define BLKFIN_DSUPBANKS 2
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#define BFIN_DCACHESIZE (32*1024)
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#define BFIN_DSUPBANKS 2
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#endif
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#else
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#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH 0x8000
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#define L1_DATA_B_LENGTH 0x8000
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#define BLKFIN_DCACHESIZE (0*1024)
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#define BLKFIN_DSUPBANKS 0
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#endif /*CONFIG_BLKFIN_DCACHE*/
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#define BFIN_DCACHESIZE (0*1024)
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#define BFIN_DSUPBANKS 0
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#endif /*CONFIG_BFIN_DCACHE*/
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#endif
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/* Memory Map for ADSP-BF532 processors */
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@ -102,36 +102,36 @@
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#define L1_DATA_A_START 0xFF804000
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#define L1_DATA_B_START 0xFF904000
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#ifdef CONFIG_BLKFIN_CACHE
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#ifdef CONFIG_BFIN_ICACHE
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#define L1_CODE_LENGTH (0xC000 - 0x4000)
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#else
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#define L1_CODE_LENGTH 0xC000
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#endif
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#ifdef CONFIG_BLKFIN_DCACHE
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#ifdef CONFIG_BFIN_DCACHE
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#ifdef CONFIG_BLKFIN_DCACHE_BANKA
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#ifdef CONFIG_BFIN_DCACHE_BANKA
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#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
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#define L1_DATA_B_LENGTH 0x4000
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#define BLKFIN_DCACHESIZE (16*1024)
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#define BLKFIN_DSUPBANKS 1
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#define BFIN_DCACHESIZE (16*1024)
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#define BFIN_DSUPBANKS 1
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#else
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#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
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#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
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#define BLKFIN_DCACHESIZE (32*1024)
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#define BLKFIN_DSUPBANKS 2
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#define BFIN_DCACHESIZE (32*1024)
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#define BFIN_DSUPBANKS 2
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#endif
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#else
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#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH 0x4000
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#define L1_DATA_B_LENGTH 0x4000
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#define BLKFIN_DCACHESIZE (0*1024)
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#define BLKFIN_DSUPBANKS 0
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#endif /*CONFIG_BLKFIN_DCACHE*/
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#define BFIN_DCACHESIZE (0*1024)
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#define BFIN_DSUPBANKS 0
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#endif /*CONFIG_BFIN_DCACHE*/
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#endif
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/* Memory Map for ADSP-BF531 processors */
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@ -144,16 +144,16 @@
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#define L1_DATA_B_LENGTH 0x0000
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#ifdef CONFIG_BLKFIN_DCACHE
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#ifdef CONFIG_BFIN_DCACHE
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#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
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#define BLKFIN_DCACHESIZE (16*1024)
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#define BLKFIN_DSUPBANKS 1
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#define BFIN_DCACHESIZE (16*1024)
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#define BFIN_DSUPBANKS 1
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#else
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#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH 0x4000
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#define BLKFIN_DCACHESIZE (0*1024)
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#define BLKFIN_DSUPBANKS 0
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#define BFIN_DCACHESIZE (0*1024)
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#define BFIN_DSUPBANKS 0
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#endif
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#endif
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@ -133,6 +133,7 @@
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000125 (0)
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#define ANOMALY_05000158 (0)
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#define ANOMALY_05000183 (0)
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#define ANOMALY_05000198 (0)
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#define ANOMALY_05000266 (0)
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@ -62,12 +62,12 @@
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/***************************/
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#define BLKFIN_DSUBBANKS 4
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#define BLKFIN_DWAYS 2
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#define BLKFIN_DLINES 64
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#define BLKFIN_ISUBBANKS 4
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#define BLKFIN_IWAYS 4
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#define BLKFIN_ILINES 32
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#define BFIN_DSUBBANKS 4
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#define BFIN_DWAYS 2
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#define BFIN_DLINES 64
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#define BFIN_ISUBBANKS 4
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#define BFIN_IWAYS 4
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#define BFIN_ILINES 32
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#define WAY0_L 0x1
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#define WAY1_L 0x2
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@ -138,59 +138,4 @@
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#define CPUID 0x0
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#endif
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#if (CONFIG_MEM_SIZE % 4)
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#error "SDRAM mem size must be multible of 4MB"
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#endif
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#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
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#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
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#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
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#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
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/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
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#define ANOMALY_05000158_WORKAROUND 0x200
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#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
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#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
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| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
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#else /*Write Through */
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#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
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| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
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#endif
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#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
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#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
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#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
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#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
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#define SIZE_1K 0x00000400 /* 1K */
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#define SIZE_4K 0x00001000 /* 4K */
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#define SIZE_1M 0x00100000 /* 1M */
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#define SIZE_4M 0x00400000 /* 4M */
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#define MAX_CPLBS (16 * 2)
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/*
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* Number of required data CPLB switchtable entries
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||||
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
|
||||
* approx 16 for smaller 1MB page size CPLBs for allignment purposes
|
||||
* 1 for L1 Data Memory
|
||||
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
|
||||
* 1 for ASYNC Memory
|
||||
*/
|
||||
|
||||
|
||||
#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
|
||||
|
||||
/*
|
||||
* Number of required instruction CPLB switchtable entries
|
||||
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
|
||||
* approx 12 for smaller 1MB page size CPLBs for allignment purposes
|
||||
* 1 for L1 Instruction Memory
|
||||
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
|
||||
*/
|
||||
|
||||
#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
|
||||
|
||||
#endif /* __MACH_BF537_H__ */
|
||||
|
|
|
|||
|
|
@ -52,10 +52,10 @@
|
|||
|
||||
/* Memory Map for ADSP-BF537 processors */
|
||||
|
||||
#ifdef CONFIG_BLKFIN_CACHE
|
||||
#define BLKFIN_ICACHESIZE (16*1024)
|
||||
#ifdef CONFIG_BFIN_ICACHE
|
||||
#define BFIN_ICACHESIZE (16*1024)
|
||||
#else
|
||||
#define BLKFIN_ICACHESIZE (0*1024)
|
||||
#define BFIN_ICACHESIZE (0*1024)
|
||||
#endif
|
||||
|
||||
|
||||
|
|
@ -66,29 +66,29 @@
|
|||
|
||||
#define L1_CODE_LENGTH 0xC000
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE_BANKA
|
||||
#ifdef CONFIG_BFIN_DCACHE_BANKA
|
||||
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BLKFIN_DCACHESIZE (16*1024)
|
||||
#define BLKFIN_DSUPBANKS 1
|
||||
#define BFIN_DCACHESIZE (16*1024)
|
||||
#define BFIN_DSUPBANKS 1
|
||||
#else
|
||||
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
|
||||
#define BLKFIN_DCACHESIZE (32*1024)
|
||||
#define BLKFIN_DSUPBANKS 2
|
||||
#define BFIN_DCACHESIZE (32*1024)
|
||||
#define BFIN_DSUPBANKS 2
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH 0x8000
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BLKFIN_DCACHESIZE (0*1024)
|
||||
#define BLKFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BLKFIN_DCACHE*/
|
||||
#define BFIN_DCACHESIZE (0*1024)
|
||||
#define BFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BFIN_DCACHE*/
|
||||
|
||||
#endif /*CONFIG_BF537*/
|
||||
|
||||
|
|
@ -102,30 +102,30 @@
|
|||
#define L1_CODE_LENGTH 0xC000
|
||||
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE_BANKA
|
||||
#ifdef CONFIG_BFIN_DCACHE_BANKA
|
||||
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH 0x4000
|
||||
#define BLKFIN_DCACHESIZE (16*1024)
|
||||
#define BLKFIN_DSUPBANKS 1
|
||||
#define BFIN_DCACHESIZE (16*1024)
|
||||
#define BFIN_DSUPBANKS 1
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
|
||||
#define BLKFIN_DCACHESIZE (32*1024)
|
||||
#define BLKFIN_DSUPBANKS 2
|
||||
#define BFIN_DCACHESIZE (32*1024)
|
||||
#define BFIN_DSUPBANKS 2
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH 0x4000
|
||||
#define L1_DATA_B_LENGTH 0x4000
|
||||
#define BLKFIN_DCACHESIZE (0*1024)
|
||||
#define BLKFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BLKFIN_DCACHE*/
|
||||
#define BFIN_DCACHESIZE (0*1024)
|
||||
#define BFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BFIN_DCACHE*/
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -138,30 +138,30 @@
|
|||
|
||||
#define L1_CODE_LENGTH 0xC000
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE_BANKA
|
||||
#ifdef CONFIG_BFIN_DCACHE_BANKA
|
||||
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BLKFIN_DCACHESIZE (16*1024)
|
||||
#define BLKFIN_DSUPBANKS 1
|
||||
#define BFIN_DCACHESIZE (16*1024)
|
||||
#define BFIN_DSUPBANKS 1
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
|
||||
#define BLKFIN_DCACHESIZE (32*1024)
|
||||
#define BLKFIN_DSUPBANKS 2
|
||||
#define BFIN_DCACHESIZE (32*1024)
|
||||
#define BFIN_DSUPBANKS 2
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH 0x8000
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BLKFIN_DCACHESIZE (0*1024)
|
||||
#define BLKFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BLKFIN_DCACHE*/
|
||||
#define BFIN_DCACHESIZE (0*1024)
|
||||
#define BFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BFIN_DCACHE*/
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -52,12 +52,12 @@
|
|||
/***************************/
|
||||
|
||||
|
||||
#define BLKFIN_DSUBBANKS 4
|
||||
#define BLKFIN_DWAYS 2
|
||||
#define BLKFIN_DLINES 64
|
||||
#define BLKFIN_ISUBBANKS 4
|
||||
#define BLKFIN_IWAYS 4
|
||||
#define BLKFIN_ILINES 32
|
||||
#define BFIN_DSUBBANKS 4
|
||||
#define BFIN_DWAYS 2
|
||||
#define BFIN_DLINES 64
|
||||
#define BFIN_ISUBBANKS 4
|
||||
#define BFIN_IWAYS 4
|
||||
#define BFIN_ILINES 32
|
||||
|
||||
#define WAY0_L 0x1
|
||||
#define WAY1_L 0x2
|
||||
|
|
@ -126,59 +126,4 @@
|
|||
#define CPUID 0x0
|
||||
#endif
|
||||
|
||||
#if (CONFIG_MEM_SIZE % 4)
|
||||
#error "SDRAM mem size must be multible of 4MB"
|
||||
#endif
|
||||
|
||||
#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
|
||||
#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
|
||||
#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
||||
#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
|
||||
|
||||
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
|
||||
|
||||
#define ANOMALY_05000158_WORKAROUND 0x200
|
||||
#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
|
||||
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
|
||||
| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
|
||||
#else /*Write Through */
|
||||
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
|
||||
| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
|
||||
#endif
|
||||
|
||||
|
||||
#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
|
||||
#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
|
||||
#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
|
||||
#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
|
||||
|
||||
#define SIZE_1K 0x00000400 /* 1K */
|
||||
#define SIZE_4K 0x00001000 /* 4K */
|
||||
#define SIZE_1M 0x00100000 /* 1M */
|
||||
#define SIZE_4M 0x00400000 /* 4M */
|
||||
|
||||
#define MAX_CPLBS (16 * 2)
|
||||
|
||||
/*
|
||||
* Number of required data CPLB switchtable entries
|
||||
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
|
||||
* approx 16 for smaller 1MB page size CPLBs for allignment purposes
|
||||
* 1 for L1 Data Memory
|
||||
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
|
||||
* 1 for ASYNC Memory
|
||||
*/
|
||||
|
||||
|
||||
#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
|
||||
|
||||
/*
|
||||
* Number of required instruction CPLB switchtable entries
|
||||
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
|
||||
* approx 12 for smaller 1MB page size CPLBs for allignment purposes
|
||||
* 1 for L1 Instruction Memory
|
||||
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
|
||||
*/
|
||||
|
||||
#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
|
||||
|
||||
#endif /* __MACH_BF48_H__ */
|
||||
|
|
|
|||
|
|
@ -51,10 +51,10 @@
|
|||
/* Level 1 Memory */
|
||||
|
||||
/* Memory Map for ADSP-BF548 processors */
|
||||
#ifdef CONFIG_BLKFIN_ICACHE
|
||||
#define BLKFIN_ICACHESIZE (16*1024)
|
||||
#ifdef CONFIG_BFIN_ICACHE
|
||||
#define BFIN_ICACHESIZE (16*1024)
|
||||
#else
|
||||
#define BLKFIN_ICACHESIZE (0*1024)
|
||||
#define BFIN_ICACHESIZE (0*1024)
|
||||
#endif
|
||||
|
||||
#define L1_CODE_START 0xFFA00000
|
||||
|
|
@ -63,29 +63,29 @@
|
|||
|
||||
#define L1_CODE_LENGTH 0xC000
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE_BANKA
|
||||
#ifdef CONFIG_BFIN_DCACHE_BANKA
|
||||
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BLKFIN_DCACHESIZE (16*1024)
|
||||
#define BLKFIN_DSUPBANKS 1
|
||||
#define BFIN_DCACHESIZE (16*1024)
|
||||
#define BFIN_DSUPBANKS 1
|
||||
#else
|
||||
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
|
||||
#define BLKFIN_DCACHESIZE (32*1024)
|
||||
#define BLKFIN_DSUPBANKS 2
|
||||
#define BFIN_DCACHESIZE (32*1024)
|
||||
#define BFIN_DSUPBANKS 2
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH 0x8000
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BLKFIN_DCACHESIZE (0*1024)
|
||||
#define BLKFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BLKFIN_DCACHE*/
|
||||
#define BFIN_DCACHESIZE (0*1024)
|
||||
#define BFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BFIN_DCACHE*/
|
||||
|
||||
/* Scratch Pad Memory */
|
||||
|
||||
|
|
|
|||
|
|
@ -73,13 +73,13 @@
|
|||
*/
|
||||
|
||||
|
||||
#define BLKFIN_ISUBBANKS 4
|
||||
#define BLKFIN_IWAYS 4
|
||||
#define BLKFIN_ILINES 32
|
||||
#define BFIN_ISUBBANKS 4
|
||||
#define BFIN_IWAYS 4
|
||||
#define BFIN_ILINES 32
|
||||
|
||||
#define BLKFIN_DSUBBANKS 4
|
||||
#define BLKFIN_DWAYS 2
|
||||
#define BLKFIN_DLINES 64
|
||||
#define BFIN_DSUBBANKS 4
|
||||
#define BFIN_DWAYS 2
|
||||
#define BFIN_DLINES 64
|
||||
|
||||
#define WAY0_L 0x1
|
||||
#define WAY1_L 0x2
|
||||
|
|
@ -239,83 +239,4 @@
|
|||
#define CPUID 0x0
|
||||
#endif
|
||||
|
||||
#if (CONFIG_MEM_SIZE % 4)
|
||||
#error "SDRAM memory size must be a multiple of 4MB!"
|
||||
#endif
|
||||
#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
|
||||
#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
|
||||
#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
||||
#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
|
||||
|
||||
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
|
||||
|
||||
#define ANOMALY_05000158_WORKAROUND 0x200
|
||||
#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
|
||||
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
|
||||
| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
|
||||
#else /*Write Through */
|
||||
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_DIRTY \
|
||||
| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
|
||||
#endif
|
||||
|
||||
|
||||
#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
|
||||
#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
|
||||
#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
|
||||
#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
|
||||
|
||||
#define L2_MEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
|
||||
|
||||
#define SIZE_1K 0x00000400 /* 1K */
|
||||
#define SIZE_4K 0x00001000 /* 4K */
|
||||
#define SIZE_1M 0x00100000 /* 1M */
|
||||
#define SIZE_4M 0x00400000 /* 4M */
|
||||
|
||||
#define MAX_CPLBS (16 * 2)
|
||||
|
||||
/*
|
||||
* Number of required data CPLB switchtable entries
|
||||
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
|
||||
* approx 16 for smaller 1MB page size CPLBs for allignment purposes
|
||||
* 1 for L1 Data Memory
|
||||
* 1 for L2 Data Memory
|
||||
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
|
||||
* 64 for ASYNC Memory
|
||||
*/
|
||||
|
||||
|
||||
#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 + 64) * 2)
|
||||
|
||||
/*
|
||||
* Number of required instruction CPLB switchtable entries
|
||||
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
|
||||
* approx 12 for smaller 1MB page size CPLBs for allignment purposes
|
||||
* 1 for L1 Instruction Memory
|
||||
* 1 for L2 Instruction Memory
|
||||
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
|
||||
*/
|
||||
|
||||
#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)
|
||||
|
||||
#if 0 /* comment by mhfan */
|
||||
/* Event Vector Table Address */
|
||||
#define EVT_EMULATION_ADDR 0xffe02000
|
||||
#define EVT_RESET_ADDR 0xffe02004
|
||||
#define EVT_NMI_ADDR 0xffe02008
|
||||
#define EVT_EXCEPTION_ADDR 0xffe0200c
|
||||
#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010
|
||||
#define EVT_HARDWARE_ERROR_ADDR 0xffe02014
|
||||
#define EVT_TIMER_ADDR 0xffe02018
|
||||
#define EVT_IVG7_ADDR 0xffe0201c
|
||||
#define EVT_IVG8_ADDR 0xffe02020
|
||||
#define EVT_IVG9_ADDR 0xffe02024
|
||||
#define EVT_IVG10_ADDR 0xffe02028
|
||||
#define EVT_IVG11_ADDR 0xffe0202c
|
||||
#define EVT_IVG12_ADDR 0xffe02030
|
||||
#define EVT_IVG13_ADDR 0xffe02034
|
||||
#define EVT_IVG14_ADDR 0xffe02038
|
||||
#define EVT_IVG15_ADDR 0xffe0203c
|
||||
#define EVT_OVERRIDE_ADDR 0xffe02100
|
||||
#endif /* comment by mhfan */
|
||||
|
||||
#endif /* __MACH_BF561_H__ */
|
||||
|
|
|
|||
|
|
@ -21,10 +21,10 @@
|
|||
|
||||
/* Level 1 Memory */
|
||||
|
||||
#ifdef CONFIG_BLKFIN_CACHE
|
||||
#define BLKFIN_ICACHESIZE (16*1024)
|
||||
#ifdef CONFIG_BFIN_ICACHE
|
||||
#define BFIN_ICACHESIZE (16*1024)
|
||||
#else
|
||||
#define BLKFIN_ICACHESIZE (0*1024)
|
||||
#define BFIN_ICACHESIZE (0*1024)
|
||||
#endif
|
||||
|
||||
/* Memory Map for ADSP-BF561 processors */
|
||||
|
|
@ -36,29 +36,29 @@
|
|||
|
||||
#define L1_CODE_LENGTH 0x4000
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
|
||||
#ifdef CONFIG_BLKFIN_DCACHE_BANKA
|
||||
#ifdef CONFIG_BFIN_DCACHE_BANKA
|
||||
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BLKFIN_DCACHESIZE (16*1024)
|
||||
#define BLKFIN_DSUPBANKS 1
|
||||
#define BFIN_DCACHESIZE (16*1024)
|
||||
#define BFIN_DSUPBANKS 1
|
||||
#else
|
||||
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
|
||||
#define BLKFIN_DCACHESIZE (32*1024)
|
||||
#define BLKFIN_DSUPBANKS 2
|
||||
#define BFIN_DCACHESIZE (32*1024)
|
||||
#define BFIN_DSUPBANKS 2
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH 0x8000
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BLKFIN_DCACHESIZE (0*1024)
|
||||
#define BLKFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BLKFIN_DCACHE*/
|
||||
#define BFIN_DCACHESIZE (0*1024)
|
||||
#define BFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BFIN_DCACHE*/
|
||||
#endif
|
||||
|
||||
/* Level 2 Memory */
|
||||
|
|
|
|||
|
|
@ -27,7 +27,8 @@
|
|||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _BFIN_CLOCKS_H
|
||||
#define _BFIN_CLOCKS_H
|
||||
|
||||
#ifdef CONFIG_CCLK_DIV_1
|
||||
# define CONFIG_CCLK_ACT_DIV CCLK_DIV1
|
||||
|
|
@ -66,3 +67,4 @@
|
|||
# define CONFIG_VCO_MULT 0
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -639,6 +639,7 @@
|
|||
#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access
|
||||
* allowed (user mode)
|
||||
*/
|
||||
|
||||
#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
|
||||
#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
|
||||
#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
|
||||
|
|
@ -671,6 +672,8 @@
|
|||
*/
|
||||
#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
|
||||
|
||||
#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
|
||||
|
||||
/* TBUFCTL Masks */
|
||||
#define TBUFPWR 0x0001
|
||||
#define TBUFEN 0x0002
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
#include <asm-generic/4level-fixup.h>
|
||||
|
||||
#include <asm/page.h>
|
||||
#include <asm/cplb.h>
|
||||
#include <asm/mach-common/def_LPBlackfin.h>
|
||||
|
||||
typedef pte_t *pte_addr_t;
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ extern unsigned long irq_flags;
|
|||
); \
|
||||
} while (0)
|
||||
|
||||
#if ANOMALY_05000244 && defined(CONFIG_BLKFIN_CACHE)
|
||||
#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
|
||||
# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
|
||||
#else
|
||||
# define NOP_PAD_ANOMALY_05000244
|
||||
|
|
|
|||
Loading…
Reference in a new issue