From 37ec72ea91a32df1564e66e7725cf0679e331220 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Mon, 24 Aug 2020 19:49:29 +0530 Subject: [PATCH 1/4] ARM: dts: msm: Add device node for watchdog in SM6150 Add device node for hardware msm-watchdog, this is needed to report system lockups related bugs in the kernel. Change-Id: I9afbed8e89fa9c70c87978c4201214c752fd8e7a --- qcom/sm6150.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index f4c7ab4a979f..c4deb69159cb 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1845,6 +1845,18 @@ vote = <67>; }; }; + + wdog: qcom,wdt@17c10000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17c10000 0x1000>; + reg-names = "wdt-base"; + interrupts = , + ; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; }; #include "sm6150-qupv3.dtsi" From 71d7e2b857e83174cf18fc7dcab5bceceeb35c1c Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Fri, 18 Dec 2020 09:02:00 +0530 Subject: [PATCH 2/4] ARM: dts: msm: Add DCVS device nodes to SM6150 Add bw_hwmon and memlat device tree nodes to enable DCVS support to SM6150. Change-Id: I0b8fcdfa878df1cd8f0492114b65c9378656026b --- qcom/sm6150.dtsi | 256 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 256 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index c4deb69159cb..653ea995e5e8 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -14,6 +14,12 @@ #include #include +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} +#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\ + opp-hz = /bits/ 64 ;\ + opp-supported-hw = ;} + / { model = "Qualcomm Technologies, Inc. SM6150"; compatible = "qcom,sm6150"; @@ -631,6 +637,256 @@ }; }; + llcc_bw_opp_table: llcc-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ + BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */ + BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */ + BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */ + BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */ + BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */ + }; + + cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw { + compatible = "qcom,devfreq-icc"; + governor = "performance"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &gem_noc SLAVE_LLCC>; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x90b6300 0x300>, <0x90b6200 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_cpu_llcc_bw>; + qcom,count-unit = <0x10000>; + }; + + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ + BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ + BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ + BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ + BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ + BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ + BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ + BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */ + BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ + BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ + }; + + cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@90cd000 { + compatible = "qcom,bimc-bwmon5"; + reg = <0x90cd000 0x1000>; + reg-names = "base"; + interrupts = ; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_llcc_ddr_bw>; + qcom,count-unit = <0x10000>; + }; + + cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18321110 0x500>; + reg-names = "ftbl-base"; + qcom,ftbl-row-size = <0x20>; + governor = "performance"; + interconnects = <&osm_l3 MASTER_OSM_L3_APPS + &osm_l3 SLAVE_OSM_L3_CLUSTER0>; + }; + + cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl { + qcom,core-dev-table = + < 576000 300000000 >, + < 1017600 556800000 >, + < 1209660 806400000 >, + < 1516800 940800000 >, + < 1804800 1363200000 >; + }; + + cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat { + compatible = "qcom,devfreq-icc"; + governor = "performance"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &gem_noc SLAVE_LLCC>; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + + cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,target-dev = <&cpu0_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,stall-cycle-ev = <0xE7>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,target-dev = <&cpu0_cpu_llcc_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,stall-cycle-ev = <0xE7>; + qcom,core-dev-table = + < 748000 MHZ_TO_MBPS(150, 16) >, + < 1209600 MHZ_TO_MBPS(300, 16) >, + < 1516800 MHZ_TO_MBPS(466, 16) >, + < 1804800 MHZ_TO_MBPS(600, 16) >; + }; + + cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,target-dev = <&cpu0_llcc_ddr_lat>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 748000 MHZ_TO_MBPS( 300, 4) >, + < 1017600 MHZ_TO_MBPS( 451, 4) >, + < 1209600 MHZ_TO_MBPS( 547, 4) >, + < 1516800 MHZ_TO_MBPS( 768, 4) >, + < 1804800 MHZ_TO_MBPS(1017, 4) >; + }; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 748800 MHZ_TO_MBPS( 300, 4) >, + < 1209600 MHZ_TO_MBPS( 451, 4) >, + < 1593600 MHZ_TO_MBPS( 547, 4) >, + < 1804800 MHZ_TO_MBPS( 768, 4) >; + }; + }; + + cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18321110 0x500>; + reg-names = "ftbl-base"; + qcom,ftbl-row-size = <0x20>; + governor = "performance"; + interconnects = <&osm_l3 MASTER_OSM_L3_APPS + &osm_l3 SLAVE_OSM_L3_CLUSTER1>; + }; + + cpu6_cpu_l3_tbl: qcom,cpu6_cpu_l3_tbl { + qcom,core-dev-table = + < 1017600 556800000 >, + < 1209600 806400000 >, + < 1516800 940800000 >, + < 1708800 1209600000 >, + < 2208000 1363200000 >; + }; + + cpu6_cpu_llcc_lat: qcom,cpu6-cpu-llcc-lat { + compatible = "qcom,devfreq-icc"; + governor = "performance"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &gem_noc SLAVE_LLCC>; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu6_llcc_ddr_lat: qcom,cpu6-llcc-ddr-lat { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu6_memlat_cpugrp: qcom,cpu6-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU6 &CPU7>; + + cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,target-dev = <&cpu6_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,stall-cycle-ev = <0x15E>; + qcom,core-dev-table = <&cpu6_cpu_l3_tbl>; + }; + + cpu6_cpu_llcc_latmon: qcom,cpu6-cpu-llcc-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,target-dev = <&cpu6_cpu_llcc_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,stall-cycle-ev = <0x15E>; + qcom,core-dev-table = + < 768000 MHZ_TO_MBPS(300, 16) >, + < 1017600 MHZ_TO_MBPS(466, 16) >, + < 1209600 MHZ_TO_MBPS(600, 16) >, + < 1708800 MHZ_TO_MBPS(806, 16) >, + < 2208000 MHZ_TO_MBPS(933, 16) >; + }; + + cpu6_llcc_ddr_latmon: qcom,cpu6-llcc-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,target-dev = <&cpu6_llcc_ddr_lat>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 768000 MHZ_TO_MBPS( 451, 4) >, + < 1017600 MHZ_TO_MBPS( 547, 4) >, + < 1209600 MHZ_TO_MBPS(1017, 4) >, + < 1708800 MHZ_TO_MBPS(1555, 4) >, + < 2208000 MHZ_TO_MBPS(1804, 4) >; + }; + + cpu6_computemon: qcom,cpu6-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,target-dev = <&cpu6_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1017600 MHZ_TO_MBPS( 300, 4) >, + < 1209600 MHZ_TO_MBPS( 547, 4) >, + < 1516800 MHZ_TO_MBPS( 768, 4) >, + < 1708800 MHZ_TO_MBPS(1017, 4) >, + < 2208000 MHZ_TO_MBPS(1804, 4) >; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm6150-pdc"; reg = <0xb220000 0x30000>, <0x17c000f0 0x60>; From 7a0c8e97da72039f4b90217ae0288625e7f3ae53 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Thu, 21 Jan 2021 18:43:48 +0530 Subject: [PATCH 3/4] ARM: dts: msm: Add PMU device nodes to SM6150 Add LLCC PMU, CPU PMU and DSU PMU device nodes to SM6150. Change-Id: I8985e8c8bcdd76bf2babacbf60c47c7f46b7c3d1 --- qcom/sm6150.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 653ea995e5e8..211d20ade731 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -637,6 +637,12 @@ }; }; + llcc_pmu: llcc-pmu@90cc000 { + compatible = "qcom,llcc-pmu-ver2"; + reg = <0x090cc000 0x300>; + reg-names = "lagg-base"; + }; + llcc_bw_opp_table: llcc-bw-opp-table { compatible = "operating-points-v2"; BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ @@ -928,6 +934,19 @@ }; }; + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = ; + }; + + dsu_pmu@0 { + compatible = "arm,dsu-pmu"; + interrupts = ; + cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, + <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; + }; + qcom,msm-imem@146aa000 { compatible = "qcom,msm-imem"; reg = <0x146aa000 0x1000>; From 17ba41bc3b344c2f499c801bb25dd39ccb8c2738 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Fri, 25 Sep 2020 10:47:37 +0530 Subject: [PATCH 4/4] ARM: dts: msm: Add device node for llcc node on SM6150 Add device node for last level cache controller on SM6150. Change-Id: Id8e6c6ded90e02e594f583aac179222fae359bf5 --- bindings/arm/msm/qcom,llcc.txt | 2 +- qcom/sm6150.dtsi | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/bindings/arm/msm/qcom,llcc.txt b/bindings/arm/msm/qcom,llcc.txt index 6bddb3cbb70c..bf052f36b6de 100644 --- a/bindings/arm/msm/qcom,llcc.txt +++ b/bindings/arm/msm/qcom,llcc.txt @@ -14,7 +14,7 @@ Properties: Definition: must be "qcom,sdm845-llcc" or "qcom,lahaina-llcc" or "qcom,shima-llcc" or "qcom,sdxlemur-llcc" or "qcom,yupik-llcc" or "qcom,sm8150-llcc" - or "qcom,sdmshrike-llcc" + or "qcom,sdmshrike-llcc" or "qcom,sm6150-llcc" "qcom,llcc-v2" must be appended for V2 hardware. - reg: diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 211d20ade731..6460aff6ac7e 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1001,6 +1001,13 @@ clock-frequency = <32768>; }; + cache-controller@9200000 { + compatible = "qcom,sm6150-llcc"; + reg = <0x9200000 0x50000> , <0x9600000 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + cap-based-alloc-and-pwr-collapse; + }; + apps_rsc: rsc@18200000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc";