mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (416 commits) ARM: DMA: add support for DMA debugging ARM: PL011: add DMA burst threshold support for ST variants ARM: PL011: Add support for transmit DMA ARM: PL011: Ensure IRQs are disabled in UART interrupt handler ARM: PL011: Separate hardware FIFO size from TTY FIFO size ARM: PL011: Allow better handling of vendor data ARM: PL011: Ensure error flags are clear at startup ARM: PL011: include revision number in boot-time port printk ARM: vexpress: add sched_clock() for Versatile Express ARM i.MX53: Make MX53 EVK bootable ARM i.MX53: Some bug fix about MX53 MSL code ARM: 6607/1: sa1100: Update platform device registration ARM: 6606/1: sa1100: Fix platform device registration ARM i.MX51: rename IPU irqs ARM i.MX51: Add ipu clock support ARM: imx/mx27_3ds: Add PMIC support ARM: DMA: Replace page_to_dma()/dma_to_page() with pfn_to_dma()/dma_to_pfn() mx51: fix usb clock support MX51: Add support for usb host 2 arch/arm/plat-mxc/ehci.c: fix errors/typos ...
This commit is contained in:
Linus Torvalds
commit
3c0cb7c31c
661 changed files with 30869 additions and 12081 deletions
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@ -7,6 +7,7 @@
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*
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* Copyright 1999 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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* Copyright (C) 2010 ST-Ericsson SA
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -48,6 +49,9 @@
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#include <linux/amba/serial.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/scatterlist.h>
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#include <asm/io.h>
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#include <asm/sizes.h>
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@ -63,21 +67,6 @@
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#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
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#define UART_DUMMY_DR_RX (1 << 16)
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/*
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* We wrap our port structure around the generic uart_port.
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*/
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struct uart_amba_port {
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struct uart_port port;
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struct clk *clk;
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unsigned int im; /* interrupt mask */
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unsigned int old_status;
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unsigned int ifls; /* vendor-specific */
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unsigned int lcrh_tx; /* vendor-specific */
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unsigned int lcrh_rx; /* vendor-specific */
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bool oversampling; /* vendor-specific */
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bool autorts;
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};
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/* There is by now at least one vendor with differing details, so handle it */
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struct vendor_data {
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unsigned int ifls;
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@ -85,6 +74,7 @@ struct vendor_data {
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unsigned int lcrh_tx;
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unsigned int lcrh_rx;
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bool oversampling;
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bool dma_threshold;
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};
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static struct vendor_data vendor_arm = {
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@ -93,6 +83,7 @@ static struct vendor_data vendor_arm = {
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.lcrh_tx = UART011_LCRH,
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.lcrh_rx = UART011_LCRH,
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.oversampling = false,
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.dma_threshold = false,
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};
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static struct vendor_data vendor_st = {
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@ -101,22 +92,535 @@ static struct vendor_data vendor_st = {
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.lcrh_tx = ST_UART011_LCRH_TX,
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.lcrh_rx = ST_UART011_LCRH_RX,
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.oversampling = true,
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.dma_threshold = true,
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};
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/* Deals with DMA transactions */
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struct pl011_dmatx_data {
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struct dma_chan *chan;
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struct scatterlist sg;
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char *buf;
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bool queued;
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};
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/*
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* We wrap our port structure around the generic uart_port.
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*/
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struct uart_amba_port {
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struct uart_port port;
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struct clk *clk;
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const struct vendor_data *vendor;
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unsigned int dmacr; /* dma control reg */
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unsigned int im; /* interrupt mask */
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unsigned int old_status;
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unsigned int fifosize; /* vendor-specific */
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unsigned int lcrh_tx; /* vendor-specific */
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unsigned int lcrh_rx; /* vendor-specific */
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bool autorts;
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char type[12];
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#ifdef CONFIG_DMA_ENGINE
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/* DMA stuff */
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bool using_dma;
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struct pl011_dmatx_data dmatx;
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#endif
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};
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/*
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* All the DMA operation mode stuff goes inside this ifdef.
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* This assumes that you have a generic DMA device interface,
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* no custom DMA interfaces are supported.
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*/
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#ifdef CONFIG_DMA_ENGINE
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#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
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static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
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{
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/* DMA is the sole user of the platform data right now */
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struct amba_pl011_data *plat = uap->port.dev->platform_data;
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struct dma_slave_config tx_conf = {
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.dst_addr = uap->port.mapbase + UART01x_DR,
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.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
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.direction = DMA_TO_DEVICE,
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.dst_maxburst = uap->fifosize >> 1,
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};
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struct dma_chan *chan;
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dma_cap_mask_t mask;
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/* We need platform data */
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if (!plat || !plat->dma_filter) {
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dev_info(uap->port.dev, "no DMA platform data\n");
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return;
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}
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/* Try to acquire a generic DMA engine slave channel */
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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chan = dma_request_channel(mask, plat->dma_filter, plat->dma_tx_param);
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if (!chan) {
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dev_err(uap->port.dev, "no TX DMA channel!\n");
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return;
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}
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dmaengine_slave_config(chan, &tx_conf);
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uap->dmatx.chan = chan;
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dev_info(uap->port.dev, "DMA channel TX %s\n",
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dma_chan_name(uap->dmatx.chan));
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}
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#ifndef MODULE
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/*
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* Stack up the UARTs and let the above initcall be done at device
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* initcall time, because the serial driver is called as an arch
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* initcall, and at this time the DMA subsystem is not yet registered.
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* At this point the driver will switch over to using DMA where desired.
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*/
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struct dma_uap {
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struct list_head node;
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struct uart_amba_port *uap;
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};
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static LIST_HEAD(pl011_dma_uarts);
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static int __init pl011_dma_initcall(void)
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{
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struct list_head *node, *tmp;
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list_for_each_safe(node, tmp, &pl011_dma_uarts) {
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struct dma_uap *dmau = list_entry(node, struct dma_uap, node);
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pl011_dma_probe_initcall(dmau->uap);
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list_del(node);
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kfree(dmau);
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}
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return 0;
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}
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device_initcall(pl011_dma_initcall);
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static void pl011_dma_probe(struct uart_amba_port *uap)
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{
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struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL);
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if (dmau) {
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dmau->uap = uap;
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list_add_tail(&dmau->node, &pl011_dma_uarts);
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}
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}
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#else
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static void pl011_dma_probe(struct uart_amba_port *uap)
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{
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pl011_dma_probe_initcall(uap);
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}
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#endif
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static void pl011_dma_remove(struct uart_amba_port *uap)
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{
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/* TODO: remove the initcall if it has not yet executed */
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if (uap->dmatx.chan)
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dma_release_channel(uap->dmatx.chan);
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}
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/* Forward declare this for the refill routine */
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static int pl011_dma_tx_refill(struct uart_amba_port *uap);
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/*
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* The current DMA TX buffer has been sent.
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* Try to queue up another DMA buffer.
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*/
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static void pl011_dma_tx_callback(void *data)
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{
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struct uart_amba_port *uap = data;
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struct pl011_dmatx_data *dmatx = &uap->dmatx;
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unsigned long flags;
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u16 dmacr;
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spin_lock_irqsave(&uap->port.lock, flags);
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if (uap->dmatx.queued)
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dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
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DMA_TO_DEVICE);
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dmacr = uap->dmacr;
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uap->dmacr = dmacr & ~UART011_TXDMAE;
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writew(uap->dmacr, uap->port.membase + UART011_DMACR);
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/*
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* If TX DMA was disabled, it means that we've stopped the DMA for
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* some reason (eg, XOFF received, or we want to send an X-char.)
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*
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* Note: we need to be careful here of a potential race between DMA
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* and the rest of the driver - if the driver disables TX DMA while
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* a TX buffer completing, we must update the tx queued status to
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* get further refills (hence we check dmacr).
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*/
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if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
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uart_circ_empty(&uap->port.state->xmit)) {
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uap->dmatx.queued = false;
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spin_unlock_irqrestore(&uap->port.lock, flags);
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return;
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}
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if (pl011_dma_tx_refill(uap) <= 0) {
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/*
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* We didn't queue a DMA buffer for some reason, but we
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* have data pending to be sent. Re-enable the TX IRQ.
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*/
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uap->im |= UART011_TXIM;
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writew(uap->im, uap->port.membase + UART011_IMSC);
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}
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spin_unlock_irqrestore(&uap->port.lock, flags);
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}
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/*
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* Try to refill the TX DMA buffer.
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* Locking: called with port lock held and IRQs disabled.
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* Returns:
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* 1 if we queued up a TX DMA buffer.
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* 0 if we didn't want to handle this by DMA
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* <0 on error
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*/
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static int pl011_dma_tx_refill(struct uart_amba_port *uap)
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{
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struct pl011_dmatx_data *dmatx = &uap->dmatx;
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struct dma_chan *chan = dmatx->chan;
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struct dma_device *dma_dev = chan->device;
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struct dma_async_tx_descriptor *desc;
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struct circ_buf *xmit = &uap->port.state->xmit;
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unsigned int count;
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/*
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* Try to avoid the overhead involved in using DMA if the
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* transaction fits in the first half of the FIFO, by using
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* the standard interrupt handling. This ensures that we
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* issue a uart_write_wakeup() at the appropriate time.
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*/
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count = uart_circ_chars_pending(xmit);
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if (count < (uap->fifosize >> 1)) {
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uap->dmatx.queued = false;
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return 0;
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}
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/*
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* Bodge: don't send the last character by DMA, as this
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* will prevent XON from notifying us to restart DMA.
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*/
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count -= 1;
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/* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
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if (count > PL011_DMA_BUFFER_SIZE)
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count = PL011_DMA_BUFFER_SIZE;
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if (xmit->tail < xmit->head)
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memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
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else {
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size_t first = UART_XMIT_SIZE - xmit->tail;
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size_t second = xmit->head;
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memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
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if (second)
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memcpy(&dmatx->buf[first], &xmit->buf[0], second);
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}
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dmatx->sg.length = count;
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if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
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uap->dmatx.queued = false;
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dev_dbg(uap->port.dev, "unable to map TX DMA\n");
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return -EBUSY;
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}
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desc = dma_dev->device_prep_slave_sg(chan, &dmatx->sg, 1, DMA_TO_DEVICE,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc) {
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dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
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uap->dmatx.queued = false;
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/*
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* If DMA cannot be used right now, we complete this
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* transaction via IRQ and let the TTY layer retry.
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*/
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dev_dbg(uap->port.dev, "TX DMA busy\n");
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return -EBUSY;
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}
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/* Some data to go along to the callback */
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desc->callback = pl011_dma_tx_callback;
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desc->callback_param = uap;
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/* All errors should happen at prepare time */
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dmaengine_submit(desc);
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/* Fire the DMA transaction */
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dma_dev->device_issue_pending(chan);
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uap->dmacr |= UART011_TXDMAE;
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writew(uap->dmacr, uap->port.membase + UART011_DMACR);
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uap->dmatx.queued = true;
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/*
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* Now we know that DMA will fire, so advance the ring buffer
|
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* with the stuff we just dispatched.
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*/
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xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
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uap->port.icount.tx += count;
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|
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
|
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uart_write_wakeup(&uap->port);
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return 1;
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}
|
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|
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/*
|
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* We received a transmit interrupt without a pending X-char but with
|
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* pending characters.
|
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* Locking: called with port lock held and IRQs disabled.
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* Returns:
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* false if we want to use PIO to transmit
|
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* true if we queued a DMA buffer
|
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*/
|
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static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
|
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{
|
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if (!uap->using_dma)
|
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return false;
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|
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/*
|
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* If we already have a TX buffer queued, but received a
|
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* TX interrupt, it will be because we've just sent an X-char.
|
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* Ensure the TX DMA is enabled and the TX IRQ is disabled.
|
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*/
|
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if (uap->dmatx.queued) {
|
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uap->dmacr |= UART011_TXDMAE;
|
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writew(uap->dmacr, uap->port.membase + UART011_DMACR);
|
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uap->im &= ~UART011_TXIM;
|
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writew(uap->im, uap->port.membase + UART011_IMSC);
|
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return true;
|
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}
|
||||
|
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/*
|
||||
* We don't have a TX buffer queued, so try to queue one.
|
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* If we succesfully queued a buffer, mask the TX IRQ.
|
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*/
|
||||
if (pl011_dma_tx_refill(uap) > 0) {
|
||||
uap->im &= ~UART011_TXIM;
|
||||
writew(uap->im, uap->port.membase + UART011_IMSC);
|
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return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
/*
|
||||
* Stop the DMA transmit (eg, due to received XOFF).
|
||||
* Locking: called with port lock held and IRQs disabled.
|
||||
*/
|
||||
static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
|
||||
{
|
||||
if (uap->dmatx.queued) {
|
||||
uap->dmacr &= ~UART011_TXDMAE;
|
||||
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Try to start a DMA transmit, or in the case of an XON/OFF
|
||||
* character queued for send, try to get that character out ASAP.
|
||||
* Locking: called with port lock held and IRQs disabled.
|
||||
* Returns:
|
||||
* false if we want the TX IRQ to be enabled
|
||||
* true if we have a buffer queued
|
||||
*/
|
||||
static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
|
||||
{
|
||||
u16 dmacr;
|
||||
|
||||
if (!uap->using_dma)
|
||||
return false;
|
||||
|
||||
if (!uap->port.x_char) {
|
||||
/* no X-char, try to push chars out in DMA mode */
|
||||
bool ret = true;
|
||||
|
||||
if (!uap->dmatx.queued) {
|
||||
if (pl011_dma_tx_refill(uap) > 0) {
|
||||
uap->im &= ~UART011_TXIM;
|
||||
ret = true;
|
||||
} else {
|
||||
uap->im |= UART011_TXIM;
|
||||
ret = false;
|
||||
}
|
||||
writew(uap->im, uap->port.membase + UART011_IMSC);
|
||||
} else if (!(uap->dmacr & UART011_TXDMAE)) {
|
||||
uap->dmacr |= UART011_TXDMAE;
|
||||
writew(uap->dmacr,
|
||||
uap->port.membase + UART011_DMACR);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* We have an X-char to send. Disable DMA to prevent it loading
|
||||
* the TX fifo, and then see if we can stuff it into the FIFO.
|
||||
*/
|
||||
dmacr = uap->dmacr;
|
||||
uap->dmacr &= ~UART011_TXDMAE;
|
||||
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
|
||||
|
||||
if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
|
||||
/*
|
||||
* No space in the FIFO, so enable the transmit interrupt
|
||||
* so we know when there is space. Note that once we've
|
||||
* loaded the character, we should just re-enable DMA.
|
||||
*/
|
||||
return false;
|
||||
}
|
||||
|
||||
writew(uap->port.x_char, uap->port.membase + UART01x_DR);
|
||||
uap->port.icount.tx++;
|
||||
uap->port.x_char = 0;
|
||||
|
||||
/* Success - restore the DMA state */
|
||||
uap->dmacr = dmacr;
|
||||
writew(dmacr, uap->port.membase + UART011_DMACR);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* Flush the transmit buffer.
|
||||
* Locking: called with port lock held and IRQs disabled.
|
||||
*/
|
||||
static void pl011_dma_flush_buffer(struct uart_port *port)
|
||||
{
|
||||
struct uart_amba_port *uap = (struct uart_amba_port *)port;
|
||||
|
||||
if (!uap->using_dma)
|
||||
return;
|
||||
|
||||
/* Avoid deadlock with the DMA engine callback */
|
||||
spin_unlock(&uap->port.lock);
|
||||
dmaengine_terminate_all(uap->dmatx.chan);
|
||||
spin_lock(&uap->port.lock);
|
||||
if (uap->dmatx.queued) {
|
||||
dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
|
||||
DMA_TO_DEVICE);
|
||||
uap->dmatx.queued = false;
|
||||
uap->dmacr &= ~UART011_TXDMAE;
|
||||
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void pl011_dma_startup(struct uart_amba_port *uap)
|
||||
{
|
||||
if (!uap->dmatx.chan)
|
||||
return;
|
||||
|
||||
uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
|
||||
if (!uap->dmatx.buf) {
|
||||
dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
|
||||
uap->port.fifosize = uap->fifosize;
|
||||
return;
|
||||
}
|
||||
|
||||
sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
|
||||
|
||||
/* The DMA buffer is now the FIFO the TTY subsystem can use */
|
||||
uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
|
||||
uap->using_dma = true;
|
||||
|
||||
/* Turn on DMA error (RX/TX will be enabled on demand) */
|
||||
uap->dmacr |= UART011_DMAONERR;
|
||||
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
|
||||
|
||||
/*
|
||||
* ST Micro variants has some specific dma burst threshold
|
||||
* compensation. Set this to 16 bytes, so burst will only
|
||||
* be issued above/below 16 bytes.
|
||||
*/
|
||||
if (uap->vendor->dma_threshold)
|
||||
writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
|
||||
uap->port.membase + ST_UART011_DMAWM);
|
||||
}
|
||||
|
||||
static void pl011_dma_shutdown(struct uart_amba_port *uap)
|
||||
{
|
||||
if (!uap->using_dma)
|
||||
return;
|
||||
|
||||
/* Disable RX and TX DMA */
|
||||
while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
|
||||
barrier();
|
||||
|
||||
spin_lock_irq(&uap->port.lock);
|
||||
uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
|
||||
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
|
||||
spin_unlock_irq(&uap->port.lock);
|
||||
|
||||
/* In theory, this should already be done by pl011_dma_flush_buffer */
|
||||
dmaengine_terminate_all(uap->dmatx.chan);
|
||||
if (uap->dmatx.queued) {
|
||||
dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
|
||||
DMA_TO_DEVICE);
|
||||
uap->dmatx.queued = false;
|
||||
}
|
||||
|
||||
kfree(uap->dmatx.buf);
|
||||
|
||||
uap->using_dma = false;
|
||||
}
|
||||
|
||||
#else
|
||||
/* Blank functions if the DMA engine is not available */
|
||||
static inline void pl011_dma_probe(struct uart_amba_port *uap)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void pl011_dma_remove(struct uart_amba_port *uap)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void pl011_dma_startup(struct uart_amba_port *uap)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
|
||||
{
|
||||
}
|
||||
|
||||
static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
|
||||
{
|
||||
}
|
||||
|
||||
static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
#define pl011_dma_flush_buffer NULL
|
||||
#endif
|
||||
|
||||
|
||||
static void pl011_stop_tx(struct uart_port *port)
|
||||
{
|
||||
struct uart_amba_port *uap = (struct uart_amba_port *)port;
|
||||
|
||||
uap->im &= ~UART011_TXIM;
|
||||
writew(uap->im, uap->port.membase + UART011_IMSC);
|
||||
pl011_dma_tx_stop(uap);
|
||||
}
|
||||
|
||||
static void pl011_start_tx(struct uart_port *port)
|
||||
{
|
||||
struct uart_amba_port *uap = (struct uart_amba_port *)port;
|
||||
|
||||
uap->im |= UART011_TXIM;
|
||||
writew(uap->im, uap->port.membase + UART011_IMSC);
|
||||
if (!pl011_dma_tx_start(uap)) {
|
||||
uap->im |= UART011_TXIM;
|
||||
writew(uap->im, uap->port.membase + UART011_IMSC);
|
||||
}
|
||||
}
|
||||
|
||||
static void pl011_stop_rx(struct uart_port *port)
|
||||
|
|
@ -203,7 +707,11 @@ static void pl011_tx_chars(struct uart_amba_port *uap)
|
|||
return;
|
||||
}
|
||||
|
||||
count = uap->port.fifosize >> 1;
|
||||
/* If we are using DMA mode, try to send some characters. */
|
||||
if (pl011_dma_tx_irq(uap))
|
||||
return;
|
||||
|
||||
count = uap->fifosize >> 1;
|
||||
do {
|
||||
writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
|
||||
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
|
||||
|
|
@ -246,10 +754,11 @@ static void pl011_modem_status(struct uart_amba_port *uap)
|
|||
static irqreturn_t pl011_int(int irq, void *dev_id)
|
||||
{
|
||||
struct uart_amba_port *uap = dev_id;
|
||||
unsigned long flags;
|
||||
unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
|
||||
int handled = 0;
|
||||
|
||||
spin_lock(&uap->port.lock);
|
||||
spin_lock_irqsave(&uap->port.lock, flags);
|
||||
|
||||
status = readw(uap->port.membase + UART011_MIS);
|
||||
if (status) {
|
||||
|
|
@ -274,7 +783,7 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
|
|||
handled = 1;
|
||||
}
|
||||
|
||||
spin_unlock(&uap->port.lock);
|
||||
spin_unlock_irqrestore(&uap->port.lock, flags);
|
||||
|
||||
return IRQ_RETVAL(handled);
|
||||
}
|
||||
|
|
@ -396,7 +905,7 @@ static int pl011_startup(struct uart_port *port)
|
|||
if (retval)
|
||||
goto clk_dis;
|
||||
|
||||
writew(uap->ifls, uap->port.membase + UART011_IFLS);
|
||||
writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
|
||||
|
||||
/*
|
||||
* Provoke TX FIFO interrupt into asserting.
|
||||
|
|
@ -423,11 +932,18 @@ static int pl011_startup(struct uart_port *port)
|
|||
cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
|
||||
writew(cr, uap->port.membase + UART011_CR);
|
||||
|
||||
/* Clear pending error interrupts */
|
||||
writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
|
||||
uap->port.membase + UART011_ICR);
|
||||
|
||||
/*
|
||||
* initialise the old status of the modem signals
|
||||
*/
|
||||
uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
|
||||
|
||||
/* Startup DMA */
|
||||
pl011_dma_startup(uap);
|
||||
|
||||
/*
|
||||
* Finally, enable interrupts
|
||||
*/
|
||||
|
|
@ -467,6 +983,8 @@ static void pl011_shutdown(struct uart_port *port)
|
|||
writew(0xffff, uap->port.membase + UART011_ICR);
|
||||
spin_unlock_irq(&uap->port.lock);
|
||||
|
||||
pl011_dma_shutdown(uap);
|
||||
|
||||
/*
|
||||
* Free the interrupt
|
||||
*/
|
||||
|
|
@ -498,13 +1016,18 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
|
|||
struct uart_amba_port *uap = (struct uart_amba_port *)port;
|
||||
unsigned int lcr_h, old_cr;
|
||||
unsigned long flags;
|
||||
unsigned int baud, quot;
|
||||
unsigned int baud, quot, clkdiv;
|
||||
|
||||
if (uap->vendor->oversampling)
|
||||
clkdiv = 8;
|
||||
else
|
||||
clkdiv = 16;
|
||||
|
||||
/*
|
||||
* Ask the core to calculate the divisor for us.
|
||||
*/
|
||||
baud = uart_get_baud_rate(port, termios, old, 0,
|
||||
port->uartclk/(uap->oversampling ? 8 : 16));
|
||||
port->uartclk / clkdiv);
|
||||
|
||||
if (baud > port->uartclk/16)
|
||||
quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
|
||||
|
|
@ -532,7 +1055,7 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
|
|||
if (!(termios->c_cflag & PARODD))
|
||||
lcr_h |= UART01x_LCRH_EPS;
|
||||
}
|
||||
if (port->fifosize > 1)
|
||||
if (uap->fifosize > 1)
|
||||
lcr_h |= UART01x_LCRH_FEN;
|
||||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
|
@ -588,8 +1111,8 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
|
|||
uap->autorts = false;
|
||||
}
|
||||
|
||||
if (uap->oversampling) {
|
||||
if (baud > port->uartclk/16)
|
||||
if (uap->vendor->oversampling) {
|
||||
if (baud > port->uartclk / 16)
|
||||
old_cr |= ST_UART011_CR_OVSFACT;
|
||||
else
|
||||
old_cr &= ~ST_UART011_CR_OVSFACT;
|
||||
|
|
@ -622,7 +1145,8 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
|
|||
|
||||
static const char *pl011_type(struct uart_port *port)
|
||||
{
|
||||
return port->type == PORT_AMBA ? "AMBA/PL011" : NULL;
|
||||
struct uart_amba_port *uap = (struct uart_amba_port *)port;
|
||||
return uap->port.type == PORT_AMBA ? uap->type : NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -679,6 +1203,7 @@ static struct uart_ops amba_pl011_pops = {
|
|||
.break_ctl = pl011_break_ctl,
|
||||
.startup = pl011_startup,
|
||||
.shutdown = pl011_shutdown,
|
||||
.flush_buffer = pl011_dma_flush_buffer,
|
||||
.set_termios = pl011_set_termios,
|
||||
.type = pl011_type,
|
||||
.release_port = pl010_release_port,
|
||||
|
|
@ -761,7 +1286,7 @@ pl011_console_get_options(struct uart_amba_port *uap, int *baud,
|
|||
|
||||
*baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
|
||||
|
||||
if (uap->oversampling) {
|
||||
if (uap->vendor->oversampling) {
|
||||
if (readw(uap->port.membase + UART011_CR)
|
||||
& ST_UART011_CR_OVSFACT)
|
||||
*baud *= 2;
|
||||
|
|
@ -858,19 +1383,22 @@ static int pl011_probe(struct amba_device *dev, struct amba_id *id)
|
|||
goto unmap;
|
||||
}
|
||||
|
||||
uap->ifls = vendor->ifls;
|
||||
uap->vendor = vendor;
|
||||
uap->lcrh_rx = vendor->lcrh_rx;
|
||||
uap->lcrh_tx = vendor->lcrh_tx;
|
||||
uap->oversampling = vendor->oversampling;
|
||||
uap->fifosize = vendor->fifosize;
|
||||
uap->port.dev = &dev->dev;
|
||||
uap->port.mapbase = dev->res.start;
|
||||
uap->port.membase = base;
|
||||
uap->port.iotype = UPIO_MEM;
|
||||
uap->port.irq = dev->irq[0];
|
||||
uap->port.fifosize = vendor->fifosize;
|
||||
uap->port.fifosize = uap->fifosize;
|
||||
uap->port.ops = &amba_pl011_pops;
|
||||
uap->port.flags = UPF_BOOT_AUTOCONF;
|
||||
uap->port.line = i;
|
||||
pl011_dma_probe(uap);
|
||||
|
||||
snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
|
||||
|
||||
amba_ports[i] = uap;
|
||||
|
||||
|
|
@ -879,6 +1407,7 @@ static int pl011_probe(struct amba_device *dev, struct amba_id *id)
|
|||
if (ret) {
|
||||
amba_set_drvdata(dev, NULL);
|
||||
amba_ports[i] = NULL;
|
||||
pl011_dma_remove(uap);
|
||||
clk_put(uap->clk);
|
||||
unmap:
|
||||
iounmap(base);
|
||||
|
|
@ -902,6 +1431,7 @@ static int pl011_remove(struct amba_device *dev)
|
|||
if (amba_ports[i] == uap)
|
||||
amba_ports[i] = NULL;
|
||||
|
||||
pl011_dma_remove(uap);
|
||||
iounmap(uap->port.membase);
|
||||
clk_put(uap->clk);
|
||||
kfree(uap);
|
||||
|
|
|
|||
Loading…
Reference in a new issue