From 472fc0c7d882de576dd6494abe2248061f1f0380 Mon Sep 17 00:00:00 2001 From: Govindaraj Rajagopal Date: Tue, 9 Jun 2020 08:52:31 +0530 Subject: [PATCH] ARM: dts: msm: Add throttle clk support for shima Add GCC_VIDEO_MVP_THROTTLE_CORE_CLK support for shima. Change-Id: I225aefd60640cd10b6ba3b3ceb2508acca50fb45 --- qcom/shima-vidc.dtsi | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/qcom/shima-vidc.dtsi b/qcom/shima-vidc.dtsi index 3b6894c007c2..9da8055b606a 100644 --- a/qcom/shima-vidc.dtsi +++ b/qcom/shima-vidc.dtsi @@ -15,15 +15,16 @@ vcodec-supply = <&video_cc_mvs0_gdsc>; /* Clocks */ - clock-names = "gcc_video_axi0", + clock-names = "gcc_video_axi0", "gcc_video_throttle", "core_clk", "vcodec_clk"; clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&gcc GCC_VIDEO_MVP_THROTTLE_CORE_CLK>, <&videocc VIDEO_CC_MVS0C_CLK>, <&videocc VIDEO_CC_MVS0_CLK>; - qcom,proxy-clock-names = "gcc_video_axi0", + qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_throttle", "core_clk", "vcodec_clk"; /* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/ - qcom,clock-configs = <0x0 0x1 0x1>; + qcom,clock-configs = <0x0 0x0 0x1 0x1>; qcom,allowed-clock-rates = <240000000 338000000 364800000>; resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, @@ -113,15 +114,16 @@ vcodec-supply = <&video_cc_mvs0_gdsc>; /* Clocks */ - clock-names = "gcc_video_axi0", + clock-names = "gcc_video_axi0", "gcc_video_throttle", "core_clk", "vcodec_clk"; clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&gcc GCC_VIDEO_MVP_THROTTLE_CORE_CLK>, <&videocc VIDEO_CC_MVS0C_CLK>, <&videocc VIDEO_CC_MVS0_CLK>; - qcom,proxy-clock-names = "gcc_video_axi0", + qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_throttle", "core_clk", "vcodec_clk"; /* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/ - qcom,clock-configs = <0x0 0x1 0x1>; + qcom,clock-configs = <0x0 0x0 0x1 0x1>; qcom,allowed-clock-rates = <201600000>; resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, <&videocc VIDEO_CC_MVS0C_CLK_ARES>; @@ -210,15 +212,16 @@ vcodec-supply = <&video_cc_mvs0_gdsc>; /* Clocks */ - clock-names = "gcc_video_axi0", + clock-names = "gcc_video_axi0", "gcc_video_throttle", "core_clk", "vcodec_clk"; clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&gcc GCC_VIDEO_MVP_THROTTLE_CORE_CLK>, <&videocc VIDEO_CC_MVS0C_CLK>, <&videocc VIDEO_CC_MVS0_CLK>; - qcom,proxy-clock-names = "gcc_video_axi0", + qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_throttle", "core_clk", "vcodec_clk"; /* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/ - qcom,clock-configs = <0x0 0x1 0x1>; + qcom,clock-configs = <0x0 0x0 0x1 0x1>; qcom,allowed-clock-rates = <240000000 338000000 366000000 444000000>; resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,