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pci-v4.17-changes
-----BEGIN PGP SIGNATURE----- iQJIBAABCgAyFiEEgMe7l+5h9hnxdsnuWYigwDrT+vwFAlrHeY8UHGJoZWxnYWFz QGdvb2dsZS5jb20ACgkQWYigwDrT+vxhLRAAndV/0NDyWZU0eZNM6twri2SEFnF7 E4ar+YthxDxxJG4TLJbIA12jc5NgHZy4WuttDa6Jb99KreBXIHJFlNi/V/tme6zf +yXUuxWae7wJzBiaay57VqLGSc80gt/LTgjLa1siwQqjTbO3wSXR6JJXNaE9FtQ4 /jL61t8bD1Peb5cWTpt9p0hrnKI0/pHwASdReyFS4F/HDKdvpof7BxE/OU3HSxxA XKC2v6RjY4S93vkzvApDXQ+vhKquVRK7/ojyTXQUO/GIzcARprO7H4k62N4ar0x/ qbXLkR8IMkwA8ecsNmcL92ftb/cXoHfd+wdK8WpijqzF4kW4SdteVWbIhUzI0gbr 0gjDYIzjplvH3pZGv/qvx+8sFtAP95OdPjuAAW2qJ9TCVfmiS8naNFCvcxg87RhD gjyQD3If1X7F8wy309lhq7VNyRexTHgIMgTXHyFvuZMzn/Qe1huL2XCwDcEAg/OX AvU2iuSE5tWAh7gIUMF/aWi3uoeJUyyoru5ZR//gqdFfx9YxpSimO1UDXnpPi8SR Iz/jzHJc0aWGYdQ9l6HiSbJF3P/QQcWYs9igt0A7BRGB05SPdWCh7sSO70FJa8ME f4WID5/qEiaH26kiSRX4cUqpc8Amk8bT0DXw2OT57qy3JM0ZdV5ENQX11pSpr9hv uLEf0DU7AEmdvzQ= =T++R -----END PGP SIGNATURE----- Merge tag 'pci-v4.17-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: - move pci_uevent_ers() out of pci.h (Michael Ellerman) - skip ASPM common clock warning if BIOS already configured it (Sinan Kaya) - fix ASPM Coverity warning about threshold_ns (Gustavo A. R. Silva) - remove last user of pci_get_bus_and_slot() and the function itself (Sinan Kaya) - add decoding for 16 GT/s link speed (Jay Fang) - add interfaces to get max link speed and width (Tal Gilboa) - add pcie_bandwidth_capable() to compute max supported link bandwidth (Tal Gilboa) - add pcie_bandwidth_available() to compute bandwidth available to device (Tal Gilboa) - add pcie_print_link_status() to log link speed and whether it's limited (Tal Gilboa) - use PCI core interfaces to report when device performance may be limited by its slot instead of doing it in each driver (Tal Gilboa) - fix possible cpqphp NULL pointer dereference (Shawn Lin) - rescan more of the hierarchy on ACPI hotplug to fix Thunderbolt/xHCI hotplug (Mika Westerberg) - add support for PCI I/O port space that's neither directly accessible via CPU in/out instructions nor directly mapped into CPU physical memory space. This is fairly intrusive and includes minor changes to interfaces used for I/O space on most platforms (Zhichang Yuan, John Garry) - add support for HiSilicon Hip06/Hip07 LPC I/O space (Zhichang Yuan, John Garry) - use PCI_EXP_DEVCTL2_COMP_TIMEOUT in rapidio/tsi721 (Bjorn Helgaas) - remove possible NULL pointer dereference in of_pci_bus_find_domain_nr() (Shawn Lin) - report quirk timings with dev_info (Bjorn Helgaas) - report quirks that take longer than 10ms (Bjorn Helgaas) - add and use Altera Vendor ID (Johannes Thumshirn) - tidy Makefiles and comments (Bjorn Helgaas) - don't set up INTx if MSI or MSI-X is enabled to align cris, frv, ia64, and mn10300 with x86 (Bjorn Helgaas) - move pcieport_if.h to drivers/pci/pcie/ to encapsulate it (Frederick Lawler) - merge pcieport_if.h into portdrv.h (Bjorn Helgaas) - move workaround for BIOS PME issue from portdrv to PCI core (Bjorn Helgaas) - completely disable portdrv with "pcie_ports=compat" (Bjorn Helgaas) - remove portdrv link order dependency (Bjorn Helgaas) - remove support for unused VC portdrv service (Bjorn Helgaas) - simplify portdrv feature permission checking (Bjorn Helgaas) - remove "pcie_hp=nomsi" parameter (use "pci=nomsi" instead) (Bjorn Helgaas) - remove unnecessary "pcie_ports=auto" parameter (Bjorn Helgaas) - use cached AER capability offset (Frederick Lawler) - don't enable DPC if BIOS hasn't granted AER control (Mika Westerberg) - rename pcie-dpc.c to dpc.c (Bjorn Helgaas) - use generic pci_mmap_resource_range() instead of powerpc and xtensa arch-specific versions (David Woodhouse) - support arbitrary PCI host bridge offsets on sparc (Yinghai Lu) - remove System and Video ROM reservations on sparc (Bjorn Helgaas) - probe for device reset support during enumeration instead of runtime (Bjorn Helgaas) - add ACS quirk for Ampere (née APM) root ports (Feng Kan) - add function 1 DMA alias quirk for Marvell 88SE9220 (Thomas Vincent-Cross) - protect device restore with device lock (Sinan Kaya) - handle failure of FLR gracefully (Sinan Kaya) - handle CRS (config retry status) after device resets (Sinan Kaya) - skip various config reads for SR-IOV VFs as an optimization (KarimAllah Ahmed) - consolidate VPD code in vpd.c (Bjorn Helgaas) - add Tegra dependency on PCI_MSI_IRQ_DOMAIN (Arnd Bergmann) - add DT support for R-Car r8a7743 (Biju Das) - fix a PCI_EJECT vs PCI_BUS_RELATIONS race condition in Hyper-V host bridge driver that causes a general protection fault (Dexuan Cui) - fix Hyper-V host bridge hang in MSI setup on 1-vCPU VMs with SR-IOV (Dexuan Cui) - fix Hyper-V host bridge hang when ejecting a VF before setting up MSI (Dexuan Cui) - make several structures static (Fengguang Wu) - increase number of MSI IRQs supported by Synopsys DesignWare bridges from 32 to 256 (Gustavo Pimentel) - implemented multiplexed IRQ domain API and remove obsolete MSI IRQ API from DesignWare drivers (Gustavo Pimentel) - add Tegra power management support (Manikanta Maddireddy) - add Tegra loadable module support (Manikanta Maddireddy) - handle 64-bit BARs correctly in endpoint support (Niklas Cassel) - support optional regulator for HiSilicon STB (Shawn Guo) - use regulator bulk API for Qualcomm apq8064 (Srinivas Kandagatla) - support power supplies for Qualcomm msm8996 (Srinivas Kandagatla) * tag 'pci-v4.17-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (123 commits) MAINTAINERS: Add John Garry as maintainer for HiSilicon LPC driver HISI LPC: Add ACPI support ACPI / scan: Do not enumerate Indirect IO host children ACPI / scan: Rename acpi_is_serial_bus_slave() for more general use HISI LPC: Support the LPC host on Hip06/Hip07 with DT bindings of: Add missing I/O range exception for indirect-IO devices PCI: Apply the new generic I/O management on PCI IO hosts PCI: Add fwnode handler as input param of pci_register_io_range() PCI: Remove __weak tag from pci_register_io_range() MAINTAINERS: Add missing /drivers/pci/cadence directory entry fm10k: Report PCIe link properties with pcie_print_link_status() net/mlx5e: Use pcie_bandwidth_available() to compute bandwidth net/mlx5: Report PCIe link properties with pcie_print_link_status() net/mlx4_core: Report PCIe link properties with pcie_print_link_status() PCI: Add pcie_print_link_status() to log link speed and whether it's limited PCI: Add pcie_bandwidth_available() to compute bandwidth available to device misc: pci_endpoint_test: Handle 64-bit BARs properly PCI: designware-ep: Make dw_pcie_ep_reset_bar() handle 64-bit BARs properly PCI: endpoint: Make sure that BAR_5 does not have 64-bit flag set when clearing PCI: endpoint: Make epc->ops->clear_bar()/pci_epc_clear_bar() take struct *epf_bar ...
This commit is contained in:
Linus Torvalds
commit
3c0d551e02
118 changed files with 3491 additions and 2365 deletions
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@ -2,8 +2,10 @@
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#define pr_fmt(fmt) "OF: " fmt
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#include <linux/device.h>
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#include <linux/fwnode.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/logic_pio.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/pci.h>
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@ -333,7 +335,8 @@ int of_pci_range_to_resource(struct of_pci_range *range,
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if (res->flags & IORESOURCE_IO) {
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unsigned long port;
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err = pci_register_io_range(range->cpu_addr, range->size);
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err = pci_register_io_range(&np->fwnode, range->cpu_addr,
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range->size);
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if (err)
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goto invalid_range;
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port = pci_address_to_pio(range->cpu_addr);
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@ -560,9 +563,14 @@ static int of_translate_one(struct device_node *parent, struct of_bus *bus,
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* that translation is impossible (that is we are not dealing with a value
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* that can be mapped to a cpu physical address). This is not really specified
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* that way, but this is traditionally the way IBM at least do things
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*
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* Whenever the translation fails, the *host pointer will be set to the
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* device that had registered logical PIO mapping, and the return code is
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* relative to that node.
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*/
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static u64 __of_translate_address(struct device_node *dev,
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const __be32 *in_addr, const char *rprop)
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const __be32 *in_addr, const char *rprop,
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struct device_node **host)
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{
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struct device_node *parent = NULL;
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struct of_bus *bus, *pbus;
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@ -575,6 +583,7 @@ static u64 __of_translate_address(struct device_node *dev,
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/* Increase refcount at current level */
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of_node_get(dev);
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*host = NULL;
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/* Get parent & match bus type */
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parent = of_get_parent(dev);
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if (parent == NULL)
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@ -595,6 +604,8 @@ static u64 __of_translate_address(struct device_node *dev,
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/* Translate */
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for (;;) {
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struct logic_pio_hwaddr *iorange;
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/* Switch to parent bus */
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of_node_put(dev);
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dev = parent;
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@ -607,6 +618,19 @@ static u64 __of_translate_address(struct device_node *dev,
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break;
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}
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/*
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* For indirectIO device which has no ranges property, get
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* the address from reg directly.
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*/
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iorange = find_io_range_by_fwnode(&dev->fwnode);
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if (iorange && (iorange->flags != LOGIC_PIO_CPU_MMIO)) {
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result = of_read_number(addr + 1, na - 1);
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pr_debug("indirectIO matched(%pOF) 0x%llx\n",
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dev, result);
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*host = of_node_get(dev);
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break;
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}
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/* Get new parent bus and counts */
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pbus = of_match_bus(parent);
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pbus->count_cells(dev, &pna, &pns);
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@ -638,13 +662,32 @@ static u64 __of_translate_address(struct device_node *dev,
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u64 of_translate_address(struct device_node *dev, const __be32 *in_addr)
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{
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return __of_translate_address(dev, in_addr, "ranges");
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struct device_node *host;
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u64 ret;
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ret = __of_translate_address(dev, in_addr, "ranges", &host);
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if (host) {
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of_node_put(host);
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return OF_BAD_ADDR;
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}
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return ret;
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}
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EXPORT_SYMBOL(of_translate_address);
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u64 of_translate_dma_address(struct device_node *dev, const __be32 *in_addr)
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{
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return __of_translate_address(dev, in_addr, "dma-ranges");
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struct device_node *host;
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u64 ret;
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ret = __of_translate_address(dev, in_addr, "dma-ranges", &host);
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if (host) {
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of_node_put(host);
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return OF_BAD_ADDR;
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}
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return ret;
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}
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EXPORT_SYMBOL(of_translate_dma_address);
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@ -686,29 +729,48 @@ const __be32 *of_get_address(struct device_node *dev, int index, u64 *size,
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}
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EXPORT_SYMBOL(of_get_address);
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static u64 of_translate_ioport(struct device_node *dev, const __be32 *in_addr,
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u64 size)
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{
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u64 taddr;
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unsigned long port;
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struct device_node *host;
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taddr = __of_translate_address(dev, in_addr, "ranges", &host);
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if (host) {
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/* host-specific port access */
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port = logic_pio_trans_hwaddr(&host->fwnode, taddr, size);
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of_node_put(host);
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} else {
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/* memory-mapped I/O range */
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port = pci_address_to_pio(taddr);
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}
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if (port == (unsigned long)-1)
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return OF_BAD_ADDR;
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return port;
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}
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static int __of_address_to_resource(struct device_node *dev,
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const __be32 *addrp, u64 size, unsigned int flags,
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const char *name, struct resource *r)
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{
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u64 taddr;
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if ((flags & (IORESOURCE_IO | IORESOURCE_MEM)) == 0)
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if (flags & IORESOURCE_MEM)
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taddr = of_translate_address(dev, addrp);
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else if (flags & IORESOURCE_IO)
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taddr = of_translate_ioport(dev, addrp, size);
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else
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return -EINVAL;
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taddr = of_translate_address(dev, addrp);
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if (taddr == OF_BAD_ADDR)
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return -EINVAL;
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memset(r, 0, sizeof(struct resource));
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if (flags & IORESOURCE_IO) {
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unsigned long port;
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port = pci_address_to_pio(taddr);
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if (port == (unsigned long)-1)
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return -EINVAL;
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r->start = port;
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r->end = port + size - 1;
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} else {
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r->start = taddr;
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r->end = taddr + size - 1;
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}
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r->start = taddr;
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r->end = taddr + size - 1;
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r->flags = flags;
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r->name = name ? name : dev->full_name;
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