Pin control subsystem changes for kernel 3.5:

- Generic Device Tree bindings and hooks for drivers so we can
  move over modern drivers to using this.
 - Device Tree bindings for Tegra SoCs.
 - Funneling some devicetree helper code for the drivers/of
  subsystem.
 - New pin control drivers for:
  - Freescale MXS
  - Freescale i.MX51
  - Freescale i.MX53
  - All of these use Device Tree bindings.
 - Dummy pinctrl handles for stepwise migration to pinctrl, akin
  to dummy regulators.
 - Minor non-urgent fixes and improvments.
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Merge tag 'pinctrl-for-v3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control subsystem changes from Linus Walleij:

 - Generic Device Tree bindings and hooks for drivers so we can move
   over modern drivers to using this.

 - Device Tree bindings for Tegra SoCs.

 - Funneling some devicetree helper code for the drivers/of subsystem.

 - New pin control drivers for:
   * Freescale MXS
   * Freescale i.MX51
   * Freescale i.MX53
     All of these use Device Tree bindings.

 - Dummy pinctrl handles for stepwise migration to pinctrl, akin to
   dummy regulators.
 - Minor non-urgent fixes and improvments.

Fix up trivial conflicts in Documentation/driver-model/devres.txt and
drivers/pinctrl/core.c,

* tag 'pinctrl-for-v3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (46 commits)
  pinctrl: pinctrl-imx: add imx51 pinctrl driver
  pinctrl: pinctrl-imx: add imx53 pinctrl driver
  pinctrl: pinctrl-pxa3xx: remove empty pinmux disable function
  pinctrl: pinctrl-mxs: remove empty pinmux disable function
  pinctrl: pinctrl-imx: remove empty pinmux disable function
  pinctrl: make pinmux disable function optional
  pinctrl: a minor error checking improvement for pinconf
  pinctrl: mxs: skip gpio nodes for group creation
  pinctrl: mxs: create group for pin config node
  pinctrl: (cosmetic) fix two entries in DocBook comments
  pinctrl: add more info to error msgs in pin_request
  pinctrl: add pinctrl-mxs support
  pinctrl: pinctrl-imx: add imx6q pinctrl driver
  pinctrl: pinctrl-imx: add imx pinctrl core driver
  dt: add of_get_child_count helper function
  pinctrl: support gpio request deferred probing
  pinctrl: add pinctrl_provide_dummies interface for platforms to use
  pinctrl: enhance reporting of errors when loading from DT
  pinctrl: add kerneldoc for pinctrl_ops device tree functions
  pinctrl: propagate map validation errors
  ...

Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt

@@ -0,0 +1,95 @@
+* Freescale IOMUX Controller (IOMUXC) for i.MX
+
+The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC
+to share one PAD to several functional blocks. The sharing is done by
+multiplexing the PAD input/output signals. For each PAD there are up to
+8 muxing options (called ALT modes). Since different modules require
+different PAD settings (like pull up, keeper, etc) the IOMUXC controls
+also the PAD settings parameters.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+Freescale IMX pin configuration node is a node of a group of pins which can be
+used for a specific device or function. This node represents both mux and config
+of the pins in that group. The 'mux' selects the function mode(also named mux
+mode) this pin can work on and the 'config' configures various pad settings
+such as pull-up, open drain, drive strength, etc.
+
+Required properties for iomux controller:
+- compatible: "fsl,<soc>-iomuxc"
+  Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
+
+Required properties for pin configuration node:
+- fsl,pins: two integers array, represents a group of pins mux and config
+  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
+  pin working on a specific function, CONFIG is the pad setting value like
+  pull-up on this pin. Please refer to fsl,<soc>-pinctrl.txt for the valid
+  pins and functions of each SoC.
+
+Bits used for CONFIG:
+NO_PAD_CTL(1 << 31): indicate this pin does not need config.
+
+SION(1 << 30): Software Input On Field.
+Force the selected mux mode input path no matter of MUX_MODE functionality.
+By default the input path is determined by functionality of the selected
+mux mode (regular).
+
+Other bits are used for PAD setting.
+Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
+of bits definitions.
+
+NOTE:
+Some requirements for using fsl,imx-pinctrl binding:
+1. We have pin function node defined under iomux controller node to represent
+   what pinmux functions this SoC supports.
+2. The pin configuration node intends to work on a specific function should
+   to be defined under that specific function node.
+   The function node's name should represent well about what function
+   this group of pins in this pin configuration node are working on.
+3. The driver can use the function node's name and pin configuration node's
+   name describe the pin function and group hierarchy.
+   For example, Linux IMX pinctrl driver takes the function node's name
+   as the function name and pin configuration node's name as group name to
+   create the map table.
+4. Each pin configuration node should have a phandle, devices can set pins
+   configurations by referring to the phandle of that pin configuration node.
+
+Examples:
+usdhc@0219c000 { /* uSDHC4 */
+	fsl,card-wired;
+	vmmc-supply = <&reg_3p3v>;
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc4_1>;
+};
+
+iomuxc@020e0000 {
+	compatible = "fsl,imx6q-iomuxc";
+	reg = <0x020e0000 0x4000>;
+
+	/* shared pinctrl settings */
+	usdhc4 {
+		pinctrl_usdhc4_1: usdhc4grp-1 {
+			fsl,pins = <1386 0x17059	/* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
+				    1392 0x10059	/* MX6Q_PAD_SD4_CLK__USDHC4_CLK	*/
+				    1462 0x17059	/* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
+				    1470 0x17059	/* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
+				    1478 0x17059	/* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
+				    1486 0x17059	/* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
+				    1493 0x17059	/* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
+				    1501 0x17059	/* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
+				    1509 0x17059	/* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
+				    1517 0x17059>;	/* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+		};
+	};
+	....
+};
+Refer to the IOMUXC controller chapter in imx6q datasheet,
+0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed,
+80Ohm driver strength and Fast Slew Rate.
+User should refer to each SoC spec to set the correct value.
+
+TODO: when dtc macro support is available, we can change above raw data
+to dt macro which can get better readability in dts file.

Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt

@@ -0,0 +1,787 @@
+* Freescale IMX51 IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+
+Required properties:
+- compatible: "fsl,imx51-iomuxc"
+- fsl,pins: two integers array, represents a group of pins mux and config
+  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
+  pin working on a specific function, CONFIG is the pad setting value like
+  pull-up for this pin. Please refer to imx51 datasheet for the valid pad
+  config settings.
+
+CONFIG bits definition:
+PAD_CTL_HVE			(1 << 13)
+PAD_CTL_HYS			(1 << 8)
+PAD_CTL_PKE			(1 << 7)
+PAD_CTL_PUE			(1 << 6)
+PAD_CTL_PUS_100K_DOWN		(0 << 4)
+PAD_CTL_PUS_47K_UP		(1 << 4)
+PAD_CTL_PUS_100K_UP		(2 << 4)
+PAD_CTL_PUS_22K_UP		(3 << 4)
+PAD_CTL_ODE			(1 << 3)
+PAD_CTL_DSE_LOW			(0 << 1)
+PAD_CTL_DSE_MED			(1 << 1)
+PAD_CTL_DSE_HIGH		(2 << 1)
+PAD_CTL_DSE_MAX			(3 << 1)
+PAD_CTL_SRE_FAST		(1 << 0)
+PAD_CTL_SRE_SLOW		(0 << 0)
+
+See below for available PIN_FUNC_ID for imx51:
+MX51_PAD_EIM_D16__AUD4_RXFS			0
+MX51_PAD_EIM_D16__AUD5_TXD			1
+MX51_PAD_EIM_D16__EIM_D16			2
+MX51_PAD_EIM_D16__GPIO2_0			3
+MX51_PAD_EIM_D16__I2C1_SDA			4
+MX51_PAD_EIM_D16__UART2_CTS			5
+MX51_PAD_EIM_D16__USBH2_DATA0			6
+MX51_PAD_EIM_D17__AUD5_RXD			7
+MX51_PAD_EIM_D17__EIM_D17			8
+MX51_PAD_EIM_D17__GPIO2_1			9
+MX51_PAD_EIM_D17__UART2_RXD			10
+MX51_PAD_EIM_D17__UART3_CTS			11
+MX51_PAD_EIM_D17__USBH2_DATA1			12
+MX51_PAD_EIM_D18__AUD5_TXC			13
+MX51_PAD_EIM_D18__EIM_D18			14
+MX51_PAD_EIM_D18__GPIO2_2			15
+MX51_PAD_EIM_D18__UART2_TXD			16
+MX51_PAD_EIM_D18__UART3_RTS			17
+MX51_PAD_EIM_D18__USBH2_DATA2			18
+MX51_PAD_EIM_D19__AUD4_RXC			19
+MX51_PAD_EIM_D19__AUD5_TXFS			20
+MX51_PAD_EIM_D19__EIM_D19			21
+MX51_PAD_EIM_D19__GPIO2_3			22
+MX51_PAD_EIM_D19__I2C1_SCL			23
+MX51_PAD_EIM_D19__UART2_RTS			24
+MX51_PAD_EIM_D19__USBH2_DATA3			25
+MX51_PAD_EIM_D20__AUD4_TXD			26
+MX51_PAD_EIM_D20__EIM_D20			27
+MX51_PAD_EIM_D20__GPIO2_4			28
+MX51_PAD_EIM_D20__SRTC_ALARM_DEB		29
+MX51_PAD_EIM_D20__USBH2_DATA4			30
+MX51_PAD_EIM_D21__AUD4_RXD			31
+MX51_PAD_EIM_D21__EIM_D21			32
+MX51_PAD_EIM_D21__GPIO2_5			33
+MX51_PAD_EIM_D21__SRTC_ALARM_DEB		34
+MX51_PAD_EIM_D21__USBH2_DATA5			35
+MX51_PAD_EIM_D22__AUD4_TXC			36
+MX51_PAD_EIM_D22__EIM_D22			37
+MX51_PAD_EIM_D22__GPIO2_6			38
+MX51_PAD_EIM_D22__USBH2_DATA6			39
+MX51_PAD_EIM_D23__AUD4_TXFS			40
+MX51_PAD_EIM_D23__EIM_D23			41
+MX51_PAD_EIM_D23__GPIO2_7			42
+MX51_PAD_EIM_D23__SPDIF_OUT1			43
+MX51_PAD_EIM_D23__USBH2_DATA7			44
+MX51_PAD_EIM_D24__AUD6_RXFS			45
+MX51_PAD_EIM_D24__EIM_D24			46
+MX51_PAD_EIM_D24__GPIO2_8			47
+MX51_PAD_EIM_D24__I2C2_SDA			48
+MX51_PAD_EIM_D24__UART3_CTS			49
+MX51_PAD_EIM_D24__USBOTG_DATA0			50
+MX51_PAD_EIM_D25__EIM_D25			51
+MX51_PAD_EIM_D25__KEY_COL6			52
+MX51_PAD_EIM_D25__UART2_CTS			53
+MX51_PAD_EIM_D25__UART3_RXD			54
+MX51_PAD_EIM_D25__USBOTG_DATA1			55
+MX51_PAD_EIM_D26__EIM_D26			56
+MX51_PAD_EIM_D26__KEY_COL7			57
+MX51_PAD_EIM_D26__UART2_RTS			58
+MX51_PAD_EIM_D26__UART3_TXD			59
+MX51_PAD_EIM_D26__USBOTG_DATA2			60
+MX51_PAD_EIM_D27__AUD6_RXC			61
+MX51_PAD_EIM_D27__EIM_D27			62
+MX51_PAD_EIM_D27__GPIO2_9			63
+MX51_PAD_EIM_D27__I2C2_SCL			64
+MX51_PAD_EIM_D27__UART3_RTS			65
+MX51_PAD_EIM_D27__USBOTG_DATA3			66
+MX51_PAD_EIM_D28__AUD6_TXD			67
+MX51_PAD_EIM_D28__EIM_D28			68
+MX51_PAD_EIM_D28__KEY_ROW4			69
+MX51_PAD_EIM_D28__USBOTG_DATA4			70
+MX51_PAD_EIM_D29__AUD6_RXD			71
+MX51_PAD_EIM_D29__EIM_D29			72
+MX51_PAD_EIM_D29__KEY_ROW5			73
+MX51_PAD_EIM_D29__USBOTG_DATA5			74
+MX51_PAD_EIM_D30__AUD6_TXC			75
+MX51_PAD_EIM_D30__EIM_D30			76
+MX51_PAD_EIM_D30__KEY_ROW6			77
+MX51_PAD_EIM_D30__USBOTG_DATA6			78
+MX51_PAD_EIM_D31__AUD6_TXFS			79
+MX51_PAD_EIM_D31__EIM_D31			80
+MX51_PAD_EIM_D31__KEY_ROW7			81
+MX51_PAD_EIM_D31__USBOTG_DATA7			82
+MX51_PAD_EIM_A16__EIM_A16			83
+MX51_PAD_EIM_A16__GPIO2_10			84
+MX51_PAD_EIM_A16__OSC_FREQ_SEL0			85
+MX51_PAD_EIM_A17__EIM_A17			86
+MX51_PAD_EIM_A17__GPIO2_11			87
+MX51_PAD_EIM_A17__OSC_FREQ_SEL1			88
+MX51_PAD_EIM_A18__BOOT_LPB0			89
+MX51_PAD_EIM_A18__EIM_A18			90
+MX51_PAD_EIM_A18__GPIO2_12			91
+MX51_PAD_EIM_A19__BOOT_LPB1			92
+MX51_PAD_EIM_A19__EIM_A19			93
+MX51_PAD_EIM_A19__GPIO2_13			94
+MX51_PAD_EIM_A20__BOOT_UART_SRC0		95
+MX51_PAD_EIM_A20__EIM_A20			96
+MX51_PAD_EIM_A20__GPIO2_14			97
+MX51_PAD_EIM_A21__BOOT_UART_SRC1		98
+MX51_PAD_EIM_A21__EIM_A21			99
+MX51_PAD_EIM_A21__GPIO2_15			100
+MX51_PAD_EIM_A22__EIM_A22			101
+MX51_PAD_EIM_A22__GPIO2_16			102
+MX51_PAD_EIM_A23__BOOT_HPN_EN			103
+MX51_PAD_EIM_A23__EIM_A23			104
+MX51_PAD_EIM_A23__GPIO2_17			105
+MX51_PAD_EIM_A24__EIM_A24			106
+MX51_PAD_EIM_A24__GPIO2_18			107
+MX51_PAD_EIM_A24__USBH2_CLK			108
+MX51_PAD_EIM_A25__DISP1_PIN4			109
+MX51_PAD_EIM_A25__EIM_A25			110
+MX51_PAD_EIM_A25__GPIO2_19			111
+MX51_PAD_EIM_A25__USBH2_DIR			112
+MX51_PAD_EIM_A26__CSI1_DATA_EN			113
+MX51_PAD_EIM_A26__DISP2_EXT_CLK			114
+MX51_PAD_EIM_A26__EIM_A26			115
+MX51_PAD_EIM_A26__GPIO2_20			116
+MX51_PAD_EIM_A26__USBH2_STP			117
+MX51_PAD_EIM_A27__CSI2_DATA_EN			118
+MX51_PAD_EIM_A27__DISP1_PIN1			119
+MX51_PAD_EIM_A27__EIM_A27			120
+MX51_PAD_EIM_A27__GPIO2_21			121
+MX51_PAD_EIM_A27__USBH2_NXT			122
+MX51_PAD_EIM_EB0__EIM_EB0			123
+MX51_PAD_EIM_EB1__EIM_EB1			124
+MX51_PAD_EIM_EB2__AUD5_RXFS			125
+MX51_PAD_EIM_EB2__CSI1_D2			126
+MX51_PAD_EIM_EB2__EIM_EB2			127
+MX51_PAD_EIM_EB2__FEC_MDIO			128
+MX51_PAD_EIM_EB2__GPIO2_22			129
+MX51_PAD_EIM_EB2__GPT_CMPOUT1			130
+MX51_PAD_EIM_EB3__AUD5_RXC			131
+MX51_PAD_EIM_EB3__CSI1_D3			132
+MX51_PAD_EIM_EB3__EIM_EB3			133
+MX51_PAD_EIM_EB3__FEC_RDATA1			134
+MX51_PAD_EIM_EB3__GPIO2_23			135
+MX51_PAD_EIM_EB3__GPT_CMPOUT2			136
+MX51_PAD_EIM_OE__EIM_OE				137
+MX51_PAD_EIM_OE__GPIO2_24			138
+MX51_PAD_EIM_CS0__EIM_CS0			139
+MX51_PAD_EIM_CS0__GPIO2_25			140
+MX51_PAD_EIM_CS1__EIM_CS1			141
+MX51_PAD_EIM_CS1__GPIO2_26			142
+MX51_PAD_EIM_CS2__AUD5_TXD			143
+MX51_PAD_EIM_CS2__CSI1_D4			144
+MX51_PAD_EIM_CS2__EIM_CS2			145
+MX51_PAD_EIM_CS2__FEC_RDATA2			146
+MX51_PAD_EIM_CS2__GPIO2_27			147
+MX51_PAD_EIM_CS2__USBOTG_STP			148
+MX51_PAD_EIM_CS3__AUD5_RXD			149
+MX51_PAD_EIM_CS3__CSI1_D5			150
+MX51_PAD_EIM_CS3__EIM_CS3			151
+MX51_PAD_EIM_CS3__FEC_RDATA3			152
+MX51_PAD_EIM_CS3__GPIO2_28			153
+MX51_PAD_EIM_CS3__USBOTG_NXT			154
+MX51_PAD_EIM_CS4__AUD5_TXC			155
+MX51_PAD_EIM_CS4__CSI1_D6			156
+MX51_PAD_EIM_CS4__EIM_CS4			157
+MX51_PAD_EIM_CS4__FEC_RX_ER			158
+MX51_PAD_EIM_CS4__GPIO2_29			159
+MX51_PAD_EIM_CS4__USBOTG_CLK			160
+MX51_PAD_EIM_CS5__AUD5_TXFS			161
+MX51_PAD_EIM_CS5__CSI1_D7			162
+MX51_PAD_EIM_CS5__DISP1_EXT_CLK			163
+MX51_PAD_EIM_CS5__EIM_CS5			164
+MX51_PAD_EIM_CS5__FEC_CRS			165
+MX51_PAD_EIM_CS5__GPIO2_30			166
+MX51_PAD_EIM_CS5__USBOTG_DIR			167
+MX51_PAD_EIM_DTACK__EIM_DTACK			168
+MX51_PAD_EIM_DTACK__GPIO2_31			169
+MX51_PAD_EIM_LBA__EIM_LBA			170
+MX51_PAD_EIM_LBA__GPIO3_1			171
+MX51_PAD_EIM_CRE__EIM_CRE			172
+MX51_PAD_EIM_CRE__GPIO3_2			173
+MX51_PAD_DRAM_CS1__DRAM_CS1			174
+MX51_PAD_NANDF_WE_B__GPIO3_3			175
+MX51_PAD_NANDF_WE_B__NANDF_WE_B			176
+MX51_PAD_NANDF_WE_B__PATA_DIOW			177
+MX51_PAD_NANDF_WE_B__SD3_DATA0			178
+MX51_PAD_NANDF_RE_B__GPIO3_4			179
+MX51_PAD_NANDF_RE_B__NANDF_RE_B			180
+MX51_PAD_NANDF_RE_B__PATA_DIOR			181
+MX51_PAD_NANDF_RE_B__SD3_DATA1			182
+MX51_PAD_NANDF_ALE__GPIO3_5			183
+MX51_PAD_NANDF_ALE__NANDF_ALE			184
+MX51_PAD_NANDF_ALE__PATA_BUFFER_EN		185
+MX51_PAD_NANDF_CLE__GPIO3_6			186
+MX51_PAD_NANDF_CLE__NANDF_CLE			187
+MX51_PAD_NANDF_CLE__PATA_RESET_B		188
+MX51_PAD_NANDF_WP_B__GPIO3_7			189
+MX51_PAD_NANDF_WP_B__NANDF_WP_B			190
+MX51_PAD_NANDF_WP_B__PATA_DMACK			191
+MX51_PAD_NANDF_WP_B__SD3_DATA2			192
+MX51_PAD_NANDF_RB0__ECSPI2_SS1			193
+MX51_PAD_NANDF_RB0__GPIO3_8			194
+MX51_PAD_NANDF_RB0__NANDF_RB0			195
+MX51_PAD_NANDF_RB0__PATA_DMARQ			196
+MX51_PAD_NANDF_RB0__SD3_DATA3			197
+MX51_PAD_NANDF_RB1__CSPI_MOSI			198
+MX51_PAD_NANDF_RB1__ECSPI2_RDY			199
+MX51_PAD_NANDF_RB1__GPIO3_9			200
+MX51_PAD_NANDF_RB1__NANDF_RB1			201
+MX51_PAD_NANDF_RB1__PATA_IORDY			202
+MX51_PAD_NANDF_RB1__SD4_CMD			203
+MX51_PAD_NANDF_RB2__DISP2_WAIT			204
+MX51_PAD_NANDF_RB2__ECSPI2_SCLK			205
+MX51_PAD_NANDF_RB2__FEC_COL			206
+MX51_PAD_NANDF_RB2__GPIO3_10			207
+MX51_PAD_NANDF_RB2__NANDF_RB2			208
+MX51_PAD_NANDF_RB2__USBH3_H3_DP			209
+MX51_PAD_NANDF_RB2__USBH3_NXT			210
+MX51_PAD_NANDF_RB3__DISP1_WAIT			211
+MX51_PAD_NANDF_RB3__ECSPI2_MISO			212
+MX51_PAD_NANDF_RB3__FEC_RX_CLK			213
+MX51_PAD_NANDF_RB3__GPIO3_11			214
+MX51_PAD_NANDF_RB3__NANDF_RB3			215
+MX51_PAD_NANDF_RB3__USBH3_CLK			216
+MX51_PAD_NANDF_RB3__USBH3_H3_DM			217
+MX51_PAD_GPIO_NAND__GPIO_NAND			218
+MX51_PAD_GPIO_NAND__PATA_INTRQ			219
+MX51_PAD_NANDF_CS0__GPIO3_16			220
+MX51_PAD_NANDF_CS0__NANDF_CS0			221
+MX51_PAD_NANDF_CS1__GPIO3_17			222
+MX51_PAD_NANDF_CS1__NANDF_CS1			223
+MX51_PAD_NANDF_CS2__CSPI_SCLK			224
+MX51_PAD_NANDF_CS2__FEC_TX_ER			225
+MX51_PAD_NANDF_CS2__GPIO3_18			226
+MX51_PAD_NANDF_CS2__NANDF_CS2			227
+MX51_PAD_NANDF_CS2__PATA_CS_0			228
+MX51_PAD_NANDF_CS2__SD4_CLK			229
+MX51_PAD_NANDF_CS2__USBH3_H1_DP			230
+MX51_PAD_NANDF_CS3__FEC_MDC			231
+MX51_PAD_NANDF_CS3__GPIO3_19			232
+MX51_PAD_NANDF_CS3__NANDF_CS3			233
+MX51_PAD_NANDF_CS3__PATA_CS_1			234
+MX51_PAD_NANDF_CS3__SD4_DAT0			235
+MX51_PAD_NANDF_CS3__USBH3_H1_DM			236
+MX51_PAD_NANDF_CS4__FEC_TDATA1			237
+MX51_PAD_NANDF_CS4__GPIO3_20			238
+MX51_PAD_NANDF_CS4__NANDF_CS4			239
+MX51_PAD_NANDF_CS4__PATA_DA_0			240
+MX51_PAD_NANDF_CS4__SD4_DAT1			241
+MX51_PAD_NANDF_CS4__USBH3_STP			242
+MX51_PAD_NANDF_CS5__FEC_TDATA2			243
+MX51_PAD_NANDF_CS5__GPIO3_21			244
+MX51_PAD_NANDF_CS5__NANDF_CS5			245
+MX51_PAD_NANDF_CS5__PATA_DA_1			246
+MX51_PAD_NANDF_CS5__SD4_DAT2			247
+MX51_PAD_NANDF_CS5__USBH3_DIR			248
+MX51_PAD_NANDF_CS6__CSPI_SS3			249
+MX51_PAD_NANDF_CS6__FEC_TDATA3			250
+MX51_PAD_NANDF_CS6__GPIO3_22			251
+MX51_PAD_NANDF_CS6__NANDF_CS6			252
+MX51_PAD_NANDF_CS6__PATA_DA_2			253
+MX51_PAD_NANDF_CS6__SD4_DAT3			254
+MX51_PAD_NANDF_CS7__FEC_TX_EN			255
+MX51_PAD_NANDF_CS7__GPIO3_23			256
+MX51_PAD_NANDF_CS7__NANDF_CS7			257
+MX51_PAD_NANDF_CS7__SD3_CLK			258
+MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0		259
+MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK		260
+MX51_PAD_NANDF_RDY_INT__GPIO3_24		261
+MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT		262
+MX51_PAD_NANDF_RDY_INT__SD3_CMD			263
+MX51_PAD_NANDF_D15__ECSPI2_MOSI			264
+MX51_PAD_NANDF_D15__GPIO3_25			265
+MX51_PAD_NANDF_D15__NANDF_D15			266
+MX51_PAD_NANDF_D15__PATA_DATA15			267
+MX51_PAD_NANDF_D15__SD3_DAT7			268
+MX51_PAD_NANDF_D14__ECSPI2_SS3			269
+MX51_PAD_NANDF_D14__GPIO3_26			270
+MX51_PAD_NANDF_D14__NANDF_D14			271
+MX51_PAD_NANDF_D14__PATA_DATA14			272
+MX51_PAD_NANDF_D14__SD3_DAT6			273
+MX51_PAD_NANDF_D13__ECSPI2_SS2			274
+MX51_PAD_NANDF_D13__GPIO3_27			275
+MX51_PAD_NANDF_D13__NANDF_D13			276
+MX51_PAD_NANDF_D13__PATA_DATA13			277
+MX51_PAD_NANDF_D13__SD3_DAT5			278
+MX51_PAD_NANDF_D12__ECSPI2_SS1			279
+MX51_PAD_NANDF_D12__GPIO3_28			280
+MX51_PAD_NANDF_D12__NANDF_D12			281
+MX51_PAD_NANDF_D12__PATA_DATA12			282
+MX51_PAD_NANDF_D12__SD3_DAT4			283
+MX51_PAD_NANDF_D11__FEC_RX_DV			284
+MX51_PAD_NANDF_D11__GPIO3_29			285
+MX51_PAD_NANDF_D11__NANDF_D11			286
+MX51_PAD_NANDF_D11__PATA_DATA11			287
+MX51_PAD_NANDF_D11__SD3_DATA3			288
+MX51_PAD_NANDF_D10__GPIO3_30			289
+MX51_PAD_NANDF_D10__NANDF_D10			290
+MX51_PAD_NANDF_D10__PATA_DATA10			291
+MX51_PAD_NANDF_D10__SD3_DATA2			292
+MX51_PAD_NANDF_D9__FEC_RDATA0			293
+MX51_PAD_NANDF_D9__GPIO3_31			294
+MX51_PAD_NANDF_D9__NANDF_D9			295
+MX51_PAD_NANDF_D9__PATA_DATA9			296
+MX51_PAD_NANDF_D9__SD3_DATA1			297
+MX51_PAD_NANDF_D8__FEC_TDATA0			298
+MX51_PAD_NANDF_D8__GPIO4_0			299
+MX51_PAD_NANDF_D8__NANDF_D8			300
+MX51_PAD_NANDF_D8__PATA_DATA8			301
+MX51_PAD_NANDF_D8__SD3_DATA0			302
+MX51_PAD_NANDF_D7__GPIO4_1			303
+MX51_PAD_NANDF_D7__NANDF_D7			304
+MX51_PAD_NANDF_D7__PATA_DATA7			305
+MX51_PAD_NANDF_D7__USBH3_DATA0			306
+MX51_PAD_NANDF_D6__GPIO4_2			307
+MX51_PAD_NANDF_D6__NANDF_D6			308
+MX51_PAD_NANDF_D6__PATA_DATA6			309
+MX51_PAD_NANDF_D6__SD4_LCTL			310
+MX51_PAD_NANDF_D6__USBH3_DATA1			311
+MX51_PAD_NANDF_D5__GPIO4_3			312
+MX51_PAD_NANDF_D5__NANDF_D5			313
+MX51_PAD_NANDF_D5__PATA_DATA5			314
+MX51_PAD_NANDF_D5__SD4_WP			315
+MX51_PAD_NANDF_D5__USBH3_DATA2			316
+MX51_PAD_NANDF_D4__GPIO4_4			317
+MX51_PAD_NANDF_D4__NANDF_D4			318
+MX51_PAD_NANDF_D4__PATA_DATA4			319
+MX51_PAD_NANDF_D4__SD4_CD			320
+MX51_PAD_NANDF_D4__USBH3_DATA3			321
+MX51_PAD_NANDF_D3__GPIO4_5			322
+MX51_PAD_NANDF_D3__NANDF_D3			323
+MX51_PAD_NANDF_D3__PATA_DATA3			324
+MX51_PAD_NANDF_D3__SD4_DAT4			325
+MX51_PAD_NANDF_D3__USBH3_DATA4			326
+MX51_PAD_NANDF_D2__GPIO4_6			327
+MX51_PAD_NANDF_D2__NANDF_D2			328
+MX51_PAD_NANDF_D2__PATA_DATA2			329
+MX51_PAD_NANDF_D2__SD4_DAT5			330
+MX51_PAD_NANDF_D2__USBH3_DATA5			331
+MX51_PAD_NANDF_D1__GPIO4_7			332
+MX51_PAD_NANDF_D1__NANDF_D1			333
+MX51_PAD_NANDF_D1__PATA_DATA1			334
+MX51_PAD_NANDF_D1__SD4_DAT6			335
+MX51_PAD_NANDF_D1__USBH3_DATA6			336
+MX51_PAD_NANDF_D0__GPIO4_8			337
+MX51_PAD_NANDF_D0__NANDF_D0			338
+MX51_PAD_NANDF_D0__PATA_DATA0			339
+MX51_PAD_NANDF_D0__SD4_DAT7			340
+MX51_PAD_NANDF_D0__USBH3_DATA7			341
+MX51_PAD_CSI1_D8__CSI1_D8			342
+MX51_PAD_CSI1_D8__GPIO3_12			343
+MX51_PAD_CSI1_D9__CSI1_D9			344
+MX51_PAD_CSI1_D9__GPIO3_13			345
+MX51_PAD_CSI1_D10__CSI1_D10			346
+MX51_PAD_CSI1_D11__CSI1_D11			347
+MX51_PAD_CSI1_D12__CSI1_D12			348
+MX51_PAD_CSI1_D13__CSI1_D13			349
+MX51_PAD_CSI1_D14__CSI1_D14			350
+MX51_PAD_CSI1_D15__CSI1_D15			351
+MX51_PAD_CSI1_D16__CSI1_D16			352
+MX51_PAD_CSI1_D17__CSI1_D17			353
+MX51_PAD_CSI1_D18__CSI1_D18			354
+MX51_PAD_CSI1_D19__CSI1_D19			355
+MX51_PAD_CSI1_VSYNC__CSI1_VSYNC			356
+MX51_PAD_CSI1_VSYNC__GPIO3_14			357
+MX51_PAD_CSI1_HSYNC__CSI1_HSYNC			358
+MX51_PAD_CSI1_HSYNC__GPIO3_15			359
+MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK		360
+MX51_PAD_CSI1_MCLK__CSI1_MCLK			361
+MX51_PAD_CSI2_D12__CSI2_D12			362
+MX51_PAD_CSI2_D12__GPIO4_9			363
+MX51_PAD_CSI2_D13__CSI2_D13			364
+MX51_PAD_CSI2_D13__GPIO4_10			365
+MX51_PAD_CSI2_D14__CSI2_D14			366
+MX51_PAD_CSI2_D15__CSI2_D15			367
+MX51_PAD_CSI2_D16__CSI2_D16			368
+MX51_PAD_CSI2_D17__CSI2_D17			369
+MX51_PAD_CSI2_D18__CSI2_D18			370
+MX51_PAD_CSI2_D18__GPIO4_11			371
+MX51_PAD_CSI2_D19__CSI2_D19			372
+MX51_PAD_CSI2_D19__GPIO4_12			373
+MX51_PAD_CSI2_VSYNC__CSI2_VSYNC			374
+MX51_PAD_CSI2_VSYNC__GPIO4_13			375
+MX51_PAD_CSI2_HSYNC__CSI2_HSYNC			376
+MX51_PAD_CSI2_HSYNC__GPIO4_14			377
+MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK		378
+MX51_PAD_CSI2_PIXCLK__GPIO4_15			379
+MX51_PAD_I2C1_CLK__GPIO4_16			380
+MX51_PAD_I2C1_CLK__I2C1_CLK			381
+MX51_PAD_I2C1_DAT__GPIO4_17			382
+MX51_PAD_I2C1_DAT__I2C1_DAT			383
+MX51_PAD_AUD3_BB_TXD__AUD3_TXD			384
+MX51_PAD_AUD3_BB_TXD__GPIO4_18			385
+MX51_PAD_AUD3_BB_RXD__AUD3_RXD			386
+MX51_PAD_AUD3_BB_RXD__GPIO4_19			387
+MX51_PAD_AUD3_BB_RXD__UART3_RXD			388
+MX51_PAD_AUD3_BB_CK__AUD3_TXC			389
+MX51_PAD_AUD3_BB_CK__GPIO4_20			390
+MX51_PAD_AUD3_BB_FS__AUD3_TXFS			391
+MX51_PAD_AUD3_BB_FS__GPIO4_21			392
+MX51_PAD_AUD3_BB_FS__UART3_TXD			393
+MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI		394
+MX51_PAD_CSPI1_MOSI__GPIO4_22			395
+MX51_PAD_CSPI1_MOSI__I2C1_SDA			396
+MX51_PAD_CSPI1_MISO__AUD4_RXD			397
+MX51_PAD_CSPI1_MISO__ECSPI1_MISO		398
+MX51_PAD_CSPI1_MISO__GPIO4_23			399
+MX51_PAD_CSPI1_SS0__AUD4_TXC			400
+MX51_PAD_CSPI1_SS0__ECSPI1_SS0			401
+MX51_PAD_CSPI1_SS0__GPIO4_24			402
+MX51_PAD_CSPI1_SS1__AUD4_TXD			403
+MX51_PAD_CSPI1_SS1__ECSPI1_SS1			404
+MX51_PAD_CSPI1_SS1__GPIO4_25			405
+MX51_PAD_CSPI1_RDY__AUD4_TXFS			406
+MX51_PAD_CSPI1_RDY__ECSPI1_RDY			407
+MX51_PAD_CSPI1_RDY__GPIO4_26			408
+MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK		409
+MX51_PAD_CSPI1_SCLK__GPIO4_27			410
+MX51_PAD_CSPI1_SCLK__I2C1_SCL			411
+MX51_PAD_UART1_RXD__GPIO4_28			412
+MX51_PAD_UART1_RXD__UART1_RXD			413
+MX51_PAD_UART1_TXD__GPIO4_29			414
+MX51_PAD_UART1_TXD__PWM2_PWMO			415
+MX51_PAD_UART1_TXD__UART1_TXD			416
+MX51_PAD_UART1_RTS__GPIO4_30			417
+MX51_PAD_UART1_RTS__UART1_RTS			418
+MX51_PAD_UART1_CTS__GPIO4_31			419
+MX51_PAD_UART1_CTS__UART1_CTS			420
+MX51_PAD_UART2_RXD__FIRI_TXD			421
+MX51_PAD_UART2_RXD__GPIO1_20			422
+MX51_PAD_UART2_RXD__UART2_RXD			423
+MX51_PAD_UART2_TXD__FIRI_RXD			424
+MX51_PAD_UART2_TXD__GPIO1_21			425
+MX51_PAD_UART2_TXD__UART2_TXD			426
+MX51_PAD_UART3_RXD__CSI1_D0			427
+MX51_PAD_UART3_RXD__GPIO1_22			428
+MX51_PAD_UART3_RXD__UART1_DTR			429
+MX51_PAD_UART3_RXD__UART3_RXD			430
+MX51_PAD_UART3_TXD__CSI1_D1			431
+MX51_PAD_UART3_TXD__GPIO1_23			432
+MX51_PAD_UART3_TXD__UART1_DSR			433
+MX51_PAD_UART3_TXD__UART3_TXD			434
+MX51_PAD_OWIRE_LINE__GPIO1_24			435
+MX51_PAD_OWIRE_LINE__OWIRE_LINE			436
+MX51_PAD_OWIRE_LINE__SPDIF_OUT			437
+MX51_PAD_KEY_ROW0__KEY_ROW0			438
+MX51_PAD_KEY_ROW1__KEY_ROW1			439
+MX51_PAD_KEY_ROW2__KEY_ROW2			440
+MX51_PAD_KEY_ROW3__KEY_ROW3			441
+MX51_PAD_KEY_COL0__KEY_COL0			442
+MX51_PAD_KEY_COL0__PLL1_BYP			443
+MX51_PAD_KEY_COL1__KEY_COL1			444
+MX51_PAD_KEY_COL1__PLL2_BYP			445
+MX51_PAD_KEY_COL2__KEY_COL2			446
+MX51_PAD_KEY_COL2__PLL3_BYP			447
+MX51_PAD_KEY_COL3__KEY_COL3			448
+MX51_PAD_KEY_COL4__I2C2_SCL			449
+MX51_PAD_KEY_COL4__KEY_COL4			450
+MX51_PAD_KEY_COL4__SPDIF_OUT1			451
+MX51_PAD_KEY_COL4__UART1_RI			452
+MX51_PAD_KEY_COL4__UART3_RTS			453
+MX51_PAD_KEY_COL5__I2C2_SDA			454
+MX51_PAD_KEY_COL5__KEY_COL5			455
+MX51_PAD_KEY_COL5__UART1_DCD			456
+MX51_PAD_KEY_COL5__UART3_CTS			457
+MX51_PAD_USBH1_CLK__CSPI_SCLK			458
+MX51_PAD_USBH1_CLK__GPIO1_25			459
+MX51_PAD_USBH1_CLK__I2C2_SCL			460
+MX51_PAD_USBH1_CLK__USBH1_CLK			461
+MX51_PAD_USBH1_DIR__CSPI_MOSI			462
+MX51_PAD_USBH1_DIR__GPIO1_26			463
+MX51_PAD_USBH1_DIR__I2C2_SDA			464
+MX51_PAD_USBH1_DIR__USBH1_DIR			465
+MX51_PAD_USBH1_STP__CSPI_RDY			466
+MX51_PAD_USBH1_STP__GPIO1_27			467
+MX51_PAD_USBH1_STP__UART3_RXD			468
+MX51_PAD_USBH1_STP__USBH1_STP			469
+MX51_PAD_USBH1_NXT__CSPI_MISO			470
+MX51_PAD_USBH1_NXT__GPIO1_28			471
+MX51_PAD_USBH1_NXT__UART3_TXD			472
+MX51_PAD_USBH1_NXT__USBH1_NXT			473
+MX51_PAD_USBH1_DATA0__GPIO1_11			474
+MX51_PAD_USBH1_DATA0__UART2_CTS			475
+MX51_PAD_USBH1_DATA0__USBH1_DATA0		476
+MX51_PAD_USBH1_DATA1__GPIO1_12			477
+MX51_PAD_USBH1_DATA1__UART2_RXD			478
+MX51_PAD_USBH1_DATA1__USBH1_DATA1		479
+MX51_PAD_USBH1_DATA2__GPIO1_13			480
+MX51_PAD_USBH1_DATA2__UART2_TXD			481
+MX51_PAD_USBH1_DATA2__USBH1_DATA2		482
+MX51_PAD_USBH1_DATA3__GPIO1_14			483
+MX51_PAD_USBH1_DATA3__UART2_RTS			484
+MX51_PAD_USBH1_DATA3__USBH1_DATA3		485
+MX51_PAD_USBH1_DATA4__CSPI_SS0			486
+MX51_PAD_USBH1_DATA4__GPIO1_15			487
+MX51_PAD_USBH1_DATA4__USBH1_DATA4		488
+MX51_PAD_USBH1_DATA5__CSPI_SS1			489
+MX51_PAD_USBH1_DATA5__GPIO1_16			490
+MX51_PAD_USBH1_DATA5__USBH1_DATA5		491
+MX51_PAD_USBH1_DATA6__CSPI_SS3			492
+MX51_PAD_USBH1_DATA6__GPIO1_17			493
+MX51_PAD_USBH1_DATA6__USBH1_DATA6		494
+MX51_PAD_USBH1_DATA7__ECSPI1_SS3		495
+MX51_PAD_USBH1_DATA7__ECSPI2_SS3		496
+MX51_PAD_USBH1_DATA7__GPIO1_18			497
+MX51_PAD_USBH1_DATA7__USBH1_DATA7		498
+MX51_PAD_DI1_PIN11__DI1_PIN11			499
+MX51_PAD_DI1_PIN11__ECSPI1_SS2			500
+MX51_PAD_DI1_PIN11__GPIO3_0			501
+MX51_PAD_DI1_PIN12__DI1_PIN12			502
+MX51_PAD_DI1_PIN12__GPIO3_1			503
+MX51_PAD_DI1_PIN13__DI1_PIN13			504
+MX51_PAD_DI1_PIN13__GPIO3_2			505
+MX51_PAD_DI1_D0_CS__DI1_D0_CS			506
+MX51_PAD_DI1_D0_CS__GPIO3_3			507
+MX51_PAD_DI1_D1_CS__DI1_D1_CS			508
+MX51_PAD_DI1_D1_CS__DISP1_PIN14			509
+MX51_PAD_DI1_D1_CS__DISP1_PIN5			510
+MX51_PAD_DI1_D1_CS__GPIO3_4			511
+MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1		512
+MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN		513
+MX51_PAD_DISPB2_SER_DIN__GPIO3_5		514
+MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6		515
+MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO		516
+MX51_PAD_DISPB2_SER_DIO__GPIO3_6		517
+MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17		518
+MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7		519
+MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK		520
+MX51_PAD_DISPB2_SER_CLK__GPIO3_7		521
+MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK		522
+MX51_PAD_DISPB2_SER_RS__DISP1_PIN16		523
+MX51_PAD_DISPB2_SER_RS__DISP1_PIN8		524
+MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS		525
+MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS		526
+MX51_PAD_DISPB2_SER_RS__GPIO3_8			527
+MX51_PAD_DISP1_DAT0__DISP1_DAT0			528
+MX51_PAD_DISP1_DAT1__DISP1_DAT1			529
+MX51_PAD_DISP1_DAT2__DISP1_DAT2			530
+MX51_PAD_DISP1_DAT3__DISP1_DAT3			531
+MX51_PAD_DISP1_DAT4__DISP1_DAT4			532
+MX51_PAD_DISP1_DAT5__DISP1_DAT5			533
+MX51_PAD_DISP1_DAT6__BOOT_USB_SRC		534
+MX51_PAD_DISP1_DAT6__DISP1_DAT6			535
+MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG		536
+MX51_PAD_DISP1_DAT7__DISP1_DAT7			537
+MX51_PAD_DISP1_DAT8__BOOT_SRC0			538
+MX51_PAD_DISP1_DAT8__DISP1_DAT8			539
+MX51_PAD_DISP1_DAT9__BOOT_SRC1			540
+MX51_PAD_DISP1_DAT9__DISP1_DAT9			541
+MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE		542
+MX51_PAD_DISP1_DAT10__DISP1_DAT10		543
+MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2		544
+MX51_PAD_DISP1_DAT11__DISP1_DAT11		545
+MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL		546
+MX51_PAD_DISP1_DAT12__DISP1_DAT12		547
+MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0		548
+MX51_PAD_DISP1_DAT13__DISP1_DAT13		549
+MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1		550
+MX51_PAD_DISP1_DAT14__DISP1_DAT14		551
+MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH		552
+MX51_PAD_DISP1_DAT15__DISP1_DAT15		553
+MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0		554
+MX51_PAD_DISP1_DAT16__DISP1_DAT16		555
+MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1		556
+MX51_PAD_DISP1_DAT17__DISP1_DAT17		557
+MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0		558
+MX51_PAD_DISP1_DAT18__DISP1_DAT18		559
+MX51_PAD_DISP1_DAT18__DISP2_PIN11		560
+MX51_PAD_DISP1_DAT18__DISP2_PIN5		561
+MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1		562
+MX51_PAD_DISP1_DAT19__DISP1_DAT19		563
+MX51_PAD_DISP1_DAT19__DISP2_PIN12		564
+MX51_PAD_DISP1_DAT19__DISP2_PIN6		565
+MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0		566
+MX51_PAD_DISP1_DAT20__DISP1_DAT20		567
+MX51_PAD_DISP1_DAT20__DISP2_PIN13		568
+MX51_PAD_DISP1_DAT20__DISP2_PIN7		569
+MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1		570
+MX51_PAD_DISP1_DAT21__DISP1_DAT21		571
+MX51_PAD_DISP1_DAT21__DISP2_PIN14		572
+MX51_PAD_DISP1_DAT21__DISP2_PIN8		573
+MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0		574
+MX51_PAD_DISP1_DAT22__DISP1_DAT22		575
+MX51_PAD_DISP1_DAT22__DISP2_D0_CS		576
+MX51_PAD_DISP1_DAT22__DISP2_DAT16		577
+MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1		578
+MX51_PAD_DISP1_DAT23__DISP1_DAT23		579
+MX51_PAD_DISP1_DAT23__DISP2_D1_CS		580
+MX51_PAD_DISP1_DAT23__DISP2_DAT17		581
+MX51_PAD_DISP1_DAT23__DISP2_SER_CS		582
+MX51_PAD_DI1_PIN3__DI1_PIN3			583
+MX51_PAD_DI1_PIN2__DI1_PIN2			584
+MX51_PAD_DI_GP2__DISP1_SER_CLK			585
+MX51_PAD_DI_GP2__DISP2_WAIT			586
+MX51_PAD_DI_GP3__CSI1_DATA_EN			587
+MX51_PAD_DI_GP3__DISP1_SER_DIO			588
+MX51_PAD_DI_GP3__FEC_TX_ER			589
+MX51_PAD_DI2_PIN4__CSI2_DATA_EN			590
+MX51_PAD_DI2_PIN4__DI2_PIN4			591
+MX51_PAD_DI2_PIN4__FEC_CRS			592
+MX51_PAD_DI2_PIN2__DI2_PIN2			593
+MX51_PAD_DI2_PIN2__FEC_MDC			594
+MX51_PAD_DI2_PIN3__DI2_PIN3			595
+MX51_PAD_DI2_PIN3__FEC_MDIO			596
+MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK		597
+MX51_PAD_DI2_DISP_CLK__FEC_RDATA1		598
+MX51_PAD_DI_GP4__DI2_PIN15			599
+MX51_PAD_DI_GP4__DISP1_SER_DIN			600
+MX51_PAD_DI_GP4__DISP2_PIN1			601
+MX51_PAD_DI_GP4__FEC_RDATA2			602
+MX51_PAD_DISP2_DAT0__DISP2_DAT0			603
+MX51_PAD_DISP2_DAT0__FEC_RDATA3			604
+MX51_PAD_DISP2_DAT0__KEY_COL6			605
+MX51_PAD_DISP2_DAT0__UART3_RXD			606
+MX51_PAD_DISP2_DAT0__USBH3_CLK			607
+MX51_PAD_DISP2_DAT1__DISP2_DAT1			608
+MX51_PAD_DISP2_DAT1__FEC_RX_ER			609
+MX51_PAD_DISP2_DAT1__KEY_COL7			610
+MX51_PAD_DISP2_DAT1__UART3_TXD			611
+MX51_PAD_DISP2_DAT1__USBH3_DIR			612
+MX51_PAD_DISP2_DAT2__DISP2_DAT2			613
+MX51_PAD_DISP2_DAT3__DISP2_DAT3			614
+MX51_PAD_DISP2_DAT4__DISP2_DAT4			615
+MX51_PAD_DISP2_DAT5__DISP2_DAT5			616
+MX51_PAD_DISP2_DAT6__DISP2_DAT6			617
+MX51_PAD_DISP2_DAT6__FEC_TDATA1			618
+MX51_PAD_DISP2_DAT6__GPIO1_19			619
+MX51_PAD_DISP2_DAT6__KEY_ROW4			620
+MX51_PAD_DISP2_DAT6__USBH3_STP			621
+MX51_PAD_DISP2_DAT7__DISP2_DAT7			622
+MX51_PAD_DISP2_DAT7__FEC_TDATA2			623
+MX51_PAD_DISP2_DAT7__GPIO1_29			624
+MX51_PAD_DISP2_DAT7__KEY_ROW5			625
+MX51_PAD_DISP2_DAT7__USBH3_NXT			626
+MX51_PAD_DISP2_DAT8__DISP2_DAT8			627
+MX51_PAD_DISP2_DAT8__FEC_TDATA3			628
+MX51_PAD_DISP2_DAT8__GPIO1_30			629
+MX51_PAD_DISP2_DAT8__KEY_ROW6			630
+MX51_PAD_DISP2_DAT8__USBH3_DATA0		631
+MX51_PAD_DISP2_DAT9__AUD6_RXC			632
+MX51_PAD_DISP2_DAT9__DISP2_DAT9			633
+MX51_PAD_DISP2_DAT9__FEC_TX_EN			634
+MX51_PAD_DISP2_DAT9__GPIO1_31			635
+MX51_PAD_DISP2_DAT9__USBH3_DATA1		636
+MX51_PAD_DISP2_DAT10__DISP2_DAT10		637
+MX51_PAD_DISP2_DAT10__DISP2_SER_CS		638
+MX51_PAD_DISP2_DAT10__FEC_COL			639
+MX51_PAD_DISP2_DAT10__KEY_ROW7			640
+MX51_PAD_DISP2_DAT10__USBH3_DATA2		641
+MX51_PAD_DISP2_DAT11__AUD6_TXD			642
+MX51_PAD_DISP2_DAT11__DISP2_DAT11		643
+MX51_PAD_DISP2_DAT11__FEC_RX_CLK		644
+MX51_PAD_DISP2_DAT11__GPIO1_10			645
+MX51_PAD_DISP2_DAT11__USBH3_DATA3		646
+MX51_PAD_DISP2_DAT12__AUD6_RXD			647
+MX51_PAD_DISP2_DAT12__DISP2_DAT12		648
+MX51_PAD_DISP2_DAT12__FEC_RX_DV			649
+MX51_PAD_DISP2_DAT12__USBH3_DATA4		650
+MX51_PAD_DISP2_DAT13__AUD6_TXC			651
+MX51_PAD_DISP2_DAT13__DISP2_DAT13		652
+MX51_PAD_DISP2_DAT13__FEC_TX_CLK		653
+MX51_PAD_DISP2_DAT13__USBH3_DATA5		654
+MX51_PAD_DISP2_DAT14__AUD6_TXFS			655
+MX51_PAD_DISP2_DAT14__DISP2_DAT14		656
+MX51_PAD_DISP2_DAT14__FEC_RDATA0		657
+MX51_PAD_DISP2_DAT14__USBH3_DATA6		658
+MX51_PAD_DISP2_DAT15__AUD6_RXFS			659
+MX51_PAD_DISP2_DAT15__DISP1_SER_CS		660
+MX51_PAD_DISP2_DAT15__DISP2_DAT15		661
+MX51_PAD_DISP2_DAT15__FEC_TDATA0		662
+MX51_PAD_DISP2_DAT15__USBH3_DATA7		663
+MX51_PAD_SD1_CMD__AUD5_RXFS			664
+MX51_PAD_SD1_CMD__CSPI_MOSI			665
+MX51_PAD_SD1_CMD__SD1_CMD			666
+MX51_PAD_SD1_CLK__AUD5_RXC			667
+MX51_PAD_SD1_CLK__CSPI_SCLK			668
+MX51_PAD_SD1_CLK__SD1_CLK			669
+MX51_PAD_SD1_DATA0__AUD5_TXD			670
+MX51_PAD_SD1_DATA0__CSPI_MISO			671
+MX51_PAD_SD1_DATA0__SD1_DATA0			672
+MX51_PAD_EIM_DA0__EIM_DA0			673
+MX51_PAD_EIM_DA1__EIM_DA1			674
+MX51_PAD_EIM_DA2__EIM_DA2			675
+MX51_PAD_EIM_DA3__EIM_DA3			676
+MX51_PAD_SD1_DATA1__AUD5_RXD			677
+MX51_PAD_SD1_DATA1__SD1_DATA1			678
+MX51_PAD_EIM_DA4__EIM_DA4			679
+MX51_PAD_EIM_DA5__EIM_DA5			680
+MX51_PAD_EIM_DA6__EIM_DA6			681
+MX51_PAD_EIM_DA7__EIM_DA7			682
+MX51_PAD_SD1_DATA2__AUD5_TXC			683
+MX51_PAD_SD1_DATA2__SD1_DATA2			684
+MX51_PAD_EIM_DA10__EIM_DA10			685
+MX51_PAD_EIM_DA11__EIM_DA11			686
+MX51_PAD_EIM_DA8__EIM_DA8			687
+MX51_PAD_EIM_DA9__EIM_DA9			688
+MX51_PAD_SD1_DATA3__AUD5_TXFS			689
+MX51_PAD_SD1_DATA3__CSPI_SS1			690
+MX51_PAD_SD1_DATA3__SD1_DATA3			691
+MX51_PAD_GPIO1_0__CSPI_SS2			692
+MX51_PAD_GPIO1_0__GPIO1_0			693
+MX51_PAD_GPIO1_0__SD1_CD			694
+MX51_PAD_GPIO1_1__CSPI_MISO			695
+MX51_PAD_GPIO1_1__GPIO1_1			696
+MX51_PAD_GPIO1_1__SD1_WP			697
+MX51_PAD_EIM_DA12__EIM_DA12			698
+MX51_PAD_EIM_DA13__EIM_DA13			699
+MX51_PAD_EIM_DA14__EIM_DA14			700
+MX51_PAD_EIM_DA15__EIM_DA15			701
+MX51_PAD_SD2_CMD__CSPI_MOSI			702
+MX51_PAD_SD2_CMD__I2C1_SCL			703
+MX51_PAD_SD2_CMD__SD2_CMD			704
+MX51_PAD_SD2_CLK__CSPI_SCLK			705
+MX51_PAD_SD2_CLK__I2C1_SDA			706
+MX51_PAD_SD2_CLK__SD2_CLK			707
+MX51_PAD_SD2_DATA0__CSPI_MISO			708
+MX51_PAD_SD2_DATA0__SD1_DAT4			709
+MX51_PAD_SD2_DATA0__SD2_DATA0			710
+MX51_PAD_SD2_DATA1__SD1_DAT5			711
+MX51_PAD_SD2_DATA1__SD2_DATA1			712
+MX51_PAD_SD2_DATA1__USBH3_H2_DP			713
+MX51_PAD_SD2_DATA2__SD1_DAT6			714
+MX51_PAD_SD2_DATA2__SD2_DATA2			715
+MX51_PAD_SD2_DATA2__USBH3_H2_DM			716
+MX51_PAD_SD2_DATA3__CSPI_SS2			717
+MX51_PAD_SD2_DATA3__SD1_DAT7			718
+MX51_PAD_SD2_DATA3__SD2_DATA3			719
+MX51_PAD_GPIO1_2__CCM_OUT_2			720
+MX51_PAD_GPIO1_2__GPIO1_2			721
+MX51_PAD_GPIO1_2__I2C2_SCL			722
+MX51_PAD_GPIO1_2__PLL1_BYP			723
+MX51_PAD_GPIO1_2__PWM1_PWMO			724
+MX51_PAD_GPIO1_3__GPIO1_3			725
+MX51_PAD_GPIO1_3__I2C2_SDA			726
+MX51_PAD_GPIO1_3__PLL2_BYP			727
+MX51_PAD_GPIO1_3__PWM2_PWMO			728
+MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ		729
+MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B		730
+MX51_PAD_GPIO1_4__DISP2_EXT_CLK			731
+MX51_PAD_GPIO1_4__EIM_RDY			732
+MX51_PAD_GPIO1_4__GPIO1_4			733
+MX51_PAD_GPIO1_4__WDOG1_WDOG_B			734
+MX51_PAD_GPIO1_5__CSI2_MCLK			735
+MX51_PAD_GPIO1_5__DISP2_PIN16			736
+MX51_PAD_GPIO1_5__GPIO1_5			737
+MX51_PAD_GPIO1_5__WDOG2_WDOG_B			738
+MX51_PAD_GPIO1_6__DISP2_PIN17			739
+MX51_PAD_GPIO1_6__GPIO1_6			740
+MX51_PAD_GPIO1_6__REF_EN_B			741
+MX51_PAD_GPIO1_7__CCM_OUT_0			742
+MX51_PAD_GPIO1_7__GPIO1_7			743
+MX51_PAD_GPIO1_7__SD2_WP			744
+MX51_PAD_GPIO1_7__SPDIF_OUT1			745
+MX51_PAD_GPIO1_8__CSI2_DATA_EN			746
+MX51_PAD_GPIO1_8__GPIO1_8			747
+MX51_PAD_GPIO1_8__SD2_CD			748
+MX51_PAD_GPIO1_8__USBH3_PWR			749
+MX51_PAD_GPIO1_9__CCM_OUT_1			750
+MX51_PAD_GPIO1_9__DISP2_D1_CS			751
+MX51_PAD_GPIO1_9__DISP2_SER_CS			752
+MX51_PAD_GPIO1_9__GPIO1_9			753
+MX51_PAD_GPIO1_9__SD2_LCTL			754
+MX51_PAD_GPIO1_9__USBH3_OC			755

Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt

@@ -0,0 +1,918 @@
+* Freescale MXS Pin Controller
+
+The pins controlled by mxs pin controller are organized in banks, each bank
+has 32 pins.  Each pin has 4 multiplexing functions, and generally, the 4th
+function is GPIO.  The configuration on the pins includes drive strength,
+voltage and pull-up.
+
+Required properties:
+- compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
+- reg: Should contain the register physical address and length for the
+  pin controller.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices.
+
+The node of mxs pin controller acts as a container for an arbitrary number of
+subnodes.  Each of these subnodes represents some desired configuration for
+a group of pins, and only affects those parameters that are explicitly listed.
+In other words, a subnode that describes a drive strength parameter implies no
+information about pull-up. For this reason, even seemingly boolean values are
+actually tristates in this binding: unspecified, off, or on. Unspecified is
+represented as an absent property, and off/on are represented as integer
+values 0 and 1.
+
+Those subnodes under mxs pin controller node will fall into two categories.
+One is to set up a group of pins for a function, both mux selection and pin
+configurations, and it's called group node in the binding document.   The other
+one is to adjust the pin configuration for some particular pins that need a
+different configuration than what is defined in group node.  The binding
+document calls this type of node config node.
+
+On mxs, there is no hardware pin group. The pin group in this binding only
+means a group of pins put together for particular peripheral to work in
+particular function, like SSP0 functioning as mmc0-8bit.  That said, the
+group node should include all the pins needed for one function rather than
+having these pins defined in several group nodes.  It also means each of
+"pinctrl-*" phandle in client device node should only have one group node
+pointed in there, while the phandle can have multiple config node referenced
+there to adjust configurations for some pins in the group.
+
+Required subnode-properties:
+- fsl,pinmux-ids: An integer array.  Each integer in the array specify a pin
+  with given mux function, with bank, pin and mux packed as below.
+
+    [15..12] : bank number
+    [11..4]  : pin number
+    [3..0]   : mux selection
+
+  This integer with mux selection packed is used as an entity by both group
+  and config nodes to identify a pin.  The mux selection in the integer takes
+  effects only on group node, and will get ignored by driver with config node,
+  since config node is only meant to set up pin configurations.
+
+  Valid values for these integers are listed below.
+
+- reg: Should be the index of the group nodes for same function.  This property
+  is required only for group nodes, and should not be present in any config
+  nodes.
+
+Optional subnode-properties:
+- fsl,drive-strength: Integer.
+    0: 4 mA
+    1: 8 mA
+    2: 12 mA
+    3: 16 mA
+- fsl,voltage: Integer.
+    0: 1.8 V
+    1: 3.3 V
+- fsl,pull-up: Integer.
+    0: Disable the internal pull-up
+    1: Enable the internal pull-up
+
+Examples:
+
+pinctrl@80018000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,imx28-pinctrl";
+	reg = <0x80018000 2000>;
+
+	mmc0_8bit_pins_a: mmc0-8bit@0 {
+		reg = <0>;
+		fsl,pinmux-ids = <
+			0x2000 0x2010 0x2020 0x2030
+			0x2040 0x2050 0x2060 0x2070
+			0x2080 0x2090 0x20a0>;
+		fsl,drive-strength = <1>;
+		fsl,voltage = <1>;
+		fsl,pull-up = <1>;
+	};
+
+	mmc_cd_cfg: mmc-cd-cfg {
+		fsl,pinmux-ids = <0x2090>;
+		fsl,pull-up = <0>;
+	};
+
+	mmc_sck_cfg: mmc-sck-cfg {
+		fsl,pinmux-ids = <0x20a0>;
+		fsl,drive-strength = <2>;
+		fsl,pull-up = <0>;
+	};
+};
+
+In this example, group node mmc0-8bit defines a group of pins for mxs SSP0
+to function as a 8-bit mmc device, with 8mA, 3.3V and pull-up configurations
+applied on all these pins.  And config nodes mmc-cd-cfg and mmc-sck-cfg are
+adjusting the configuration for pins card-detection and clock from what group
+node mmc0-8bit defines.  Only the configuration properties to be adjusted need
+to be listed in the config nodes.
+
+Valid values for i.MX28 pinmux-id:
+
+pinmux						id
+------						--
+MX28_PAD_GPMI_D00__GPMI_D0			0x0000
+MX28_PAD_GPMI_D01__GPMI_D1			0x0010
+MX28_PAD_GPMI_D02__GPMI_D2			0x0020
+MX28_PAD_GPMI_D03__GPMI_D3			0x0030
+MX28_PAD_GPMI_D04__GPMI_D4			0x0040
+MX28_PAD_GPMI_D05__GPMI_D5			0x0050
+MX28_PAD_GPMI_D06__GPMI_D6			0x0060
+MX28_PAD_GPMI_D07__GPMI_D7			0x0070
+MX28_PAD_GPMI_CE0N__GPMI_CE0N			0x0100
+MX28_PAD_GPMI_CE1N__GPMI_CE1N			0x0110
+MX28_PAD_GPMI_CE2N__GPMI_CE2N			0x0120
+MX28_PAD_GPMI_CE3N__GPMI_CE3N			0x0130
+MX28_PAD_GPMI_RDY0__GPMI_READY0			0x0140
+MX28_PAD_GPMI_RDY1__GPMI_READY1			0x0150
+MX28_PAD_GPMI_RDY2__GPMI_READY2			0x0160
+MX28_PAD_GPMI_RDY3__GPMI_READY3			0x0170
+MX28_PAD_GPMI_RDN__GPMI_RDN			0x0180
+MX28_PAD_GPMI_WRN__GPMI_WRN			0x0190
+MX28_PAD_GPMI_ALE__GPMI_ALE			0x01a0
+MX28_PAD_GPMI_CLE__GPMI_CLE			0x01b0
+MX28_PAD_GPMI_RESETN__GPMI_RESETN		0x01c0
+MX28_PAD_LCD_D00__LCD_D0			0x1000
+MX28_PAD_LCD_D01__LCD_D1			0x1010
+MX28_PAD_LCD_D02__LCD_D2			0x1020
+MX28_PAD_LCD_D03__LCD_D3			0x1030
+MX28_PAD_LCD_D04__LCD_D4			0x1040
+MX28_PAD_LCD_D05__LCD_D5			0x1050
+MX28_PAD_LCD_D06__LCD_D6			0x1060
+MX28_PAD_LCD_D07__LCD_D7			0x1070
+MX28_PAD_LCD_D08__LCD_D8			0x1080
+MX28_PAD_LCD_D09__LCD_D9			0x1090
+MX28_PAD_LCD_D10__LCD_D10			0x10a0
+MX28_PAD_LCD_D11__LCD_D11			0x10b0
+MX28_PAD_LCD_D12__LCD_D12			0x10c0
+MX28_PAD_LCD_D13__LCD_D13			0x10d0
+MX28_PAD_LCD_D14__LCD_D14			0x10e0
+MX28_PAD_LCD_D15__LCD_D15			0x10f0
+MX28_PAD_LCD_D16__LCD_D16			0x1100
+MX28_PAD_LCD_D17__LCD_D17			0x1110
+MX28_PAD_LCD_D18__LCD_D18			0x1120
+MX28_PAD_LCD_D19__LCD_D19			0x1130
+MX28_PAD_LCD_D20__LCD_D20			0x1140
+MX28_PAD_LCD_D21__LCD_D21			0x1150
+MX28_PAD_LCD_D22__LCD_D22			0x1160
+MX28_PAD_LCD_D23__LCD_D23			0x1170
+MX28_PAD_LCD_RD_E__LCD_RD_E			0x1180
+MX28_PAD_LCD_WR_RWN__LCD_WR_RWN			0x1190
+MX28_PAD_LCD_RS__LCD_RS				0x11a0
+MX28_PAD_LCD_CS__LCD_CS				0x11b0
+MX28_PAD_LCD_VSYNC__LCD_VSYNC			0x11c0
+MX28_PAD_LCD_HSYNC__LCD_HSYNC			0x11d0
+MX28_PAD_LCD_DOTCLK__LCD_DOTCLK			0x11e0
+MX28_PAD_LCD_ENABLE__LCD_ENABLE			0x11f0
+MX28_PAD_SSP0_DATA0__SSP0_D0			0x2000
+MX28_PAD_SSP0_DATA1__SSP0_D1			0x2010
+MX28_PAD_SSP0_DATA2__SSP0_D2			0x2020
+MX28_PAD_SSP0_DATA3__SSP0_D3			0x2030
+MX28_PAD_SSP0_DATA4__SSP0_D4			0x2040
+MX28_PAD_SSP0_DATA5__SSP0_D5			0x2050
+MX28_PAD_SSP0_DATA6__SSP0_D6			0x2060
+MX28_PAD_SSP0_DATA7__SSP0_D7			0x2070
+MX28_PAD_SSP0_CMD__SSP0_CMD			0x2080
+MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT		0x2090
+MX28_PAD_SSP0_SCK__SSP0_SCK			0x20a0
+MX28_PAD_SSP1_SCK__SSP1_SCK			0x20c0
+MX28_PAD_SSP1_CMD__SSP1_CMD			0x20d0
+MX28_PAD_SSP1_DATA0__SSP1_D0			0x20e0
+MX28_PAD_SSP1_DATA3__SSP1_D3			0x20f0
+MX28_PAD_SSP2_SCK__SSP2_SCK			0x2100
+MX28_PAD_SSP2_MOSI__SSP2_CMD			0x2110
+MX28_PAD_SSP2_MISO__SSP2_D0			0x2120
+MX28_PAD_SSP2_SS0__SSP2_D3			0x2130
+MX28_PAD_SSP2_SS1__SSP2_D4			0x2140
+MX28_PAD_SSP2_SS2__SSP2_D5			0x2150
+MX28_PAD_SSP3_SCK__SSP3_SCK			0x2180
+MX28_PAD_SSP3_MOSI__SSP3_CMD			0x2190
+MX28_PAD_SSP3_MISO__SSP3_D0			0x21a0
+MX28_PAD_SSP3_SS0__SSP3_D3			0x21b0
+MX28_PAD_AUART0_RX__AUART0_RX			0x3000
+MX28_PAD_AUART0_TX__AUART0_TX			0x3010
+MX28_PAD_AUART0_CTS__AUART0_CTS			0x3020
+MX28_PAD_AUART0_RTS__AUART0_RTS			0x3030
+MX28_PAD_AUART1_RX__AUART1_RX			0x3040
+MX28_PAD_AUART1_TX__AUART1_TX			0x3050
+MX28_PAD_AUART1_CTS__AUART1_CTS			0x3060
+MX28_PAD_AUART1_RTS__AUART1_RTS			0x3070
+MX28_PAD_AUART2_RX__AUART2_RX			0x3080
+MX28_PAD_AUART2_TX__AUART2_TX			0x3090
+MX28_PAD_AUART2_CTS__AUART2_CTS			0x30a0
+MX28_PAD_AUART2_RTS__AUART2_RTS			0x30b0
+MX28_PAD_AUART3_RX__AUART3_RX			0x30c0
+MX28_PAD_AUART3_TX__AUART3_TX			0x30d0
+MX28_PAD_AUART3_CTS__AUART3_CTS			0x30e0
+MX28_PAD_AUART3_RTS__AUART3_RTS			0x30f0
+MX28_PAD_PWM0__PWM_0				0x3100
+MX28_PAD_PWM1__PWM_1				0x3110
+MX28_PAD_PWM2__PWM_2				0x3120
+MX28_PAD_SAIF0_MCLK__SAIF0_MCLK			0x3140
+MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK		0x3150
+MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK		0x3160
+MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0		0x3170
+MX28_PAD_I2C0_SCL__I2C0_SCL			0x3180
+MX28_PAD_I2C0_SDA__I2C0_SDA			0x3190
+MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0		0x31a0
+MX28_PAD_SPDIF__SPDIF_TX			0x31b0
+MX28_PAD_PWM3__PWM_3				0x31c0
+MX28_PAD_PWM4__PWM_4				0x31d0
+MX28_PAD_LCD_RESET__LCD_RESET			0x31e0
+MX28_PAD_ENET0_MDC__ENET0_MDC			0x4000
+MX28_PAD_ENET0_MDIO__ENET0_MDIO			0x4010
+MX28_PAD_ENET0_RX_EN__ENET0_RX_EN		0x4020
+MX28_PAD_ENET0_RXD0__ENET0_RXD0			0x4030
+MX28_PAD_ENET0_RXD1__ENET0_RXD1			0x4040
+MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK		0x4050
+MX28_PAD_ENET0_TX_EN__ENET0_TX_EN		0x4060
+MX28_PAD_ENET0_TXD0__ENET0_TXD0			0x4070
+MX28_PAD_ENET0_TXD1__ENET0_TXD1			0x4080
+MX28_PAD_ENET0_RXD2__ENET0_RXD2			0x4090
+MX28_PAD_ENET0_RXD3__ENET0_RXD3			0x40a0
+MX28_PAD_ENET0_TXD2__ENET0_TXD2			0x40b0
+MX28_PAD_ENET0_TXD3__ENET0_TXD3			0x40c0
+MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK		0x40d0
+MX28_PAD_ENET0_COL__ENET0_COL			0x40e0
+MX28_PAD_ENET0_CRS__ENET0_CRS			0x40f0
+MX28_PAD_ENET_CLK__CLKCTRL_ENET			0x4100
+MX28_PAD_JTAG_RTCK__JTAG_RTCK			0x4140
+MX28_PAD_EMI_D00__EMI_DATA0			0x5000
+MX28_PAD_EMI_D01__EMI_DATA1			0x5010
+MX28_PAD_EMI_D02__EMI_DATA2			0x5020
+MX28_PAD_EMI_D03__EMI_DATA3			0x5030
+MX28_PAD_EMI_D04__EMI_DATA4			0x5040
+MX28_PAD_EMI_D05__EMI_DATA5			0x5050
+MX28_PAD_EMI_D06__EMI_DATA6			0x5060
+MX28_PAD_EMI_D07__EMI_DATA7			0x5070
+MX28_PAD_EMI_D08__EMI_DATA8			0x5080
+MX28_PAD_EMI_D09__EMI_DATA9			0x5090
+MX28_PAD_EMI_D10__EMI_DATA10			0x50a0
+MX28_PAD_EMI_D11__EMI_DATA11			0x50b0
+MX28_PAD_EMI_D12__EMI_DATA12			0x50c0
+MX28_PAD_EMI_D13__EMI_DATA13			0x50d0
+MX28_PAD_EMI_D14__EMI_DATA14			0x50e0
+MX28_PAD_EMI_D15__EMI_DATA15			0x50f0
+MX28_PAD_EMI_ODT0__EMI_ODT0			0x5100
+MX28_PAD_EMI_DQM0__EMI_DQM0			0x5110
+MX28_PAD_EMI_ODT1__EMI_ODT1			0x5120
+MX28_PAD_EMI_DQM1__EMI_DQM1			0x5130
+MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK	0x5140
+MX28_PAD_EMI_CLK__EMI_CLK			0x5150
+MX28_PAD_EMI_DQS0__EMI_DQS0			0x5160
+MX28_PAD_EMI_DQS1__EMI_DQS1			0x5170
+MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN		0x51a0
+MX28_PAD_EMI_A00__EMI_ADDR0			0x6000
+MX28_PAD_EMI_A01__EMI_ADDR1			0x6010
+MX28_PAD_EMI_A02__EMI_ADDR2			0x6020
+MX28_PAD_EMI_A03__EMI_ADDR3			0x6030
+MX28_PAD_EMI_A04__EMI_ADDR4			0x6040
+MX28_PAD_EMI_A05__EMI_ADDR5			0x6050
+MX28_PAD_EMI_A06__EMI_ADDR6			0x6060
+MX28_PAD_EMI_A07__EMI_ADDR7			0x6070
+MX28_PAD_EMI_A08__EMI_ADDR8			0x6080
+MX28_PAD_EMI_A09__EMI_ADDR9			0x6090
+MX28_PAD_EMI_A10__EMI_ADDR10			0x60a0
+MX28_PAD_EMI_A11__EMI_ADDR11			0x60b0
+MX28_PAD_EMI_A12__EMI_ADDR12			0x60c0
+MX28_PAD_EMI_A13__EMI_ADDR13			0x60d0
+MX28_PAD_EMI_A14__EMI_ADDR14			0x60e0
+MX28_PAD_EMI_BA0__EMI_BA0			0x6100
+MX28_PAD_EMI_BA1__EMI_BA1			0x6110
+MX28_PAD_EMI_BA2__EMI_BA2			0x6120
+MX28_PAD_EMI_CASN__EMI_CASN			0x6130
+MX28_PAD_EMI_RASN__EMI_RASN			0x6140
+MX28_PAD_EMI_WEN__EMI_WEN			0x6150
+MX28_PAD_EMI_CE0N__EMI_CE0N			0x6160
+MX28_PAD_EMI_CE1N__EMI_CE1N			0x6170
+MX28_PAD_EMI_CKE__EMI_CKE			0x6180
+MX28_PAD_GPMI_D00__SSP1_D0			0x0001
+MX28_PAD_GPMI_D01__SSP1_D1			0x0011
+MX28_PAD_GPMI_D02__SSP1_D2			0x0021
+MX28_PAD_GPMI_D03__SSP1_D3			0x0031
+MX28_PAD_GPMI_D04__SSP1_D4			0x0041
+MX28_PAD_GPMI_D05__SSP1_D5			0x0051
+MX28_PAD_GPMI_D06__SSP1_D6			0x0061
+MX28_PAD_GPMI_D07__SSP1_D7			0x0071
+MX28_PAD_GPMI_CE0N__SSP3_D0			0x0101
+MX28_PAD_GPMI_CE1N__SSP3_D3			0x0111
+MX28_PAD_GPMI_CE2N__CAN1_TX			0x0121
+MX28_PAD_GPMI_CE3N__CAN1_RX			0x0131
+MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT		0x0141
+MX28_PAD_GPMI_RDY1__SSP1_CMD			0x0151
+MX28_PAD_GPMI_RDY2__CAN0_TX			0x0161
+MX28_PAD_GPMI_RDY3__CAN0_RX			0x0171
+MX28_PAD_GPMI_RDN__SSP3_SCK			0x0181
+MX28_PAD_GPMI_WRN__SSP1_SCK			0x0191
+MX28_PAD_GPMI_ALE__SSP3_D1			0x01a1
+MX28_PAD_GPMI_CLE__SSP3_D2			0x01b1
+MX28_PAD_GPMI_RESETN__SSP3_CMD			0x01c1
+MX28_PAD_LCD_D03__ETM_DA8			0x1031
+MX28_PAD_LCD_D04__ETM_DA9			0x1041
+MX28_PAD_LCD_D08__ETM_DA3			0x1081
+MX28_PAD_LCD_D09__ETM_DA4			0x1091
+MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT		0x1141
+MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN		0x1151
+MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT		0x1161
+MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN		0x1171
+MX28_PAD_LCD_RD_E__LCD_VSYNC			0x1181
+MX28_PAD_LCD_WR_RWN__LCD_HSYNC			0x1191
+MX28_PAD_LCD_RS__LCD_DOTCLK			0x11a1
+MX28_PAD_LCD_CS__LCD_ENABLE			0x11b1
+MX28_PAD_LCD_VSYNC__SAIF1_SDATA0		0x11c1
+MX28_PAD_LCD_HSYNC__SAIF1_SDATA1		0x11d1
+MX28_PAD_LCD_DOTCLK__SAIF1_MCLK			0x11e1
+MX28_PAD_SSP0_DATA4__SSP2_D0			0x2041
+MX28_PAD_SSP0_DATA5__SSP2_D3			0x2051
+MX28_PAD_SSP0_DATA6__SSP2_CMD			0x2061
+MX28_PAD_SSP0_DATA7__SSP2_SCK			0x2071
+MX28_PAD_SSP1_SCK__SSP2_D1			0x20c1
+MX28_PAD_SSP1_CMD__SSP2_D2			0x20d1
+MX28_PAD_SSP1_DATA0__SSP2_D6			0x20e1
+MX28_PAD_SSP1_DATA3__SSP2_D7			0x20f1
+MX28_PAD_SSP2_SCK__AUART2_RX			0x2101
+MX28_PAD_SSP2_MOSI__AUART2_TX			0x2111
+MX28_PAD_SSP2_MISO__AUART3_RX			0x2121
+MX28_PAD_SSP2_SS0__AUART3_TX			0x2131
+MX28_PAD_SSP2_SS1__SSP2_D1			0x2141
+MX28_PAD_SSP2_SS2__SSP2_D2			0x2151
+MX28_PAD_SSP3_SCK__AUART4_TX			0x2181
+MX28_PAD_SSP3_MOSI__AUART4_RX			0x2191
+MX28_PAD_SSP3_MISO__AUART4_RTS			0x21a1
+MX28_PAD_SSP3_SS0__AUART4_CTS			0x21b1
+MX28_PAD_AUART0_RX__I2C0_SCL			0x3001
+MX28_PAD_AUART0_TX__I2C0_SDA			0x3011
+MX28_PAD_AUART0_CTS__AUART4_RX			0x3021
+MX28_PAD_AUART0_RTS__AUART4_TX			0x3031
+MX28_PAD_AUART1_RX__SSP2_CARD_DETECT		0x3041
+MX28_PAD_AUART1_TX__SSP3_CARD_DETECT		0x3051
+MX28_PAD_AUART1_CTS__USB0_OVERCURRENT		0x3061
+MX28_PAD_AUART1_RTS__USB0_ID			0x3071
+MX28_PAD_AUART2_RX__SSP3_D1			0x3081
+MX28_PAD_AUART2_TX__SSP3_D2			0x3091
+MX28_PAD_AUART2_CTS__I2C1_SCL			0x30a1
+MX28_PAD_AUART2_RTS__I2C1_SDA			0x30b1
+MX28_PAD_AUART3_RX__CAN0_TX			0x30c1
+MX28_PAD_AUART3_TX__CAN0_RX			0x30d1
+MX28_PAD_AUART3_CTS__CAN1_TX			0x30e1
+MX28_PAD_AUART3_RTS__CAN1_RX			0x30f1
+MX28_PAD_PWM0__I2C1_SCL				0x3101
+MX28_PAD_PWM1__I2C1_SDA				0x3111
+MX28_PAD_PWM2__USB0_ID				0x3121
+MX28_PAD_SAIF0_MCLK__PWM_3			0x3141
+MX28_PAD_SAIF0_LRCLK__PWM_4			0x3151
+MX28_PAD_SAIF0_BITCLK__PWM_5			0x3161
+MX28_PAD_SAIF0_SDATA0__PWM_6			0x3171
+MX28_PAD_I2C0_SCL__TIMROT_ROTARYA		0x3181
+MX28_PAD_I2C0_SDA__TIMROT_ROTARYB		0x3191
+MX28_PAD_SAIF1_SDATA0__PWM_7			0x31a1
+MX28_PAD_LCD_RESET__LCD_VSYNC			0x31e1
+MX28_PAD_ENET0_MDC__GPMI_CE4N			0x4001
+MX28_PAD_ENET0_MDIO__GPMI_CE5N			0x4011
+MX28_PAD_ENET0_RX_EN__GPMI_CE6N			0x4021
+MX28_PAD_ENET0_RXD0__GPMI_CE7N			0x4031
+MX28_PAD_ENET0_RXD1__GPMI_READY4		0x4041
+MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER		0x4051
+MX28_PAD_ENET0_TX_EN__GPMI_READY5		0x4061
+MX28_PAD_ENET0_TXD0__GPMI_READY6		0x4071
+MX28_PAD_ENET0_TXD1__GPMI_READY7		0x4081
+MX28_PAD_ENET0_RXD2__ENET1_RXD0			0x4091
+MX28_PAD_ENET0_RXD3__ENET1_RXD1			0x40a1
+MX28_PAD_ENET0_TXD2__ENET1_TXD0			0x40b1
+MX28_PAD_ENET0_TXD3__ENET1_TXD1			0x40c1
+MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER		0x40d1
+MX28_PAD_ENET0_COL__ENET1_TX_EN			0x40e1
+MX28_PAD_ENET0_CRS__ENET1_RX_EN			0x40f1
+MX28_PAD_GPMI_CE2N__ENET0_RX_ER			0x0122
+MX28_PAD_GPMI_CE3N__SAIF1_MCLK			0x0132
+MX28_PAD_GPMI_RDY0__USB0_ID			0x0142
+MX28_PAD_GPMI_RDY2__ENET0_TX_ER			0x0162
+MX28_PAD_GPMI_RDY3__HSADC_TRIGGER		0x0172
+MX28_PAD_GPMI_ALE__SSP3_D4			0x01a2
+MX28_PAD_GPMI_CLE__SSP3_D5			0x01b2
+MX28_PAD_LCD_D00__ETM_DA0			0x1002
+MX28_PAD_LCD_D01__ETM_DA1			0x1012
+MX28_PAD_LCD_D02__ETM_DA2			0x1022
+MX28_PAD_LCD_D03__ETM_DA3			0x1032
+MX28_PAD_LCD_D04__ETM_DA4			0x1042
+MX28_PAD_LCD_D05__ETM_DA5			0x1052
+MX28_PAD_LCD_D06__ETM_DA6			0x1062
+MX28_PAD_LCD_D07__ETM_DA7			0x1072
+MX28_PAD_LCD_D08__ETM_DA8			0x1082
+MX28_PAD_LCD_D09__ETM_DA9			0x1092
+MX28_PAD_LCD_D10__ETM_DA10			0x10a2
+MX28_PAD_LCD_D11__ETM_DA11			0x10b2
+MX28_PAD_LCD_D12__ETM_DA12			0x10c2
+MX28_PAD_LCD_D13__ETM_DA13			0x10d2
+MX28_PAD_LCD_D14__ETM_DA14			0x10e2
+MX28_PAD_LCD_D15__ETM_DA15			0x10f2
+MX28_PAD_LCD_D16__ETM_DA7			0x1102
+MX28_PAD_LCD_D17__ETM_DA6			0x1112
+MX28_PAD_LCD_D18__ETM_DA5			0x1122
+MX28_PAD_LCD_D19__ETM_DA4			0x1132
+MX28_PAD_LCD_D20__ETM_DA3			0x1142
+MX28_PAD_LCD_D21__ETM_DA2			0x1152
+MX28_PAD_LCD_D22__ETM_DA1			0x1162
+MX28_PAD_LCD_D23__ETM_DA0			0x1172
+MX28_PAD_LCD_RD_E__ETM_TCTL			0x1182
+MX28_PAD_LCD_WR_RWN__ETM_TCLK			0x1192
+MX28_PAD_LCD_HSYNC__ETM_TCTL			0x11d2
+MX28_PAD_LCD_DOTCLK__ETM_TCLK			0x11e2
+MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT	0x20c2
+MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN		0x20d2
+MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT	0x20e2
+MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN	0x20f2
+MX28_PAD_SSP2_SCK__SAIF0_SDATA1			0x2102
+MX28_PAD_SSP2_MOSI__SAIF0_SDATA2		0x2112
+MX28_PAD_SSP2_MISO__SAIF1_SDATA1		0x2122
+MX28_PAD_SSP2_SS0__SAIF1_SDATA2			0x2132
+MX28_PAD_SSP2_SS1__USB1_OVERCURRENT		0x2142
+MX28_PAD_SSP2_SS2__USB0_OVERCURRENT		0x2152
+MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT	0x2182
+MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN	0x2192
+MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT	0x21a2
+MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN		0x21b2
+MX28_PAD_AUART0_RX__DUART_CTS			0x3002
+MX28_PAD_AUART0_TX__DUART_RTS			0x3012
+MX28_PAD_AUART0_CTS__DUART_RX			0x3022
+MX28_PAD_AUART0_RTS__DUART_TX			0x3032
+MX28_PAD_AUART1_RX__PWM_0			0x3042
+MX28_PAD_AUART1_TX__PWM_1			0x3052
+MX28_PAD_AUART1_CTS__TIMROT_ROTARYA		0x3062
+MX28_PAD_AUART1_RTS__TIMROT_ROTARYB		0x3072
+MX28_PAD_AUART2_RX__SSP3_D4			0x3082
+MX28_PAD_AUART2_TX__SSP3_D5			0x3092
+MX28_PAD_AUART2_CTS__SAIF1_BITCLK		0x30a2
+MX28_PAD_AUART2_RTS__SAIF1_LRCLK		0x30b2
+MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT	0x30c2
+MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN	0x30d2
+MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT	0x30e2
+MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN	0x30f2
+MX28_PAD_PWM0__DUART_RX				0x3102
+MX28_PAD_PWM1__DUART_TX				0x3112
+MX28_PAD_PWM2__USB1_OVERCURRENT			0x3122
+MX28_PAD_SAIF0_MCLK__AUART4_CTS			0x3142
+MX28_PAD_SAIF0_LRCLK__AUART4_RTS		0x3152
+MX28_PAD_SAIF0_BITCLK__AUART4_RX		0x3162
+MX28_PAD_SAIF0_SDATA0__AUART4_TX		0x3172
+MX28_PAD_I2C0_SCL__DUART_RX			0x3182
+MX28_PAD_I2C0_SDA__DUART_TX			0x3192
+MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1		0x31a2
+MX28_PAD_SPDIF__ENET1_RX_ER			0x31b2
+MX28_PAD_ENET0_MDC__SAIF0_SDATA1		0x4002
+MX28_PAD_ENET0_MDIO__SAIF0_SDATA2		0x4012
+MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1		0x4022
+MX28_PAD_ENET0_RXD0__SAIF1_SDATA2		0x4032
+MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT	0x4052
+MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT	0x4092
+MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN	0x40a2
+MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT	0x40b2
+MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN	0x40c2
+MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN	0x40d2
+MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT	0x40e2
+MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN	0x40f2
+MX28_PAD_GPMI_D00__GPIO_0_0			0x0003
+MX28_PAD_GPMI_D01__GPIO_0_1			0x0013
+MX28_PAD_GPMI_D02__GPIO_0_2			0x0023
+MX28_PAD_GPMI_D03__GPIO_0_3			0x0033
+MX28_PAD_GPMI_D04__GPIO_0_4			0x0043
+MX28_PAD_GPMI_D05__GPIO_0_5			0x0053
+MX28_PAD_GPMI_D06__GPIO_0_6			0x0063
+MX28_PAD_GPMI_D07__GPIO_0_7			0x0073
+MX28_PAD_GPMI_CE0N__GPIO_0_16			0x0103
+MX28_PAD_GPMI_CE1N__GPIO_0_17			0x0113
+MX28_PAD_GPMI_CE2N__GPIO_0_18			0x0123
+MX28_PAD_GPMI_CE3N__GPIO_0_19			0x0133
+MX28_PAD_GPMI_RDY0__GPIO_0_20			0x0143
+MX28_PAD_GPMI_RDY1__GPIO_0_21			0x0153
+MX28_PAD_GPMI_RDY2__GPIO_0_22			0x0163
+MX28_PAD_GPMI_RDY3__GPIO_0_23			0x0173
+MX28_PAD_GPMI_RDN__GPIO_0_24			0x0183
+MX28_PAD_GPMI_WRN__GPIO_0_25			0x0193
+MX28_PAD_GPMI_ALE__GPIO_0_26			0x01a3
+MX28_PAD_GPMI_CLE__GPIO_0_27			0x01b3
+MX28_PAD_GPMI_RESETN__GPIO_0_28			0x01c3
+MX28_PAD_LCD_D00__GPIO_1_0			0x1003
+MX28_PAD_LCD_D01__GPIO_1_1			0x1013
+MX28_PAD_LCD_D02__GPIO_1_2			0x1023
+MX28_PAD_LCD_D03__GPIO_1_3			0x1033
+MX28_PAD_LCD_D04__GPIO_1_4			0x1043
+MX28_PAD_LCD_D05__GPIO_1_5			0x1053
+MX28_PAD_LCD_D06__GPIO_1_6			0x1063
+MX28_PAD_LCD_D07__GPIO_1_7			0x1073
+MX28_PAD_LCD_D08__GPIO_1_8			0x1083
+MX28_PAD_LCD_D09__GPIO_1_9			0x1093
+MX28_PAD_LCD_D10__GPIO_1_10			0x10a3
+MX28_PAD_LCD_D11__GPIO_1_11			0x10b3
+MX28_PAD_LCD_D12__GPIO_1_12			0x10c3
+MX28_PAD_LCD_D13__GPIO_1_13			0x10d3
+MX28_PAD_LCD_D14__GPIO_1_14			0x10e3
+MX28_PAD_LCD_D15__GPIO_1_15			0x10f3
+MX28_PAD_LCD_D16__GPIO_1_16			0x1103
+MX28_PAD_LCD_D17__GPIO_1_17			0x1113
+MX28_PAD_LCD_D18__GPIO_1_18			0x1123
+MX28_PAD_LCD_D19__GPIO_1_19			0x1133
+MX28_PAD_LCD_D20__GPIO_1_20			0x1143
+MX28_PAD_LCD_D21__GPIO_1_21			0x1153
+MX28_PAD_LCD_D22__GPIO_1_22			0x1163
+MX28_PAD_LCD_D23__GPIO_1_23			0x1173
+MX28_PAD_LCD_RD_E__GPIO_1_24			0x1183
+MX28_PAD_LCD_WR_RWN__GPIO_1_25			0x1193
+MX28_PAD_LCD_RS__GPIO_1_26			0x11a3
+MX28_PAD_LCD_CS__GPIO_1_27			0x11b3
+MX28_PAD_LCD_VSYNC__GPIO_1_28			0x11c3
+MX28_PAD_LCD_HSYNC__GPIO_1_29			0x11d3
+MX28_PAD_LCD_DOTCLK__GPIO_1_30			0x11e3
+MX28_PAD_LCD_ENABLE__GPIO_1_31			0x11f3
+MX28_PAD_SSP0_DATA0__GPIO_2_0			0x2003
+MX28_PAD_SSP0_DATA1__GPIO_2_1			0x2013
+MX28_PAD_SSP0_DATA2__GPIO_2_2			0x2023
+MX28_PAD_SSP0_DATA3__GPIO_2_3			0x2033
+MX28_PAD_SSP0_DATA4__GPIO_2_4			0x2043
+MX28_PAD_SSP0_DATA5__GPIO_2_5			0x2053
+MX28_PAD_SSP0_DATA6__GPIO_2_6			0x2063
+MX28_PAD_SSP0_DATA7__GPIO_2_7			0x2073
+MX28_PAD_SSP0_CMD__GPIO_2_8			0x2083
+MX28_PAD_SSP0_DETECT__GPIO_2_9			0x2093
+MX28_PAD_SSP0_SCK__GPIO_2_10			0x20a3
+MX28_PAD_SSP1_SCK__GPIO_2_12			0x20c3
+MX28_PAD_SSP1_CMD__GPIO_2_13			0x20d3
+MX28_PAD_SSP1_DATA0__GPIO_2_14			0x20e3
+MX28_PAD_SSP1_DATA3__GPIO_2_15			0x20f3
+MX28_PAD_SSP2_SCK__GPIO_2_16			0x2103
+MX28_PAD_SSP2_MOSI__GPIO_2_17			0x2113
+MX28_PAD_SSP2_MISO__GPIO_2_18			0x2123
+MX28_PAD_SSP2_SS0__GPIO_2_19			0x2133
+MX28_PAD_SSP2_SS1__GPIO_2_20			0x2143
+MX28_PAD_SSP2_SS2__GPIO_2_21			0x2153
+MX28_PAD_SSP3_SCK__GPIO_2_24			0x2183
+MX28_PAD_SSP3_MOSI__GPIO_2_25			0x2193
+MX28_PAD_SSP3_MISO__GPIO_2_26			0x21a3
+MX28_PAD_SSP3_SS0__GPIO_2_27			0x21b3
+MX28_PAD_AUART0_RX__GPIO_3_0			0x3003
+MX28_PAD_AUART0_TX__GPIO_3_1			0x3013
+MX28_PAD_AUART0_CTS__GPIO_3_2			0x3023
+MX28_PAD_AUART0_RTS__GPIO_3_3			0x3033
+MX28_PAD_AUART1_RX__GPIO_3_4			0x3043
+MX28_PAD_AUART1_TX__GPIO_3_5			0x3053
+MX28_PAD_AUART1_CTS__GPIO_3_6			0x3063
+MX28_PAD_AUART1_RTS__GPIO_3_7			0x3073
+MX28_PAD_AUART2_RX__GPIO_3_8			0x3083
+MX28_PAD_AUART2_TX__GPIO_3_9			0x3093
+MX28_PAD_AUART2_CTS__GPIO_3_10			0x30a3
+MX28_PAD_AUART2_RTS__GPIO_3_11			0x30b3
+MX28_PAD_AUART3_RX__GPIO_3_12			0x30c3
+MX28_PAD_AUART3_TX__GPIO_3_13			0x30d3
+MX28_PAD_AUART3_CTS__GPIO_3_14			0x30e3
+MX28_PAD_AUART3_RTS__GPIO_3_15			0x30f3
+MX28_PAD_PWM0__GPIO_3_16			0x3103
+MX28_PAD_PWM1__GPIO_3_17			0x3113
+MX28_PAD_PWM2__GPIO_3_18			0x3123
+MX28_PAD_SAIF0_MCLK__GPIO_3_20			0x3143
+MX28_PAD_SAIF0_LRCLK__GPIO_3_21			0x3153
+MX28_PAD_SAIF0_BITCLK__GPIO_3_22		0x3163
+MX28_PAD_SAIF0_SDATA0__GPIO_3_23		0x3173
+MX28_PAD_I2C0_SCL__GPIO_3_24			0x3183
+MX28_PAD_I2C0_SDA__GPIO_3_25			0x3193
+MX28_PAD_SAIF1_SDATA0__GPIO_3_26		0x31a3
+MX28_PAD_SPDIF__GPIO_3_27			0x31b3
+MX28_PAD_PWM3__GPIO_3_28			0x31c3
+MX28_PAD_PWM4__GPIO_3_29			0x31d3
+MX28_PAD_LCD_RESET__GPIO_3_30			0x31e3
+MX28_PAD_ENET0_MDC__GPIO_4_0			0x4003
+MX28_PAD_ENET0_MDIO__GPIO_4_1			0x4013
+MX28_PAD_ENET0_RX_EN__GPIO_4_2			0x4023
+MX28_PAD_ENET0_RXD0__GPIO_4_3			0x4033
+MX28_PAD_ENET0_RXD1__GPIO_4_4			0x4043
+MX28_PAD_ENET0_TX_CLK__GPIO_4_5			0x4053
+MX28_PAD_ENET0_TX_EN__GPIO_4_6			0x4063
+MX28_PAD_ENET0_TXD0__GPIO_4_7			0x4073
+MX28_PAD_ENET0_TXD1__GPIO_4_8			0x4083
+MX28_PAD_ENET0_RXD2__GPIO_4_9			0x4093
+MX28_PAD_ENET0_RXD3__GPIO_4_10			0x40a3
+MX28_PAD_ENET0_TXD2__GPIO_4_11			0x40b3
+MX28_PAD_ENET0_TXD3__GPIO_4_12			0x40c3
+MX28_PAD_ENET0_RX_CLK__GPIO_4_13		0x40d3
+MX28_PAD_ENET0_COL__GPIO_4_14			0x40e3
+MX28_PAD_ENET0_CRS__GPIO_4_15			0x40f3
+MX28_PAD_ENET_CLK__GPIO_4_16			0x4103
+MX28_PAD_JTAG_RTCK__GPIO_4_20			0x4143
+
+Valid values for i.MX23 pinmux-id:
+
+pinmux						id
+------						--
+MX23_PAD_GPMI_D00__GPMI_D00			0x0000
+MX23_PAD_GPMI_D01__GPMI_D01			0x0010
+MX23_PAD_GPMI_D02__GPMI_D02			0x0020
+MX23_PAD_GPMI_D03__GPMI_D03			0x0030
+MX23_PAD_GPMI_D04__GPMI_D04			0x0040
+MX23_PAD_GPMI_D05__GPMI_D05			0x0050
+MX23_PAD_GPMI_D06__GPMI_D06			0x0060
+MX23_PAD_GPMI_D07__GPMI_D07			0x0070
+MX23_PAD_GPMI_D08__GPMI_D08			0x0080
+MX23_PAD_GPMI_D09__GPMI_D09			0x0090
+MX23_PAD_GPMI_D10__GPMI_D10			0x00a0
+MX23_PAD_GPMI_D11__GPMI_D11			0x00b0
+MX23_PAD_GPMI_D12__GPMI_D12			0x00c0
+MX23_PAD_GPMI_D13__GPMI_D13			0x00d0
+MX23_PAD_GPMI_D14__GPMI_D14			0x00e0
+MX23_PAD_GPMI_D15__GPMI_D15			0x00f0
+MX23_PAD_GPMI_CLE__GPMI_CLE			0x0100
+MX23_PAD_GPMI_ALE__GPMI_ALE			0x0110
+MX23_PAD_GPMI_CE2N__GPMI_CE2N			0x0120
+MX23_PAD_GPMI_RDY0__GPMI_RDY0			0x0130
+MX23_PAD_GPMI_RDY1__GPMI_RDY1			0x0140
+MX23_PAD_GPMI_RDY2__GPMI_RDY2			0x0150
+MX23_PAD_GPMI_RDY3__GPMI_RDY3			0x0160
+MX23_PAD_GPMI_WPN__GPMI_WPN			0x0170
+MX23_PAD_GPMI_WRN__GPMI_WRN			0x0180
+MX23_PAD_GPMI_RDN__GPMI_RDN			0x0190
+MX23_PAD_AUART1_CTS__AUART1_CTS			0x01a0
+MX23_PAD_AUART1_RTS__AUART1_RTS			0x01b0
+MX23_PAD_AUART1_RX__AUART1_RX			0x01c0
+MX23_PAD_AUART1_TX__AUART1_TX			0x01d0
+MX23_PAD_I2C_SCL__I2C_SCL			0x01e0
+MX23_PAD_I2C_SDA__I2C_SDA			0x01f0
+MX23_PAD_LCD_D00__LCD_D00			0x1000
+MX23_PAD_LCD_D01__LCD_D01			0x1010
+MX23_PAD_LCD_D02__LCD_D02			0x1020
+MX23_PAD_LCD_D03__LCD_D03			0x1030
+MX23_PAD_LCD_D04__LCD_D04			0x1040
+MX23_PAD_LCD_D05__LCD_D05			0x1050
+MX23_PAD_LCD_D06__LCD_D06			0x1060
+MX23_PAD_LCD_D07__LCD_D07			0x1070
+MX23_PAD_LCD_D08__LCD_D08			0x1080
+MX23_PAD_LCD_D09__LCD_D09			0x1090
+MX23_PAD_LCD_D10__LCD_D10			0x10a0
+MX23_PAD_LCD_D11__LCD_D11			0x10b0
+MX23_PAD_LCD_D12__LCD_D12			0x10c0
+MX23_PAD_LCD_D13__LCD_D13			0x10d0
+MX23_PAD_LCD_D14__LCD_D14			0x10e0
+MX23_PAD_LCD_D15__LCD_D15			0x10f0
+MX23_PAD_LCD_D16__LCD_D16			0x1100
+MX23_PAD_LCD_D17__LCD_D17			0x1110
+MX23_PAD_LCD_RESET__LCD_RESET			0x1120
+MX23_PAD_LCD_RS__LCD_RS				0x1130
+MX23_PAD_LCD_WR__LCD_WR				0x1140
+MX23_PAD_LCD_CS__LCD_CS				0x1150
+MX23_PAD_LCD_DOTCK__LCD_DOTCK			0x1160
+MX23_PAD_LCD_ENABLE__LCD_ENABLE			0x1170
+MX23_PAD_LCD_HSYNC__LCD_HSYNC			0x1180
+MX23_PAD_LCD_VSYNC__LCD_VSYNC			0x1190
+MX23_PAD_PWM0__PWM0				0x11a0
+MX23_PAD_PWM1__PWM1				0x11b0
+MX23_PAD_PWM2__PWM2				0x11c0
+MX23_PAD_PWM3__PWM3				0x11d0
+MX23_PAD_PWM4__PWM4				0x11e0
+MX23_PAD_SSP1_CMD__SSP1_CMD			0x2000
+MX23_PAD_SSP1_DETECT__SSP1_DETECT		0x2010
+MX23_PAD_SSP1_DATA0__SSP1_DATA0			0x2020
+MX23_PAD_SSP1_DATA1__SSP1_DATA1			0x2030
+MX23_PAD_SSP1_DATA2__SSP1_DATA2			0x2040
+MX23_PAD_SSP1_DATA3__SSP1_DATA3			0x2050
+MX23_PAD_SSP1_SCK__SSP1_SCK			0x2060
+MX23_PAD_ROTARYA__ROTARYA			0x2070
+MX23_PAD_ROTARYB__ROTARYB			0x2080
+MX23_PAD_EMI_A00__EMI_A00			0x2090
+MX23_PAD_EMI_A01__EMI_A01			0x20a0
+MX23_PAD_EMI_A02__EMI_A02			0x20b0
+MX23_PAD_EMI_A03__EMI_A03			0x20c0
+MX23_PAD_EMI_A04__EMI_A04			0x20d0
+MX23_PAD_EMI_A05__EMI_A05			0x20e0
+MX23_PAD_EMI_A06__EMI_A06			0x20f0
+MX23_PAD_EMI_A07__EMI_A07			0x2100
+MX23_PAD_EMI_A08__EMI_A08			0x2110
+MX23_PAD_EMI_A09__EMI_A09			0x2120
+MX23_PAD_EMI_A10__EMI_A10			0x2130
+MX23_PAD_EMI_A11__EMI_A11			0x2140
+MX23_PAD_EMI_A12__EMI_A12			0x2150
+MX23_PAD_EMI_BA0__EMI_BA0			0x2160
+MX23_PAD_EMI_BA1__EMI_BA1			0x2170
+MX23_PAD_EMI_CASN__EMI_CASN			0x2180
+MX23_PAD_EMI_CE0N__EMI_CE0N			0x2190
+MX23_PAD_EMI_CE1N__EMI_CE1N			0x21a0
+MX23_PAD_GPMI_CE1N__GPMI_CE1N			0x21b0
+MX23_PAD_GPMI_CE0N__GPMI_CE0N			0x21c0
+MX23_PAD_EMI_CKE__EMI_CKE			0x21d0
+MX23_PAD_EMI_RASN__EMI_RASN			0x21e0
+MX23_PAD_EMI_WEN__EMI_WEN			0x21f0
+MX23_PAD_EMI_D00__EMI_D00			0x3000
+MX23_PAD_EMI_D01__EMI_D01			0x3010
+MX23_PAD_EMI_D02__EMI_D02			0x3020
+MX23_PAD_EMI_D03__EMI_D03			0x3030
+MX23_PAD_EMI_D04__EMI_D04			0x3040
+MX23_PAD_EMI_D05__EMI_D05			0x3050
+MX23_PAD_EMI_D06__EMI_D06			0x3060
+MX23_PAD_EMI_D07__EMI_D07			0x3070
+MX23_PAD_EMI_D08__EMI_D08			0x3080
+MX23_PAD_EMI_D09__EMI_D09			0x3090
+MX23_PAD_EMI_D10__EMI_D10			0x30a0
+MX23_PAD_EMI_D11__EMI_D11			0x30b0
+MX23_PAD_EMI_D12__EMI_D12			0x30c0
+MX23_PAD_EMI_D13__EMI_D13			0x30d0
+MX23_PAD_EMI_D14__EMI_D14			0x30e0
+MX23_PAD_EMI_D15__EMI_D15			0x30f0
+MX23_PAD_EMI_DQM0__EMI_DQM0			0x3100
+MX23_PAD_EMI_DQM1__EMI_DQM1			0x3110
+MX23_PAD_EMI_DQS0__EMI_DQS0			0x3120
+MX23_PAD_EMI_DQS1__EMI_DQS1			0x3130
+MX23_PAD_EMI_CLK__EMI_CLK			0x3140
+MX23_PAD_EMI_CLKN__EMI_CLKN			0x3150
+MX23_PAD_GPMI_D00__LCD_D8			0x0001
+MX23_PAD_GPMI_D01__LCD_D9			0x0011
+MX23_PAD_GPMI_D02__LCD_D10			0x0021
+MX23_PAD_GPMI_D03__LCD_D11			0x0031
+MX23_PAD_GPMI_D04__LCD_D12			0x0041
+MX23_PAD_GPMI_D05__LCD_D13			0x0051
+MX23_PAD_GPMI_D06__LCD_D14			0x0061
+MX23_PAD_GPMI_D07__LCD_D15			0x0071
+MX23_PAD_GPMI_D08__LCD_D18			0x0081
+MX23_PAD_GPMI_D09__LCD_D19			0x0091
+MX23_PAD_GPMI_D10__LCD_D20			0x00a1
+MX23_PAD_GPMI_D11__LCD_D21			0x00b1
+MX23_PAD_GPMI_D12__LCD_D22			0x00c1
+MX23_PAD_GPMI_D13__LCD_D23			0x00d1
+MX23_PAD_GPMI_D14__AUART2_RX			0x00e1
+MX23_PAD_GPMI_D15__AUART2_TX			0x00f1
+MX23_PAD_GPMI_CLE__LCD_D16			0x0101
+MX23_PAD_GPMI_ALE__LCD_D17			0x0111
+MX23_PAD_GPMI_CE2N__ATA_A2			0x0121
+MX23_PAD_AUART1_RTS__IR_CLK			0x01b1
+MX23_PAD_AUART1_RX__IR_RX			0x01c1
+MX23_PAD_AUART1_TX__IR_TX			0x01d1
+MX23_PAD_I2C_SCL__GPMI_RDY2			0x01e1
+MX23_PAD_I2C_SDA__GPMI_CE2N			0x01f1
+MX23_PAD_LCD_D00__ETM_DA8			0x1001
+MX23_PAD_LCD_D01__ETM_DA9			0x1011
+MX23_PAD_LCD_D02__ETM_DA10			0x1021
+MX23_PAD_LCD_D03__ETM_DA11			0x1031
+MX23_PAD_LCD_D04__ETM_DA12			0x1041
+MX23_PAD_LCD_D05__ETM_DA13			0x1051
+MX23_PAD_LCD_D06__ETM_DA14			0x1061
+MX23_PAD_LCD_D07__ETM_DA15			0x1071
+MX23_PAD_LCD_D08__ETM_DA0			0x1081
+MX23_PAD_LCD_D09__ETM_DA1			0x1091
+MX23_PAD_LCD_D10__ETM_DA2			0x10a1
+MX23_PAD_LCD_D11__ETM_DA3			0x10b1
+MX23_PAD_LCD_D12__ETM_DA4			0x10c1
+MX23_PAD_LCD_D13__ETM_DA5			0x10d1
+MX23_PAD_LCD_D14__ETM_DA6			0x10e1
+MX23_PAD_LCD_D15__ETM_DA7			0x10f1
+MX23_PAD_LCD_RESET__ETM_TCTL			0x1121
+MX23_PAD_LCD_RS__ETM_TCLK			0x1131
+MX23_PAD_LCD_DOTCK__GPMI_RDY3			0x1161
+MX23_PAD_LCD_ENABLE__I2C_SCL			0x1171
+MX23_PAD_LCD_HSYNC__I2C_SDA			0x1181
+MX23_PAD_LCD_VSYNC__LCD_BUSY			0x1191
+MX23_PAD_PWM0__ROTARYA				0x11a1
+MX23_PAD_PWM1__ROTARYB				0x11b1
+MX23_PAD_PWM2__GPMI_RDY3			0x11c1
+MX23_PAD_PWM3__ETM_TCTL				0x11d1
+MX23_PAD_PWM4__ETM_TCLK				0x11e1
+MX23_PAD_SSP1_DETECT__GPMI_CE3N			0x2011
+MX23_PAD_SSP1_DATA1__I2C_SCL			0x2031
+MX23_PAD_SSP1_DATA2__I2C_SDA			0x2041
+MX23_PAD_ROTARYA__AUART2_RTS			0x2071
+MX23_PAD_ROTARYB__AUART2_CTS			0x2081
+MX23_PAD_GPMI_D00__SSP2_DATA0			0x0002
+MX23_PAD_GPMI_D01__SSP2_DATA1			0x0012
+MX23_PAD_GPMI_D02__SSP2_DATA2			0x0022
+MX23_PAD_GPMI_D03__SSP2_DATA3			0x0032
+MX23_PAD_GPMI_D04__SSP2_DATA4			0x0042
+MX23_PAD_GPMI_D05__SSP2_DATA5			0x0052
+MX23_PAD_GPMI_D06__SSP2_DATA6			0x0062
+MX23_PAD_GPMI_D07__SSP2_DATA7			0x0072
+MX23_PAD_GPMI_D08__SSP1_DATA4			0x0082
+MX23_PAD_GPMI_D09__SSP1_DATA5			0x0092
+MX23_PAD_GPMI_D10__SSP1_DATA6			0x00a2
+MX23_PAD_GPMI_D11__SSP1_DATA7			0x00b2
+MX23_PAD_GPMI_D15__GPMI_CE3N			0x00f2
+MX23_PAD_GPMI_RDY0__SSP2_DETECT			0x0132
+MX23_PAD_GPMI_RDY1__SSP2_CMD			0x0142
+MX23_PAD_GPMI_WRN__SSP2_SCK			0x0182
+MX23_PAD_AUART1_CTS__SSP1_DATA4			0x01a2
+MX23_PAD_AUART1_RTS__SSP1_DATA5			0x01b2
+MX23_PAD_AUART1_RX__SSP1_DATA6			0x01c2
+MX23_PAD_AUART1_TX__SSP1_DATA7			0x01d2
+MX23_PAD_I2C_SCL__AUART1_TX			0x01e2
+MX23_PAD_I2C_SDA__AUART1_RX			0x01f2
+MX23_PAD_LCD_D08__SAIF2_SDATA0			0x1082
+MX23_PAD_LCD_D09__SAIF1_SDATA0			0x1092
+MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK		0x10a2
+MX23_PAD_LCD_D11__SAIF_LRCLK			0x10b2
+MX23_PAD_LCD_D12__SAIF2_SDATA1			0x10c2
+MX23_PAD_LCD_D13__SAIF2_SDATA2			0x10d2
+MX23_PAD_LCD_D14__SAIF1_SDATA2			0x10e2
+MX23_PAD_LCD_D15__SAIF1_SDATA1			0x10f2
+MX23_PAD_LCD_D16__SAIF_ALT_BITCLK		0x1102
+MX23_PAD_LCD_RESET__GPMI_CE3N			0x1122
+MX23_PAD_PWM0__DUART_RX				0x11a2
+MX23_PAD_PWM1__DUART_TX				0x11b2
+MX23_PAD_PWM3__AUART1_CTS			0x11d2
+MX23_PAD_PWM4__AUART1_RTS			0x11e2
+MX23_PAD_SSP1_CMD__JTAG_TDO			0x2002
+MX23_PAD_SSP1_DETECT__USB_OTG_ID		0x2012
+MX23_PAD_SSP1_DATA0__JTAG_TDI			0x2022
+MX23_PAD_SSP1_DATA1__JTAG_TCLK			0x2032
+MX23_PAD_SSP1_DATA2__JTAG_RTCK			0x2042
+MX23_PAD_SSP1_DATA3__JTAG_TMS			0x2052
+MX23_PAD_SSP1_SCK__JTAG_TRST			0x2062
+MX23_PAD_ROTARYA__SPDIF				0x2072
+MX23_PAD_ROTARYB__GPMI_CE3N			0x2082
+MX23_PAD_GPMI_D00__GPIO_0_0			0x0003
+MX23_PAD_GPMI_D01__GPIO_0_1			0x0013
+MX23_PAD_GPMI_D02__GPIO_0_2			0x0023
+MX23_PAD_GPMI_D03__GPIO_0_3			0x0033
+MX23_PAD_GPMI_D04__GPIO_0_4			0x0043
+MX23_PAD_GPMI_D05__GPIO_0_5			0x0053
+MX23_PAD_GPMI_D06__GPIO_0_6			0x0063
+MX23_PAD_GPMI_D07__GPIO_0_7			0x0073
+MX23_PAD_GPMI_D08__GPIO_0_8			0x0083
+MX23_PAD_GPMI_D09__GPIO_0_9			0x0093
+MX23_PAD_GPMI_D10__GPIO_0_10			0x00a3
+MX23_PAD_GPMI_D11__GPIO_0_11			0x00b3
+MX23_PAD_GPMI_D12__GPIO_0_12			0x00c3
+MX23_PAD_GPMI_D13__GPIO_0_13			0x00d3
+MX23_PAD_GPMI_D14__GPIO_0_14			0x00e3
+MX23_PAD_GPMI_D15__GPIO_0_15			0x00f3
+MX23_PAD_GPMI_CLE__GPIO_0_16			0x0103
+MX23_PAD_GPMI_ALE__GPIO_0_17			0x0113
+MX23_PAD_GPMI_CE2N__GPIO_0_18			0x0123
+MX23_PAD_GPMI_RDY0__GPIO_0_19			0x0133
+MX23_PAD_GPMI_RDY1__GPIO_0_20			0x0143
+MX23_PAD_GPMI_RDY2__GPIO_0_21			0x0153
+MX23_PAD_GPMI_RDY3__GPIO_0_22			0x0163
+MX23_PAD_GPMI_WPN__GPIO_0_23			0x0173
+MX23_PAD_GPMI_WRN__GPIO_0_24			0x0183
+MX23_PAD_GPMI_RDN__GPIO_0_25			0x0193
+MX23_PAD_AUART1_CTS__GPIO_0_26			0x01a3
+MX23_PAD_AUART1_RTS__GPIO_0_27			0x01b3
+MX23_PAD_AUART1_RX__GPIO_0_28			0x01c3
+MX23_PAD_AUART1_TX__GPIO_0_29			0x01d3
+MX23_PAD_I2C_SCL__GPIO_0_30			0x01e3
+MX23_PAD_I2C_SDA__GPIO_0_31			0x01f3
+MX23_PAD_LCD_D00__GPIO_1_0			0x1003
+MX23_PAD_LCD_D01__GPIO_1_1			0x1013
+MX23_PAD_LCD_D02__GPIO_1_2			0x1023
+MX23_PAD_LCD_D03__GPIO_1_3			0x1033
+MX23_PAD_LCD_D04__GPIO_1_4			0x1043
+MX23_PAD_LCD_D05__GPIO_1_5			0x1053
+MX23_PAD_LCD_D06__GPIO_1_6			0x1063
+MX23_PAD_LCD_D07__GPIO_1_7			0x1073
+MX23_PAD_LCD_D08__GPIO_1_8			0x1083
+MX23_PAD_LCD_D09__GPIO_1_9			0x1093
+MX23_PAD_LCD_D10__GPIO_1_10			0x10a3
+MX23_PAD_LCD_D11__GPIO_1_11			0x10b3
+MX23_PAD_LCD_D12__GPIO_1_12			0x10c3
+MX23_PAD_LCD_D13__GPIO_1_13			0x10d3
+MX23_PAD_LCD_D14__GPIO_1_14			0x10e3
+MX23_PAD_LCD_D15__GPIO_1_15			0x10f3
+MX23_PAD_LCD_D16__GPIO_1_16			0x1103
+MX23_PAD_LCD_D17__GPIO_1_17			0x1113
+MX23_PAD_LCD_RESET__GPIO_1_18			0x1123
+MX23_PAD_LCD_RS__GPIO_1_19			0x1133
+MX23_PAD_LCD_WR__GPIO_1_20			0x1143
+MX23_PAD_LCD_CS__GPIO_1_21			0x1153
+MX23_PAD_LCD_DOTCK__GPIO_1_22			0x1163
+MX23_PAD_LCD_ENABLE__GPIO_1_23			0x1173
+MX23_PAD_LCD_HSYNC__GPIO_1_24			0x1183
+MX23_PAD_LCD_VSYNC__GPIO_1_25			0x1193
+MX23_PAD_PWM0__GPIO_1_26			0x11a3
+MX23_PAD_PWM1__GPIO_1_27			0x11b3
+MX23_PAD_PWM2__GPIO_1_28			0x11c3
+MX23_PAD_PWM3__GPIO_1_29			0x11d3
+MX23_PAD_PWM4__GPIO_1_30			0x11e3
+MX23_PAD_SSP1_CMD__GPIO_2_0			0x2003
+MX23_PAD_SSP1_DETECT__GPIO_2_1			0x2013
+MX23_PAD_SSP1_DATA0__GPIO_2_2			0x2023
+MX23_PAD_SSP1_DATA1__GPIO_2_3			0x2033
+MX23_PAD_SSP1_DATA2__GPIO_2_4			0x2043
+MX23_PAD_SSP1_DATA3__GPIO_2_5			0x2053
+MX23_PAD_SSP1_SCK__GPIO_2_6			0x2063
+MX23_PAD_ROTARYA__GPIO_2_7			0x2073
+MX23_PAD_ROTARYB__GPIO_2_8			0x2083
+MX23_PAD_EMI_A00__GPIO_2_9			0x2093
+MX23_PAD_EMI_A01__GPIO_2_10			0x20a3
+MX23_PAD_EMI_A02__GPIO_2_11			0x20b3
+MX23_PAD_EMI_A03__GPIO_2_12			0x20c3
+MX23_PAD_EMI_A04__GPIO_2_13			0x20d3
+MX23_PAD_EMI_A05__GPIO_2_14			0x20e3
+MX23_PAD_EMI_A06__GPIO_2_15			0x20f3
+MX23_PAD_EMI_A07__GPIO_2_16			0x2103
+MX23_PAD_EMI_A08__GPIO_2_17			0x2113
+MX23_PAD_EMI_A09__GPIO_2_18			0x2123
+MX23_PAD_EMI_A10__GPIO_2_19			0x2133
+MX23_PAD_EMI_A11__GPIO_2_20			0x2143
+MX23_PAD_EMI_A12__GPIO_2_21			0x2153
+MX23_PAD_EMI_BA0__GPIO_2_22			0x2163
+MX23_PAD_EMI_BA1__GPIO_2_23			0x2173
+MX23_PAD_EMI_CASN__GPIO_2_24			0x2183
+MX23_PAD_EMI_CE0N__GPIO_2_25			0x2193
+MX23_PAD_EMI_CE1N__GPIO_2_26			0x21a3
+MX23_PAD_GPMI_CE1N__GPIO_2_27			0x21b3
+MX23_PAD_GPMI_CE0N__GPIO_2_28			0x21c3
+MX23_PAD_EMI_CKE__GPIO_2_29			0x21d3
+MX23_PAD_EMI_RASN__GPIO_2_30			0x21e3
+MX23_PAD_EMI_WEN__GPIO_2_31			0x21f3

Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt

@@ -0,0 +1,132 @@
+NVIDIA Tegra20 pinmux controller
+
+Required properties:
+- compatible: "nvidia,tegra20-pinmux"
+- reg: Should contain the register physical address and length for each of
+  the tri-state, mux, pull-up/down, and pad control register sets.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+Tegra's pin configuration nodes act as a container for an abitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, tristate, drive strength, etc.
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function or tristate parameter. For this
+reason, even seemingly boolean values are actually tristates in this binding:
+unspecified, off, or on. Unspecified is represented as an absent property,
+and off/on are represented as integer values 0 and 1.
+
+Required subnode-properties:
+- nvidia,pins : An array of strings. Each string contains the name of a pin or
+    group. Valid values for these names are listed below.
+
+Optional subnode-properties:
+- nvidia,function: A string containing the name of the function to mux to the
+  pin or group. Valid values for function names are listed below. See the Tegra
+  TRM to determine which are valid for each pin or group.
+- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
+    0: none, 1: down, 2: up.
+- nvidia,tristate: Integer.
+    0: drive, 1: tristate.
+- nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
+    0: no, 1: yes.
+- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
+    0: no, 1: yes.
+- nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is
+    most power. Controls the drive power or current. See "Low Power Mode"
+    or "LPMD1" and "LPMD0" in the Tegra TRM.
+- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
+    The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
+    Tegra TRM.
+- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
+    The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
+    Tegra TRM.
+- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
+    fastest. The range of valid values depends on the pingroup. See
+    "DRVDN_SLWR" in the Tegra TRM.
+- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
+    fastest. The range of valid values depends on the pingroup. See
+    "DRVUP_SLWF" in the Tegra TRM.
+
+Note that many of these properties are only valid for certain specific pins
+or groups. See the Tegra TRM and various pinmux spreadsheets for complete
+details regarding which groups support which functionality. The Linux pinctrl
+driver may also be a useful reference, since it consolidates, disambiguates,
+and corrects data from all those sources.
+
+Valid values for pin and group names are:
+
+  mux groups:
+
+    These all support nvidia,function, nvidia,tristate, and many support
+    nvidia,pull.
+
+    ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, dap2, dap3, dap4,
+    ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7,
+    gpv, hdint, i2cp, irrx, irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn,
+    ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13,
+    ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, lhs, lm0, lm1, lpp,
+    lpw0, lpw1, lpw2, lsc0, lsc1, lsck, lsda, lsdi, lspi, lvp0, lvp1, lvs,
+    owc, pmc, pta, rm, sdb, sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi,
+    spdo, spia, spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, uad,
+    uca, ucb, uda.
+
+  tristate groups:
+
+    These only support nvidia,pull.
+
+    ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0,
+    ld19_18, ld21_20, ld23_22.
+
+  drive groups:
+
+    With some exceptions, these support nvidia,high-speed-mode,
+    nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength,
+    nvidia,pull-up-strength, nvidia,slew_rate-rising, nvidia,slew_rate-falling.
+
+    drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2,
+    drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg,
+    drive_lcd1, drive_lcd2, drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
+    drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, drive_xm2a,
+    drive_xm2c, drive_xm2d, drive_xm2clk, drive_sdio1, drive_crt, drive_ddc,
+    drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr,
+    drive_uda.
+
+Example:
+
+	pinctrl@70000000 {
+		compatible = "nvidia,tegra20-pinmux";
+		reg = < 0x70000014 0x10    /* Tri-state registers */
+			0x70000080 0x20    /* Mux registers */
+			0x700000a0 0x14    /* Pull-up/down registers */
+			0x70000868 0xa8 >; /* Pad control registers */
+	};
+
+Example board file extract:
+
+	pinctrl@70000000 {
+		sdio4_default: sdio4_default {
+			atb {
+				nvidia,pins = "atb", "gma", "gme";
+				nvidia,function = "sdio4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+		};
+	};
+
+	sdhci@c8000600 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdio4_default>;
+	};

Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt

@@ -0,0 +1,132 @@
+NVIDIA Tegra30 pinmux controller
+
+The Tegra30 pinctrl binding is very similar to the Tegra20 pinctrl binding,
+as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes
+that binding as a baseline, and only documents the differences between the
+two bindings.
+
+Required properties:
+- compatible: "nvidia,tegra30-pinmux"
+- reg: Should contain the register physical address and length for each of
+  the pad control and mux registers.
+
+Tegra30 adds the following optional properties for pin configuration subnodes:
+- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
+- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
+- nvidia,lock: Integer. Lock the pin configuration against further changes
+    until reset. 0: no, 1: yes.
+- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
+
+As with Tegra20, see the Tegra TRM for complete details regarding which groups
+support which functionality.
+
+Valid values for pin and group names are:
+
+  per-pin mux groups:
+
+    These all support nvidia,function, nvidia,tristate, nvidia,pull,
+    nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
+    nvidia,io-reset.
+
+    clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2, dap2_sclk_pa3,
+    dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, gmi_a17_pb0,
+    gmi_a18_pb1, lcd_pwr0_pb2, lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5,
+    sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0, lcd_pwr1_pc1,
+    uart2_txd_pc2, uart2_rxd_pc3, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5,
+    lcd_pwr2_pc6, gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1, lcd_dc1_pd2,
+    sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5, vi_vsync_pd6, vi_hsync_pd7,
+    lcd_d0_pe0, lcd_d1_pe1, lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5,
+    lcd_d6_pe6, lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2, lcd_d11_pf3,
+    lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6, lcd_d15_pf7, gmi_ad0_pg0,
+    gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
+    gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
+    gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
+    gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2, gmi_cs6_n_pi3, gmi_rst_n_pi4,
+    gmi_iordy_pi5, gmi_cs7_n_pi6, gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1,
+    gmi_cs1_n_pj2, lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5,
+    uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs4_n_pk2,
+    gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5, spdif_in_pk6, gmi_a19_pk7,
+    vi_d2_pl0, vi_d3_pl1, vi_d4_pl2, vi_d5_pl3, vi_d6_pl4, vi_d7_pl5,
+    vi_d8_pl6, vi_d9_pl7, lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3,
+    lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7, dap1_fs_pn0,
+    dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, lcd_cs0_n_pn4, lcd_sdout_pn5,
+    lcd_dc0_pn6, hdmi_int_pn7, ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2,
+    ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
+    ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3,
+    dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0,
+    kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
+    kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2,
+    kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
+    kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4,
+    kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1,
+    vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
+    sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4, pu5, pu6, jtag_rtck_pu7, pv0,
+    pv1, pv2, pv3, ddc_scl_pv4, ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7,
+    lcd_cs1_n_pw0, lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4,
+    clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0, spi2_miso_px1,
+    spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4, spi1_sck_px5, spi1_cs0_n_px6,
+    spi1_miso_px7, ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3,
+    sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7,
+    sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3, lcd_sck_pz4,
+    sys_clk_req_pz5, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, sdmmc4_dat0_paa0,
+    sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
+    sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0,
+    cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7,
+    cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3, sdmmc4_clk_pcc4,
+    clk2_req_pcc5, pex_l2_rst_n_pcc6, pex_l2_clkreq_n_pcc7,
+    pex_l0_prsnt_n_pdd0, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2,
+    pex_wake_n_pdd3, pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5,
+    pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0, clk3_req_pee1,
+    clk1_req_pee2, hdmi_cec_pee3, clk_32k_in, core_pwr_req, cpu_pwr_req, owr,
+    pwr_int_n.
+
+  drive groups:
+
+    These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
+    nvidia,slew_rate-rising, nvidia,slew_rate-falling. Most but not all
+    support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode.
+
+    ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, cec, crt, csus, dap1,
+    dap2, dap3, dap4, dbg, ddc, dev3, gma, gmb, gmc, gmd, gme, gmf, gmg,
+    gmh, gpv, lcd1, lcd2, owr, sdio1, sdio2, sdio3, spi, uaa, uab, uart2,
+    uart3, uda, vi1.
+
+Example:
+
+	pinctrl@70000000 {
+		compatible = "nvidia,tegra30-pinmux";
+		reg = < 0x70000868 0xd0     /* Pad control registers */
+			0x70003000 0x3e0 >; /* Mux registers */
+	};
+
+Example board file extract:
+
+	pinctrl@70000000 {
+		sdmmc4_default: pinmux {
+			sdmmc4_clk_pcc4 {
+				nvidia,pins =	"sdmmc4_clk_pcc4",
+						"sdmmc4_rst_n_pcc3";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			sdmmc4_dat0_paa0 {
+				nvidia,pins =	"sdmmc4_dat0_paa0",
+						"sdmmc4_dat1_paa1",
+						"sdmmc4_dat2_paa2",
+						"sdmmc4_dat3_paa3",
+						"sdmmc4_dat4_paa4",
+						"sdmmc4_dat5_paa5",
+						"sdmmc4_dat6_paa6",
+						"sdmmc4_dat7_paa7";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+			};
+		};
+	};
+
+	sdhci@78000400 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc4_default>;
+	};

Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt

@@ -0,0 +1,128 @@
+== Introduction ==
+
+Hardware modules that control pin multiplexing or configuration parameters
+such as pull-up/down, tri-state, drive-strength etc are designated as pin
+controllers. Each pin controller must be represented as a node in device tree,
+just like any other hardware module.
+
+Hardware modules whose signals are affected by pin configuration are
+designated client devices. Again, each client device must be represented as a
+node in device tree, just like any other hardware module.
+
+For a client device to operate correctly, certain pin controllers must
+set up certain specific pin configurations. Some client devices need a
+single static pin configuration, e.g. set up during initialization. Others
+need to reconfigure pins at run-time, for example to tri-state pins when the
+device is inactive. Hence, each client device can define a set of named
+states. The number and names of those states is defined by the client device's
+own binding.
+
+The common pinctrl bindings defined in this file provide an infrastructure
+for client device device tree nodes to map those state names to the pin
+configuration used by those states.
+
+Note that pin controllers themselves may also be client devices of themselves.
+For example, a pin controller may set up its own "active" state when the
+driver loads. This would allow representing a board's static pin configuration
+in a single place, rather than splitting it across multiple client device
+nodes. The decision to do this or not somewhat rests with the author of
+individual board device tree files, and any requirements imposed by the
+bindings for the individual client devices in use by that board, i.e. whether
+they require certain specific named states for dynamic pin configuration.
+
+== Pinctrl client devices ==
+
+For each client device individually, every pin state is assigned an integer
+ID. These numbers start at 0, and are contiguous. For each state ID, a unique
+property exists to define the pin configuration. Each state may also be
+assigned a name. When names are used, another property exists to map from
+those names to the integer IDs.
+
+Each client device's own binding determines the set of states the must be
+defined in its device tree node, and whether to define the set of state
+IDs that must be provided, or whether to define the set of state names that
+must be provided.
+
+Required properties:
+pinctrl-0:	List of phandles, each pointing at a pin configuration
+		node. These referenced pin configuration nodes must be child
+		nodes of the pin controller that they configure. Multiple
+		entries may exist in this list so that multiple pin
+		controllers may be configured, or so that a state may be built
+		from multiple nodes for a single pin controller, each
+		contributing part of the overall configuration. See the next
+		section of this document for details of the format of these
+		pin configuration nodes.
+
+		In some cases, it may be useful to define a state, but for it
+		to be empty. This may be required when a common IP block is
+		used in an SoC either without a pin controller, or where the
+		pin controller does not affect the HW module in question. If
+		the binding for that IP block requires certain pin states to
+		exist, they must still be defined, but may be left empty.
+
+Optional properties:
+pinctrl-1:	List of phandles, each pointing at a pin configuration
+		node within a pin controller.
+...
+pinctrl-n:	List of phandles, each pointing at a pin configuration
+		node within a pin controller.
+pinctrl-names:	The list of names to assign states. List entry 0 defines the
+		name for integer state ID 0, list entry 1 for state ID 1, and
+		so on.
+
+For example:
+
+	/* For a client device requiring named states */
+	device {
+		pinctrl-names = "active", "idle";
+		pinctrl-0 = <&state_0_node_a>;
+		pinctrl-1 = <&state_1_node_a &state_1_node_b>;
+	};
+
+	/* For the same device if using state IDs */
+	device {
+		pinctrl-0 = <&state_0_node_a>;
+		pinctrl-1 = <&state_1_node_a &state_1_node_b>;
+	};
+
+	/*
+	 * For an IP block whose binding supports pin configuration,
+	 * but in use on an SoC that doesn't have any pin control hardware
+	 */
+	device {
+		pinctrl-names = "active", "idle";
+		pinctrl-0 = <>;
+		pinctrl-1 = <>;
+	};
+
+== Pin controller devices ==
+
+Pin controller devices should contain the pin configuration nodes that client
+devices reference.
+
+For example:
+
+	pincontroller {
+		... /* Standard DT properties for the device itself elided */
+
+		state_0_node_a {
+			...
+		};
+		state_1_node_a {
+			...
+		};
+		state_1_node_b {
+			...
+		};
+	}
+
+The contents of each of those pin configuration child nodes is defined
+entirely by the binding for the individual pin controller device. There
+exists no common standard for this content.
+
+The pin configuration nodes need not be direct children of the pin controller
+device; they may be grandchildren, for example. Whether this is legal, and
+whether there is any interaction between the child and intermediate parent
+nodes, is again defined entirely by the binding for the individual pin
+controller device.

Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt

@@ -1,5 +0,0 @@
-NVIDIA Tegra 2 pinmux controller
-
-Required properties:
-- compatible : "nvidia,tegra20-pinmux"
-