mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-24 13:44:26 -04:00
Merge branch 'upstream-fixes' into upstream
Conflicts: drivers/scsi/libata-core.c
This commit is contained in:
commit
3d71b3b0b6
143 changed files with 3289 additions and 831 deletions
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@ -124,6 +124,7 @@ extern int get_option(char **str, int *pint);
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extern char *get_options(const char *str, int nints, int *ints);
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extern unsigned long long memparse(char *ptr, char **retptr);
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extern int core_kernel_text(unsigned long addr);
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extern int __kernel_text_address(unsigned long addr);
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extern int kernel_text_address(unsigned long addr);
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extern int session_of_pgrp(int pgrp);
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@ -69,6 +69,7 @@ struct mmc_data {
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unsigned int timeout_ns; /* data timeout (in ns, max 80ms) */
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unsigned int timeout_clks; /* data timeout (in clocks) */
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unsigned int blksz_bits; /* data block size */
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unsigned int blksz; /* data block size */
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unsigned int blocks; /* number of blocks */
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unsigned int error; /* data error */
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unsigned int flags;
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@ -132,6 +132,7 @@ static inline void rcu_bh_qsctr_inc(int cpu)
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}
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extern int rcu_pending(int cpu);
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extern int rcu_needs_cpu(int cpu);
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/**
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* rcu_read_lock - mark the beginning of an RCU read-side critical section.
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@ -150,6 +150,7 @@ static inline void *kcalloc(size_t n, size_t size, gfp_t flags)
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extern void kfree(const void *);
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extern unsigned int ksize(const void *);
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extern int slab_is_available(void);
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#ifdef CONFIG_NUMA
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extern void *kmem_cache_alloc_node(kmem_cache_t *, gfp_t flags, int node);
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@ -31,18 +31,23 @@ extern struct bus_type spi_bus_type;
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* @master: SPI controller used with the device.
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* @max_speed_hz: Maximum clock rate to be used with this chip
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* (on this board); may be changed by the device's driver.
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* The spi_transfer.speed_hz can override this for each transfer.
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* @chip-select: Chipselect, distinguishing chips handled by "master".
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* @mode: The spi mode defines how data is clocked out and in.
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* This may be changed by the device's driver.
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* The "active low" default for chipselect mode can be overridden,
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* as can the "MSB first" default for each word in a transfer.
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* @bits_per_word: Data transfers involve one or more words; word sizes
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* like eight or 12 bits are common. In-memory wordsizes are
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* like eight or 12 bits are common. In-memory wordsizes are
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* powers of two bytes (e.g. 20 bit samples use 32 bits).
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* This may be changed by the device's driver.
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* This may be changed by the device's driver, or left at the
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* default (0) indicating protocol words are eight bit bytes.
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* The spi_transfer.bits_per_word can override this for each transfer.
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* @irq: Negative, or the number passed to request_irq() to receive
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* interrupts from this device.
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* interrupts from this device.
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* @controller_state: Controller's runtime state
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* @controller_data: Board-specific definitions for controller, such as
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* FIFO initialization parameters; from board_info.controller_data
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* FIFO initialization parameters; from board_info.controller_data
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*
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* An spi_device is used to interchange data between an SPI slave
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* (usually a discrete chip) and CPU memory.
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@ -65,6 +70,7 @@ struct spi_device {
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#define SPI_MODE_2 (SPI_CPOL|0)
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#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
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#define SPI_CS_HIGH 0x04 /* chipselect active high? */
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#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
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u8 bits_per_word;
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int irq;
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void *controller_state;
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@ -73,7 +79,6 @@ struct spi_device {
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// likely need more hooks for more protocol options affecting how
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// the controller talks to each chip, like:
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// - bit order (default is wordwise msb-first)
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// - memory packing (12 bit samples into low bits, others zeroed)
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// - priority
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// - drop chipselect after each word
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@ -143,13 +148,13 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
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* struct spi_master - interface to SPI master controller
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* @cdev: class interface to this driver
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* @bus_num: board-specific (and often SOC-specific) identifier for a
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* given SPI controller.
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* given SPI controller.
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* @num_chipselect: chipselects are used to distinguish individual
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* SPI slaves, and are numbered from zero to num_chipselects.
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* each slave has a chipselect signal, but it's common that not
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* every chipselect is connected to a slave.
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* SPI slaves, and are numbered from zero to num_chipselects.
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* each slave has a chipselect signal, but it's common that not
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* every chipselect is connected to a slave.
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* @setup: updates the device mode and clocking records used by a
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* device's SPI controller; protocol code may call this.
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* device's SPI controller; protocol code may call this.
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* @transfer: adds a message to the controller's transfer queue.
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* @cleanup: frees controller-specific state
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*
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@ -167,13 +172,13 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
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struct spi_master {
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struct class_device cdev;
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/* other than zero (== assign one dynamically), bus_num is fully
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/* other than negative (== assign one dynamically), bus_num is fully
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* board-specific. usually that simplifies to being SOC-specific.
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* example: one SOC has three SPI controllers, numbered 1..3,
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* example: one SOC has three SPI controllers, numbered 0..2,
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* and one board's schematics might show it using SPI-2. software
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* would normally use bus_num=2 for that controller.
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*/
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u16 bus_num;
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s16 bus_num;
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/* chipselects will be integral to many controllers; some others
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* might use board-specific GPIOs.
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@ -268,10 +273,14 @@ extern struct spi_master *spi_busnum_to_master(u16 busnum);
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* @tx_dma: DMA address of tx_buf, if spi_message.is_dma_mapped
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* @rx_dma: DMA address of rx_buf, if spi_message.is_dma_mapped
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* @len: size of rx and tx buffers (in bytes)
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* @speed_hz: Select a speed other then the device default for this
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* transfer. If 0 the default (from spi_device) is used.
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* @bits_per_word: select a bits_per_word other then the device default
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* for this transfer. If 0 the default (from spi_device) is used.
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* @cs_change: affects chipselect after this transfer completes
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* @delay_usecs: microseconds to delay after this transfer before
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* (optionally) changing the chipselect status, then starting
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* the next transfer or completing this spi_message.
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* (optionally) changing the chipselect status, then starting
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* the next transfer or completing this spi_message.
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* @transfer_list: transfers are sequenced through spi_message.transfers
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*
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* SPI transfers always write the same number of bytes as they read.
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@ -322,7 +331,9 @@ struct spi_transfer {
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dma_addr_t rx_dma;
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unsigned cs_change:1;
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u8 bits_per_word;
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u16 delay_usecs;
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u32 speed_hz;
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struct list_head transfer_list;
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};
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@ -356,7 +367,7 @@ struct spi_transfer {
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* and its transfers, ignore them until its completion callback.
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*/
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struct spi_message {
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struct list_head transfers;
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struct list_head transfers;
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struct spi_device *spi;
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@ -374,7 +385,7 @@ struct spi_message {
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*/
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/* completion is reported through a callback */
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void (*complete)(void *context);
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void (*complete)(void *context);
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void *context;
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unsigned actual_length;
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int status;
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@ -30,6 +30,12 @@ struct spi_bitbang {
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struct spi_master *master;
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/* setup_transfer() changes clock and/or wordsize to match settings
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* for this transfer; zeroes restore defaults from spi_device.
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*/
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int (*setup_transfer)(struct spi_device *spi,
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struct spi_transfer *t);
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void (*chipselect)(struct spi_device *spi, int is_on);
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#define BITBANG_CS_ACTIVE 1 /* normally nCS, active low */
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#define BITBANG_CS_INACTIVE 0
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@ -51,6 +57,8 @@ struct spi_bitbang {
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extern int spi_bitbang_setup(struct spi_device *spi);
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extern void spi_bitbang_cleanup(const struct spi_device *spi);
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extern int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m);
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extern int spi_bitbang_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t);
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/* start or stop queue processing */
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extern int spi_bitbang_start(struct spi_bitbang *spi);
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@ -296,7 +296,7 @@ static inline void disable_swap_token(void)
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#define read_swap_cache_async(swp,vma,addr) NULL
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#define lookup_swap_cache(swp) NULL
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#define valid_swaphandles(swp, off) 0
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#define can_share_swap_page(p) 0
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#define can_share_swap_page(p) (page_mapcount(p) == 1)
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#define move_to_swap_cache(p, swp) 1
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#define move_from_swap_cache(p, i, m) 1
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#define __delete_from_swap_cache(p) /*NOTHING*/
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