A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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clk: ux500: Register slimbus clock lookups for u8500

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At the same time the prcc bit for the kclk is corrected to
bit 8 instead of 3.

Signed-off-by: Ulf Hansson <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Acked-by: Lee Jones <[email protected]>
Signed-off-by: Mike Turquette <[email protected]>
This commit is contained in:
Ulf Hansson 2012-10-22 15:58:01 +02:00 • committed by Mike Turquette
commit 3d93067803
1 changed files with 3 additions and 2 deletions
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5
drivers/clk/ux500/u8500_clk.c
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@ -254,6 +254,7 @@ void u8500_clk_init(void)
clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", U8500_CLKRST1_BASE,
BIT(8), 0);
clk_register_clkdev(clk, "apb_pclk", "slimbus0");
clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", U8500_CLKRST1_BASE,
BIT(9), 0);
@ -441,8 +442,8 @@ void u8500_clk_init(void)
clk_register_clkdev(clk, NULL, "nmk-i2c.2");
clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);
/* FIXME: Redefinition of BIT(3). */
U8500_CLKRST1_BASE, BIT(8), CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "slimbus0");
clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
U8500_CLKRST1_BASE, BIT(9), CLK_SET_RATE_GATE);