mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-24 05:29:04 -04:00
Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6
* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6: (46 commits)
mfd: Fix mismatch in twl4030 mutex lock-unlock
mfd: twl6030-pwm.c needs MODULE_LICENSE
mfd: Fix the omap-usb-host clock API usage on usbhs_disable()
mfd: Acknowledge WM8994 IRQs before reporting
mfd: Acknowlege all WM831x IRQs before we handle them
mfd: Avoid two assignments if failures happen in tps65910_i2c_probe
regulator: Storing tps65912 error codes in u8
mfd: Don't leak init_data in tps65910_i2c_probe
regulator: aat2870: Add AAT2870 regulator driver
backlight: Add AAT2870 backlight driver
mfd: Add AAT2870 mfd driver
mfd: Remove dead code from max8997-irq
mfd: Move TPS55910 Kconfig option
mfd: Fix missing stmpe kerneldoc
mfd: Fix off-by-one value range checking for tps65912_i2c_write
mfd: Add devices for WM831x clocking module
mfd: Remove comp{1,2}_threshold sysfs entries in tps65911_comparator_remove
mfd: Don't ask about the TPS65912 core driver in Kconfig
mfd: Fix off by one in WM831x IRQ code
mfd: Add tps65921 support from twl-core
...
This commit is contained in:
Linus Torvalds
commit
3da3f872aa
44 changed files with 4118 additions and 452 deletions
181
include/linux/mfd/aat2870.h
Normal file
181
include/linux/mfd/aat2870.h
Normal file
|
|
@ -0,0 +1,181 @@
|
|||
/*
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||||
* linux/include/linux/mfd/aat2870.h
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||||
*
|
||||
* Copyright (c) 2011, NVIDIA Corporation.
|
||||
* Author: Jin Park <jinyoungp@nvidia.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
|
||||
* 02110-1301 USA
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*/
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#ifndef __LINUX_MFD_AAT2870_H
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#define __LINUX_MFD_AAT2870_H
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#include <linux/debugfs.h>
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#include <linux/i2c.h>
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/* Register offsets */
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#define AAT2870_BL_CH_EN 0x00
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#define AAT2870_BLM 0x01
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#define AAT2870_BLS 0x02
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#define AAT2870_BL1 0x03
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#define AAT2870_BL2 0x04
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#define AAT2870_BL3 0x05
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#define AAT2870_BL4 0x06
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#define AAT2870_BL5 0x07
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#define AAT2870_BL6 0x08
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#define AAT2870_BL7 0x09
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#define AAT2870_BL8 0x0A
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#define AAT2870_FLR 0x0B
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#define AAT2870_FM 0x0C
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#define AAT2870_FS 0x0D
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#define AAT2870_ALS_CFG0 0x0E
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#define AAT2870_ALS_CFG1 0x0F
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#define AAT2870_ALS_CFG2 0x10
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#define AAT2870_AMB 0x11
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#define AAT2870_ALS0 0x12
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#define AAT2870_ALS1 0x13
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#define AAT2870_ALS2 0x14
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#define AAT2870_ALS3 0x15
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#define AAT2870_ALS4 0x16
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#define AAT2870_ALS5 0x17
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#define AAT2870_ALS6 0x18
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#define AAT2870_ALS7 0x19
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#define AAT2870_ALS8 0x1A
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#define AAT2870_ALS9 0x1B
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#define AAT2870_ALSA 0x1C
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#define AAT2870_ALSB 0x1D
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#define AAT2870_ALSC 0x1E
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#define AAT2870_ALSD 0x1F
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#define AAT2870_ALSE 0x20
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#define AAT2870_ALSF 0x21
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#define AAT2870_SUB_SET 0x22
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#define AAT2870_SUB_CTRL 0x23
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#define AAT2870_LDO_AB 0x24
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#define AAT2870_LDO_CD 0x25
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#define AAT2870_LDO_EN 0x26
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#define AAT2870_REG_NUM 0x27
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||||
|
||||
/* Device IDs */
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enum aat2870_id {
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AAT2870_ID_BL,
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AAT2870_ID_LDOA,
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AAT2870_ID_LDOB,
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AAT2870_ID_LDOC,
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AAT2870_ID_LDOD
|
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};
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|
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/* Backlight channels */
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#define AAT2870_BL_CH1 0x01
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#define AAT2870_BL_CH2 0x02
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#define AAT2870_BL_CH3 0x04
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#define AAT2870_BL_CH4 0x08
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#define AAT2870_BL_CH5 0x10
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#define AAT2870_BL_CH6 0x20
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#define AAT2870_BL_CH7 0x40
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#define AAT2870_BL_CH8 0x80
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#define AAT2870_BL_CH_ALL 0xFF
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|
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/* Backlight current magnitude (mA) */
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enum aat2870_current {
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AAT2870_CURRENT_0_45,
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AAT2870_CURRENT_0_90,
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AAT2870_CURRENT_1_80,
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AAT2870_CURRENT_2_70,
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AAT2870_CURRENT_3_60,
|
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AAT2870_CURRENT_4_50,
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AAT2870_CURRENT_5_40,
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AAT2870_CURRENT_6_30,
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AAT2870_CURRENT_7_20,
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AAT2870_CURRENT_8_10,
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AAT2870_CURRENT_9_00,
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AAT2870_CURRENT_9_90,
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AAT2870_CURRENT_10_8,
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AAT2870_CURRENT_11_7,
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AAT2870_CURRENT_12_6,
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AAT2870_CURRENT_13_5,
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AAT2870_CURRENT_14_4,
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AAT2870_CURRENT_15_3,
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AAT2870_CURRENT_16_2,
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AAT2870_CURRENT_17_1,
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AAT2870_CURRENT_18_0,
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AAT2870_CURRENT_18_9,
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AAT2870_CURRENT_19_8,
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AAT2870_CURRENT_20_7,
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AAT2870_CURRENT_21_6,
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AAT2870_CURRENT_22_5,
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AAT2870_CURRENT_23_4,
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AAT2870_CURRENT_24_3,
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AAT2870_CURRENT_25_2,
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AAT2870_CURRENT_26_1,
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AAT2870_CURRENT_27_0,
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AAT2870_CURRENT_27_9
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};
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struct aat2870_register {
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bool readable;
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bool writeable;
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u8 value;
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};
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struct aat2870_data {
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struct device *dev;
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struct i2c_client *client;
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struct mutex io_lock;
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struct aat2870_register *reg_cache; /* register cache */
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int en_pin; /* enable GPIO pin (if < 0, ignore this value) */
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bool is_enable;
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/* init and uninit for platform specified */
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int (*init)(struct aat2870_data *aat2870);
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void (*uninit)(struct aat2870_data *aat2870);
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/* i2c io funcntions */
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int (*read)(struct aat2870_data *aat2870, u8 addr, u8 *val);
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int (*write)(struct aat2870_data *aat2870, u8 addr, u8 val);
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int (*update)(struct aat2870_data *aat2870, u8 addr, u8 mask, u8 val);
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/* for debugfs */
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struct dentry *dentry_root;
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struct dentry *dentry_reg;
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};
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struct aat2870_subdev_info {
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int id;
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const char *name;
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void *platform_data;
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};
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struct aat2870_platform_data {
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int en_pin; /* enable GPIO pin (if < 0, ignore this value) */
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struct aat2870_subdev_info *subdevs;
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int num_subdevs;
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/* init and uninit for platform specified */
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int (*init)(struct aat2870_data *aat2870);
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void (*uninit)(struct aat2870_data *aat2870);
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};
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struct aat2870_bl_platform_data {
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/* backlight channels, default is AAT2870_BL_CH_ALL */
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int channels;
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/* backlight current magnitude, default is AAT2870_CURRENT_27_9 */
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int max_current;
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/* maximum brightness, default is 255 */
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int max_brightness;
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};
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#endif /* __LINUX_MFD_AAT2870_H */
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|
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@ -28,6 +28,7 @@
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#define AB8500_INTERRUPT 0xE
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#define AB8500_RTC 0xF
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#define AB8500_MISC 0x10
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#define AB8500_DEVELOPMENT 0x11
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#define AB8500_DEBUG 0x12
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#define AB8500_PROD_TEST 0x13
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#define AB8500_OTP_EMUL 0x15
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@ -74,13 +75,6 @@
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#define AB8500_INT_ACC_DETECT_21DB_F 37
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#define AB8500_INT_ACC_DETECT_21DB_R 38
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#define AB8500_INT_GP_SW_ADC_CONV_END 39
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#define AB8500_INT_ACC_DETECT_1DB_F 33
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#define AB8500_INT_ACC_DETECT_1DB_R 34
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#define AB8500_INT_ACC_DETECT_22DB_F 35
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#define AB8500_INT_ACC_DETECT_22DB_R 36
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#define AB8500_INT_ACC_DETECT_21DB_F 37
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#define AB8500_INT_ACC_DETECT_21DB_R 38
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#define AB8500_INT_GP_SW_ADC_CONV_END 39
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#define AB8500_INT_GPIO6R 40
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#define AB8500_INT_GPIO7R 41
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#define AB8500_INT_GPIO8R 42
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|
|
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@ -57,6 +57,7 @@ struct stmpe_variant_info;
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* @irq_lock: IRQ bus lock
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* @dev: device, mostly for dev_dbg()
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* @i2c: i2c client
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* @partnum: part number
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* @variant: the detected STMPE model number
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* @regs: list of addresses of registers which are at different addresses on
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* different variants. Indexed by one of STMPE_IDX_*.
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@ -121,6 +122,8 @@ struct stmpe_keypad_platform_data {
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* @norequest_mask: bitmask specifying which GPIOs should _not_ be
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* requestable due to different usage (e.g. touch, keypad)
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* STMPE_GPIO_NOREQ_* macros can be used here.
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* @setup: board specific setup callback.
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* @remove: board specific remove callback
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*/
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struct stmpe_gpio_platform_data {
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int gpio_base;
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@ -791,6 +791,7 @@ int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
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void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base);
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int tps65910_irq_init(struct tps65910 *tps65910, int irq,
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struct tps65910_platform_data *pdata);
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int tps65910_irq_exit(struct tps65910 *tps65910);
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static inline int tps65910_chip_id(struct tps65910 *tps65910)
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{
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327
include/linux/mfd/tps65912.h
Normal file
327
include/linux/mfd/tps65912.h
Normal file
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@ -0,0 +1,327 @@
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/*
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* tps65912.h -- TI TPS6591x
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*
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* Copyright 2011 Texas Instruments Inc.
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*
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* Author: Margarita Olaya <magi@slimlogic.co.uk>
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||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
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*
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*/
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#ifndef __LINUX_MFD_TPS65912_H
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#define __LINUX_MFD_TPS65912_H
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/* TPS regulator type list */
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#define REGULATOR_LDO 0
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#define REGULATOR_DCDC 1
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/*
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* List of registers for TPS65912
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*/
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#define TPS65912_DCDC1_CTRL 0x00
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#define TPS65912_DCDC2_CTRL 0x01
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#define TPS65912_DCDC3_CTRL 0x02
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#define TPS65912_DCDC4_CTRL 0x03
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#define TPS65912_DCDC1_OP 0x04
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#define TPS65912_DCDC1_AVS 0x05
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#define TPS65912_DCDC1_LIMIT 0x06
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#define TPS65912_DCDC2_OP 0x07
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#define TPS65912_DCDC2_AVS 0x08
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#define TPS65912_DCDC2_LIMIT 0x09
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#define TPS65912_DCDC3_OP 0x0A
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#define TPS65912_DCDC3_AVS 0x0B
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#define TPS65912_DCDC3_LIMIT 0x0C
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#define TPS65912_DCDC4_OP 0x0D
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#define TPS65912_DCDC4_AVS 0x0E
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#define TPS65912_DCDC4_LIMIT 0x0F
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#define TPS65912_LDO1_OP 0x10
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#define TPS65912_LDO1_AVS 0x11
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#define TPS65912_LDO1_LIMIT 0x12
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#define TPS65912_LDO2_OP 0x13
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#define TPS65912_LDO2_AVS 0x14
|
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#define TPS65912_LDO2_LIMIT 0x15
|
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#define TPS65912_LDO3_OP 0x16
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#define TPS65912_LDO3_AVS 0x17
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#define TPS65912_LDO3_LIMIT 0x18
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#define TPS65912_LDO4_OP 0x19
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#define TPS65912_LDO4_AVS 0x1A
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#define TPS65912_LDO4_LIMIT 0x1B
|
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#define TPS65912_LDO5 0x1C
|
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#define TPS65912_LDO6 0x1D
|
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#define TPS65912_LDO7 0x1E
|
||||
#define TPS65912_LDO8 0x1F
|
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#define TPS65912_LDO9 0x20
|
||||
#define TPS65912_LDO10 0x21
|
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#define TPS65912_THRM 0x22
|
||||
#define TPS65912_CLK32OUT 0x23
|
||||
#define TPS65912_DEVCTRL 0x24
|
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#define TPS65912_DEVCTRL2 0x25
|
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#define TPS65912_I2C_SPI_CFG 0x26
|
||||
#define TPS65912_KEEP_ON 0x27
|
||||
#define TPS65912_KEEP_ON2 0x28
|
||||
#define TPS65912_SET_OFF1 0x29
|
||||
#define TPS65912_SET_OFF2 0x2A
|
||||
#define TPS65912_DEF_VOLT 0x2B
|
||||
#define TPS65912_DEF_VOLT_MAPPING 0x2C
|
||||
#define TPS65912_DISCHARGE 0x2D
|
||||
#define TPS65912_DISCHARGE2 0x2E
|
||||
#define TPS65912_EN1_SET1 0x2F
|
||||
#define TPS65912_EN1_SET2 0x30
|
||||
#define TPS65912_EN2_SET1 0x31
|
||||
#define TPS65912_EN2_SET2 0x32
|
||||
#define TPS65912_EN3_SET1 0x33
|
||||
#define TPS65912_EN3_SET2 0x34
|
||||
#define TPS65912_EN4_SET1 0x35
|
||||
#define TPS65912_EN4_SET2 0x36
|
||||
#define TPS65912_PGOOD 0x37
|
||||
#define TPS65912_PGOOD2 0x38
|
||||
#define TPS65912_INT_STS 0x39
|
||||
#define TPS65912_INT_MSK 0x3A
|
||||
#define TPS65912_INT_STS2 0x3B
|
||||
#define TPS65912_INT_MSK2 0x3C
|
||||
#define TPS65912_INT_STS3 0x3D
|
||||
#define TPS65912_INT_MSK3 0x3E
|
||||
#define TPS65912_INT_STS4 0x3F
|
||||
#define TPS65912_INT_MSK4 0x40
|
||||
#define TPS65912_GPIO1 0x41
|
||||
#define TPS65912_GPIO2 0x42
|
||||
#define TPS65912_GPIO3 0x43
|
||||
#define TPS65912_GPIO4 0x44
|
||||
#define TPS65912_GPIO5 0x45
|
||||
#define TPS65912_VMON 0x46
|
||||
#define TPS65912_LEDA_CTRL1 0x47
|
||||
#define TPS65912_LEDA_CTRL2 0x48
|
||||
#define TPS65912_LEDA_CTRL3 0x49
|
||||
#define TPS65912_LEDA_CTRL4 0x4A
|
||||
#define TPS65912_LEDA_CTRL5 0x4B
|
||||
#define TPS65912_LEDA_CTRL6 0x4C
|
||||
#define TPS65912_LEDA_CTRL7 0x4D
|
||||
#define TPS65912_LEDA_CTRL8 0x4E
|
||||
#define TPS65912_LEDB_CTRL1 0x4F
|
||||
#define TPS65912_LEDB_CTRL2 0x50
|
||||
#define TPS65912_LEDB_CTRL3 0x51
|
||||
#define TPS65912_LEDB_CTRL4 0x52
|
||||
#define TPS65912_LEDB_CTRL5 0x53
|
||||
#define TPS65912_LEDB_CTRL6 0x54
|
||||
#define TPS65912_LEDB_CTRL7 0x55
|
||||
#define TPS65912_LEDB_CTRL8 0x56
|
||||
#define TPS65912_LEDC_CTRL1 0x57
|
||||
#define TPS65912_LEDC_CTRL2 0x58
|
||||
#define TPS65912_LEDC_CTRL3 0x59
|
||||
#define TPS65912_LEDC_CTRL4 0x5A
|
||||
#define TPS65912_LEDC_CTRL5 0x5B
|
||||
#define TPS65912_LEDC_CTRL6 0x5C
|
||||
#define TPS65912_LEDC_CTRL7 0x5D
|
||||
#define TPS65912_LEDC_CTRL8 0x5E
|
||||
#define TPS65912_LED_RAMP_UP_TIME 0x5F
|
||||
#define TPS65912_LED_RAMP_DOWN_TIME 0x60
|
||||
#define TPS65912_LED_SEQ_EN 0x61
|
||||
#define TPS65912_LOADSWITCH 0x62
|
||||
#define TPS65912_SPARE 0x63
|
||||
#define TPS65912_VERNUM 0x64
|
||||
#define TPS6591X_MAX_REGISTER 0x64
|
||||
|
||||
/* IRQ Definitions */
|
||||
#define TPS65912_IRQ_PWRHOLD_F 0
|
||||
#define TPS65912_IRQ_VMON 1
|
||||
#define TPS65912_IRQ_PWRON 2
|
||||
#define TPS65912_IRQ_PWRON_LP 3
|
||||
#define TPS65912_IRQ_PWRHOLD_R 4
|
||||
#define TPS65912_IRQ_HOTDIE 5
|
||||
#define TPS65912_IRQ_GPIO1_R 6
|
||||
#define TPS65912_IRQ_GPIO1_F 7
|
||||
#define TPS65912_IRQ_GPIO2_R 8
|
||||
#define TPS65912_IRQ_GPIO2_F 9
|
||||
#define TPS65912_IRQ_GPIO3_R 10
|
||||
#define TPS65912_IRQ_GPIO3_F 11
|
||||
#define TPS65912_IRQ_GPIO4_R 12
|
||||
#define TPS65912_IRQ_GPIO4_F 13
|
||||
#define TPS65912_IRQ_GPIO5_R 14
|
||||
#define TPS65912_IRQ_GPIO5_F 15
|
||||
#define TPS65912_IRQ_PGOOD_DCDC1 16
|
||||
#define TPS65912_IRQ_PGOOD_DCDC2 17
|
||||
#define TPS65912_IRQ_PGOOD_DCDC3 18
|
||||
#define TPS65912_IRQ_PGOOD_DCDC4 19
|
||||
#define TPS65912_IRQ_PGOOD_LDO1 20
|
||||
#define TPS65912_IRQ_PGOOD_LDO2 21
|
||||
#define TPS65912_IRQ_PGOOD_LDO3 22
|
||||
#define TPS65912_IRQ_PGOOD_LDO4 23
|
||||
#define TPS65912_IRQ_PGOOD_LDO5 24
|
||||
#define TPS65912_IRQ_PGOOD_LDO6 25
|
||||
#define TPS65912_IRQ_PGOOD_LDO7 26
|
||||
#define TPS65912_IRQ_PGOOD_LD08 27
|
||||
#define TPS65912_IRQ_PGOOD_LDO9 28
|
||||
#define TPS65912_IRQ_PGOOD_LDO10 29
|
||||
|
||||
#define TPS65912_NUM_IRQ 30
|
||||
|
||||
/* GPIO 1 and 2 Register Definitions */
|
||||
#define GPIO_SLEEP_MASK 0x80
|
||||
#define GPIO_SLEEP_SHIFT 7
|
||||
#define GPIO_DEB_MASK 0x10
|
||||
#define GPIO_DEB_SHIFT 4
|
||||
#define GPIO_CFG_MASK 0x04
|
||||
#define GPIO_CFG_SHIFT 2
|
||||
#define GPIO_STS_MASK 0x02
|
||||
#define GPIO_STS_SHIFT 1
|
||||
#define GPIO_SET_MASK 0x01
|
||||
#define GPIO_SET_SHIFT 0
|
||||
|
||||
/* GPIO 3 Register Definitions */
|
||||
#define GPIO3_SLEEP_MASK 0x80
|
||||
#define GPIO3_SLEEP_SHIFT 7
|
||||
#define GPIO3_SEL_MASK 0x40
|
||||
#define GPIO3_SEL_SHIFT 6
|
||||
#define GPIO3_ODEN_MASK 0x20
|
||||
#define GPIO3_ODEN_SHIFT 5
|
||||
#define GPIO3_DEB_MASK 0x10
|
||||
#define GPIO3_DEB_SHIFT 4
|
||||
#define GPIO3_PDEN_MASK 0x08
|
||||
#define GPIO3_PDEN_SHIFT 3
|
||||
#define GPIO3_CFG_MASK 0x04
|
||||
#define GPIO3_CFG_SHIFT 2
|
||||
#define GPIO3_STS_MASK 0x02
|
||||
#define GPIO3_STS_SHIFT 1
|
||||
#define GPIO3_SET_MASK 0x01
|
||||
#define GPIO3_SET_SHIFT 0
|
||||
|
||||
/* GPIO 4 Register Definitions */
|
||||
#define GPIO4_SLEEP_MASK 0x80
|
||||
#define GPIO4_SLEEP_SHIFT 7
|
||||
#define GPIO4_SEL_MASK 0x40
|
||||
#define GPIO4_SEL_SHIFT 6
|
||||
#define GPIO4_ODEN_MASK 0x20
|
||||
#define GPIO4_ODEN_SHIFT 5
|
||||
#define GPIO4_DEB_MASK 0x10
|
||||
#define GPIO4_DEB_SHIFT 4
|
||||
#define GPIO4_PDEN_MASK 0x08
|
||||
#define GPIO4_PDEN_SHIFT 3
|
||||
#define GPIO4_CFG_MASK 0x04
|
||||
#define GPIO4_CFG_SHIFT 2
|
||||
#define GPIO4_STS_MASK 0x02
|
||||
#define GPIO4_STS_SHIFT 1
|
||||
#define GPIO4_SET_MASK 0x01
|
||||
#define GPIO4_SET_SHIFT 0
|
||||
|
||||
/* Register THERM (0x80) register.RegisterDescription */
|
||||
#define THERM_THERM_HD_MASK 0x20
|
||||
#define THERM_THERM_HD_SHIFT 5
|
||||
#define THERM_THERM_TS_MASK 0x10
|
||||
#define THERM_THERM_TS_SHIFT 4
|
||||
#define THERM_THERM_HDSEL_MASK 0x0C
|
||||
#define THERM_THERM_HDSEL_SHIFT 2
|
||||
#define THERM_RSVD1_MASK 0x02
|
||||
#define THERM_RSVD1_SHIFT 1
|
||||
#define THERM_THERM_STATE_MASK 0x01
|
||||
#define THERM_THERM_STATE_SHIFT 0
|
||||
|
||||
/* Register DCDCCTRL1 register.RegisterDescription */
|
||||
#define DCDCCTRL_VCON_ENABLE_MASK 0x80
|
||||
#define DCDCCTRL_VCON_ENABLE_SHIFT 7
|
||||
#define DCDCCTRL_VCON_RANGE1_MASK 0x40
|
||||
#define DCDCCTRL_VCON_RANGE1_SHIFT 6
|
||||
#define DCDCCTRL_VCON_RANGE0_MASK 0x20
|
||||
#define DCDCCTRL_VCON_RANGE0_SHIFT 5
|
||||
#define DCDCCTRL_TSTEP2_MASK 0x10
|
||||
#define DCDCCTRL_TSTEP2_SHIFT 4
|
||||
#define DCDCCTRL_TSTEP1_MASK 0x08
|
||||
#define DCDCCTRL_TSTEP1_SHIFT 3
|
||||
#define DCDCCTRL_TSTEP0_MASK 0x04
|
||||
#define DCDCCTRL_TSTEP0_SHIFT 2
|
||||
#define DCDCCTRL_DCDC1_MODE_MASK 0x02
|
||||
#define DCDCCTRL_DCDC1_MODE_SHIFT 1
|
||||
|
||||
/* Register DCDCCTRL2 and DCDCCTRL3 register.RegisterDescription */
|
||||
#define DCDCCTRL_TSTEP2_MASK 0x10
|
||||
#define DCDCCTRL_TSTEP2_SHIFT 4
|
||||
#define DCDCCTRL_TSTEP1_MASK 0x08
|
||||
#define DCDCCTRL_TSTEP1_SHIFT 3
|
||||
#define DCDCCTRL_TSTEP0_MASK 0x04
|
||||
#define DCDCCTRL_TSTEP0_SHIFT 2
|
||||
#define DCDCCTRL_DCDC_MODE_MASK 0x02
|
||||
#define DCDCCTRL_DCDC_MODE_SHIFT 1
|
||||
#define DCDCCTRL_RSVD0_MASK 0x01
|
||||
#define DCDCCTRL_RSVD0_SHIFT 0
|
||||
|
||||
/* Register DCDCCTRL4 register.RegisterDescription */
|
||||
#define DCDCCTRL_RAMP_TIME_MASK 0x01
|
||||
#define DCDCCTRL_RAMP_TIME_SHIFT 0
|
||||
|
||||
/* Register DCDCx_AVS */
|
||||
#define DCDC_AVS_ENABLE_MASK 0x80
|
||||
#define DCDC_AVS_ENABLE_SHIFT 7
|
||||
#define DCDC_AVS_ECO_MASK 0x40
|
||||
#define DCDC_AVS_ECO_SHIFT 6
|
||||
|
||||
/* Register DCDCx_LIMIT */
|
||||
#define DCDC_LIMIT_RANGE_MASK 0xC0
|
||||
#define DCDC_LIMIT_RANGE_SHIFT 6
|
||||
#define DCDC_LIMIT_MAX_SEL_MASK 0x3F
|
||||
#define DCDC_LIMIT_MAX_SEL_SHIFT 0
|
||||
|
||||
/**
|
||||
* struct tps65912_board
|
||||
* Board platform dat may be used to initialize regulators.
|
||||
*/
|
||||
struct tps65912_board {
|
||||
int is_dcdc1_avs;
|
||||
int is_dcdc2_avs;
|
||||
int is_dcdc3_avs;
|
||||
int is_dcdc4_avs;
|
||||
int irq;
|
||||
int irq_base;
|
||||
int gpio_base;
|
||||
struct regulator_init_data *tps65912_pmic_init_data;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct tps65912 - tps65912 sub-driver chip access routines
|
||||
*/
|
||||
|
||||
struct tps65912 {
|
||||
struct device *dev;
|
||||
/* for read/write acces */
|
||||
struct mutex io_mutex;
|
||||
|
||||
/* For device IO interfaces: I2C or SPI */
|
||||
void *control_data;
|
||||
|
||||
int (*read)(struct tps65912 *tps65912, u8 reg, int size, void *dest);
|
||||
int (*write)(struct tps65912 *tps65912, u8 reg, int size, void *src);
|
||||
|
||||
/* Client devices */
|
||||
struct tps65912_pmic *pmic;
|
||||
|
||||
/* GPIO Handling */
|
||||
struct gpio_chip gpio;
|
||||
|
||||
/* IRQ Handling */
|
||||
struct mutex irq_lock;
|
||||
int chip_irq;
|
||||
int irq_base;
|
||||
int irq_num;
|
||||
u32 irq_mask;
|
||||
};
|
||||
|
||||
struct tps65912_platform_data {
|
||||
int irq;
|
||||
int irq_base;
|
||||
};
|
||||
|
||||
unsigned int tps_chip(void);
|
||||
|
||||
int tps65912_set_bits(struct tps65912 *tps65912, u8 reg, u8 mask);
|
||||
int tps65912_clear_bits(struct tps65912 *tps65912, u8 reg, u8 mask);
|
||||
int tps65912_reg_read(struct tps65912 *tps65912, u8 reg);
|
||||
int tps65912_reg_write(struct tps65912 *tps65912, u8 reg, u8 val);
|
||||
int tps65912_device_init(struct tps65912 *tps65912);
|
||||
void tps65912_device_exit(struct tps65912 *tps65912);
|
||||
int tps65912_irq_init(struct tps65912 *tps65912, int irq,
|
||||
struct tps65912_platform_data *pdata);
|
||||
|
||||
#endif /* __LINUX_MFD_TPS65912_H */
|
||||
|
|
@ -17,6 +17,7 @@
|
|||
|
||||
#include <linux/completion.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/list.h>
|
||||
|
||||
/*
|
||||
* Register values.
|
||||
|
|
@ -234,9 +235,111 @@
|
|||
#define WM831X_ON_PIN_TO_SHIFT 0 /* ON_PIN_TO - [1:0] */
|
||||
#define WM831X_ON_PIN_TO_WIDTH 2 /* ON_PIN_TO - [1:0] */
|
||||
|
||||
/*
|
||||
* R16528 (0x4090) - Clock Control 1
|
||||
*/
|
||||
#define WM831X_CLKOUT_ENA 0x8000 /* CLKOUT_ENA */
|
||||
#define WM831X_CLKOUT_ENA_MASK 0x8000 /* CLKOUT_ENA */
|
||||
#define WM831X_CLKOUT_ENA_SHIFT 15 /* CLKOUT_ENA */
|
||||
#define WM831X_CLKOUT_ENA_WIDTH 1 /* CLKOUT_ENA */
|
||||
#define WM831X_CLKOUT_OD 0x2000 /* CLKOUT_OD */
|
||||
#define WM831X_CLKOUT_OD_MASK 0x2000 /* CLKOUT_OD */
|
||||
#define WM831X_CLKOUT_OD_SHIFT 13 /* CLKOUT_OD */
|
||||
#define WM831X_CLKOUT_OD_WIDTH 1 /* CLKOUT_OD */
|
||||
#define WM831X_CLKOUT_SLOT_MASK 0x0700 /* CLKOUT_SLOT - [10:8] */
|
||||
#define WM831X_CLKOUT_SLOT_SHIFT 8 /* CLKOUT_SLOT - [10:8] */
|
||||
#define WM831X_CLKOUT_SLOT_WIDTH 3 /* CLKOUT_SLOT - [10:8] */
|
||||
#define WM831X_CLKOUT_SLPSLOT_MASK 0x0070 /* CLKOUT_SLPSLOT - [6:4] */
|
||||
#define WM831X_CLKOUT_SLPSLOT_SHIFT 4 /* CLKOUT_SLPSLOT - [6:4] */
|
||||
#define WM831X_CLKOUT_SLPSLOT_WIDTH 3 /* CLKOUT_SLPSLOT - [6:4] */
|
||||
#define WM831X_CLKOUT_SRC 0x0001 /* CLKOUT_SRC */
|
||||
#define WM831X_CLKOUT_SRC_MASK 0x0001 /* CLKOUT_SRC */
|
||||
#define WM831X_CLKOUT_SRC_SHIFT 0 /* CLKOUT_SRC */
|
||||
#define WM831X_CLKOUT_SRC_WIDTH 1 /* CLKOUT_SRC */
|
||||
|
||||
/*
|
||||
* R16529 (0x4091) - Clock Control 2
|
||||
*/
|
||||
#define WM831X_XTAL_INH 0x8000 /* XTAL_INH */
|
||||
#define WM831X_XTAL_INH_MASK 0x8000 /* XTAL_INH */
|
||||
#define WM831X_XTAL_INH_SHIFT 15 /* XTAL_INH */
|
||||
#define WM831X_XTAL_INH_WIDTH 1 /* XTAL_INH */
|
||||
#define WM831X_XTAL_ENA 0x2000 /* XTAL_ENA */
|
||||
#define WM831X_XTAL_ENA_MASK 0x2000 /* XTAL_ENA */
|
||||
#define WM831X_XTAL_ENA_SHIFT 13 /* XTAL_ENA */
|
||||
#define WM831X_XTAL_ENA_WIDTH 1 /* XTAL_ENA */
|
||||
#define WM831X_XTAL_BKUPENA 0x1000 /* XTAL_BKUPENA */
|
||||
#define WM831X_XTAL_BKUPENA_MASK 0x1000 /* XTAL_BKUPENA */
|
||||
#define WM831X_XTAL_BKUPENA_SHIFT 12 /* XTAL_BKUPENA */
|
||||
#define WM831X_XTAL_BKUPENA_WIDTH 1 /* XTAL_BKUPENA */
|
||||
#define WM831X_FLL_AUTO 0x0080 /* FLL_AUTO */
|
||||
#define WM831X_FLL_AUTO_MASK 0x0080 /* FLL_AUTO */
|
||||
#define WM831X_FLL_AUTO_SHIFT 7 /* FLL_AUTO */
|
||||
#define WM831X_FLL_AUTO_WIDTH 1 /* FLL_AUTO */
|
||||
#define WM831X_FLL_AUTO_FREQ_MASK 0x0007 /* FLL_AUTO_FREQ - [2:0] */
|
||||
#define WM831X_FLL_AUTO_FREQ_SHIFT 0 /* FLL_AUTO_FREQ - [2:0] */
|
||||
#define WM831X_FLL_AUTO_FREQ_WIDTH 3 /* FLL_AUTO_FREQ - [2:0] */
|
||||
|
||||
/*
|
||||
* R16530 (0x4092) - FLL Control 1
|
||||
*/
|
||||
#define WM831X_FLL_FRAC 0x0004 /* FLL_FRAC */
|
||||
#define WM831X_FLL_FRAC_MASK 0x0004 /* FLL_FRAC */
|
||||
#define WM831X_FLL_FRAC_SHIFT 2 /* FLL_FRAC */
|
||||
#define WM831X_FLL_FRAC_WIDTH 1 /* FLL_FRAC */
|
||||
#define WM831X_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */
|
||||
#define WM831X_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */
|
||||
#define WM831X_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */
|
||||
#define WM831X_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */
|
||||
#define WM831X_FLL_ENA 0x0001 /* FLL_ENA */
|
||||
#define WM831X_FLL_ENA_MASK 0x0001 /* FLL_ENA */
|
||||
#define WM831X_FLL_ENA_SHIFT 0 /* FLL_ENA */
|
||||
#define WM831X_FLL_ENA_WIDTH 1 /* FLL_ENA */
|
||||
|
||||
/*
|
||||
* R16531 (0x4093) - FLL Control 2
|
||||
*/
|
||||
#define WM831X_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */
|
||||
#define WM831X_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */
|
||||
#define WM831X_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */
|
||||
#define WM831X_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */
|
||||
#define WM831X_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */
|
||||
#define WM831X_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */
|
||||
#define WM831X_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
|
||||
#define WM831X_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
|
||||
#define WM831X_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
|
||||
|
||||
/*
|
||||
* R16532 (0x4094) - FLL Control 3
|
||||
*/
|
||||
#define WM831X_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */
|
||||
#define WM831X_FLL_K_SHIFT 0 /* FLL_K - [15:0] */
|
||||
#define WM831X_FLL_K_WIDTH 16 /* FLL_K - [15:0] */
|
||||
|
||||
/*
|
||||
* R16533 (0x4095) - FLL Control 4
|
||||
*/
|
||||
#define WM831X_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */
|
||||
#define WM831X_FLL_N_SHIFT 5 /* FLL_N - [14:5] */
|
||||
#define WM831X_FLL_N_WIDTH 10 /* FLL_N - [14:5] */
|
||||
#define WM831X_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */
|
||||
#define WM831X_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */
|
||||
#define WM831X_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */
|
||||
|
||||
/*
|
||||
* R16534 (0x4096) - FLL Control 5
|
||||
*/
|
||||
#define WM831X_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */
|
||||
#define WM831X_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */
|
||||
#define WM831X_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */
|
||||
#define WM831X_FLL_CLK_SRC_MASK 0x0003 /* FLL_CLK_SRC - [1:0] */
|
||||
#define WM831X_FLL_CLK_SRC_SHIFT 0 /* FLL_CLK_SRC - [1:0] */
|
||||
#define WM831X_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */
|
||||
|
||||
struct regulator_dev;
|
||||
|
||||
#define WM831X_NUM_IRQ_REGS 5
|
||||
#define WM831X_NUM_GPIO_REGS 16
|
||||
|
||||
enum wm831x_parent {
|
||||
WM8310 = 0x8310,
|
||||
|
|
@ -248,6 +351,12 @@ enum wm831x_parent {
|
|||
WM8326 = 0x8326,
|
||||
};
|
||||
|
||||
struct wm831x;
|
||||
enum wm831x_auxadc;
|
||||
|
||||
typedef int (*wm831x_auxadc_read_fn)(struct wm831x *wm831x,
|
||||
enum wm831x_auxadc input);
|
||||
|
||||
struct wm831x {
|
||||
struct mutex io_lock;
|
||||
|
||||
|
|
@ -261,7 +370,7 @@ struct wm831x {
|
|||
|
||||
int irq; /* Our chip IRQ */
|
||||
struct mutex irq_lock;
|
||||
unsigned int irq_base;
|
||||
int irq_base;
|
||||
int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */
|
||||
int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */
|
||||
|
||||
|
|
@ -272,8 +381,13 @@ struct wm831x {
|
|||
|
||||
int num_gpio;
|
||||
|
||||
/* Used by the interrupt controller code to post writes */
|
||||
int gpio_update[WM831X_NUM_GPIO_REGS];
|
||||
|
||||
struct mutex auxadc_lock;
|
||||
struct completion auxadc_done;
|
||||
struct list_head auxadc_pending;
|
||||
u16 auxadc_active;
|
||||
wm831x_auxadc_read_fn auxadc_read;
|
||||
|
||||
/* The WM831x has a security key blocking access to certain
|
||||
* registers. The mutex is taken by the accessors for locking
|
||||
|
|
@ -300,5 +414,6 @@ void wm831x_device_exit(struct wm831x *wm831x);
|
|||
int wm831x_device_suspend(struct wm831x *wm831x);
|
||||
int wm831x_irq_init(struct wm831x *wm831x, int irq);
|
||||
void wm831x_irq_exit(struct wm831x *wm831x);
|
||||
void wm831x_auxadc_init(struct wm831x *wm831x);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -120,6 +120,9 @@ struct wm831x_pdata {
|
|||
/** Put the /IRQ line into CMOS mode */
|
||||
bool irq_cmos;
|
||||
|
||||
/** Disable the touchscreen */
|
||||
bool disable_touch;
|
||||
|
||||
int irq_base;
|
||||
int gpio_base;
|
||||
int gpio_defaults[WM831X_GPIO_NUM];
|
||||
|
|
|
|||
Loading…
Reference in a new issue