From 3dde3cb49e9a7f510b3fae0694b766652ecf6b85 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Wed, 19 Aug 2020 13:29:57 +0530 Subject: [PATCH] interconnect: qcom: Add OSM L3 support on SCSHRIKE Add Operating State Manager (OSM) L3 interconnect provider support on SCSHRIKE SoCs. Change-Id: I69bd044422520601b121f260ff0cebf07d5a5220 Signed-off-by: Veera Vegivada --- drivers/interconnect/qcom/osm-l3.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index be7e2531901d..161e20fb2147 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -113,6 +113,23 @@ static const struct qcom_icc_desc sm8150_icc_osm_l3 = { .num_nodes = ARRAY_SIZE(sm8150_osm_l3_nodes), }; + +DEFINE_QNODE(mas_osm_l3_apps_scshrike, OSM_MASTER_L3_APPS, 1, + OSM_SLAVE_L3_CLUSTER0, OSM_SLAVE_L3_CLUSTER1, + OSM_SLAVE_L3_MISC, OSM_SLAVE_L3_GPU); + +static struct qcom_icc_node *scshrike_osm_l3_nodes[] = { + [MASTER_OSM_L3_APPS] = &mas_osm_l3_apps_scshrike, + [SLAVE_OSM_L3_CLUSTER0] = &slv_osm_l3_cluster0, + [SLAVE_OSM_L3_CLUSTER1] = &slv_osm_l3_cluster1, + [SLAVE_OSM_L3_MISC] = &slv_osm_l3_misc, + [SLAVE_OSM_L3_GPU] = &slv_osm_l3_gpu, +}; + +static const struct qcom_icc_desc scshrike_icc_osm_l3 = { + .nodes = scshrike_osm_l3_nodes, + .num_nodes = ARRAY_SIZE(scshrike_osm_l3_nodes), +}; static int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, u32 peak_bw, u32 *agg_avg, u32 *agg_peak) { @@ -285,6 +302,7 @@ err: static const struct of_device_id osm_l3_of_match[] = { { .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 }, { .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 }, + { .compatible = "qcom,scshrike-osm-l3", .data = &scshrike_icc_osm_l3 }, { } }; MODULE_DEVICE_TABLE(of, osm_l3_of_match);