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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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Amlogic DT updates for v4.11, round 2
- add SAR ADC driver - add ADC laddered keys to meson-gxbb-p200 board -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJYlNIUAAoJEFk3GJrT+8Zl6+YP/1U3aOeboRpqQiKucyMEU8bi GWxVAfbeIO6n9s9NMqxhBIc9fpx1sVvt8748va8xIJfQun+qrYFPvGJlK45EXfmq 3sJSf3mu6pMyjB5FZ7m7R69G60Y80TeQ9hDvbAbSvW5c7fM69lBNouXATXK7tyaT v00pRNPZZ8yDmcNnxLxKYJ5bMPS9uloHYihROTTjFF+Q2zwg6hn1Zo7j/O8Yn4sw DNoorRLBwvI/HpkDeIl4I4T3h7oNqSzBs2h4R9k6kDUP+MkguHSBkysF6QfRnCp8 MA3W+j5Rxk0neKNkXJlDry3cApwsmOjm47H68PSa2ODGo1BQhw+RtcZkdMinH7UU Lq0j/12oft1UHW+WcB5+x4d+gaVLAtNbNFIQLa/lgo/uX/6nkyKlnit74h6OoSvR hiYaRWKQwHgR7t2JzMLLVXQoadebkv8rahR0sQBInRus/s+XGC/n78VAUHNJYUKC +lykvMOokxSwJA3RtethsGmf9PEclr9LSLqenZ7GsrvYyv6ZuaLQjChN+EtMyQgt C5vRw0octczi51OBDrmiHPVOKs9ZPM9BC3bQLpKLUyiW+LDQmKZ6rVAV21Ofbm+X rPAyq6q3GXJWDty9QJzYpLZfSyWsqDwwjzzYw8RcLjyOMrnA/DU8oRa0uxzl03ZZ h2UTspCfUSPaRuAZ7vo0 =SARm -----END PGP SIGNATURE----- Merge tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/late Pull "Amlogic DT updates for v4.11, round 2" from Kevin Hilman: - add SAR ADC driver - add ADC laddered keys to meson-gxbb-p200 board * tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM64: dts: meson-gxbb-p200: add ADC laddered keys ARM64: dts: meson: meson-gx: add the SAR ADC ARM64: dts: meson-gxl: add the pwm_ao_b pin ARM64: dts: meson-gx: add the missing pwm_AO_ab node clk: gxbb: fix CLKID_ETH defined twice ARM64: dts: meson-gxl: rename Nexbox A95x for consistency clk: gxbb: add the SAR ADC clocks and expose them dt-bindings: amlogic: Add WeTek boards ARM64: dts: meson-gxbb: Add support for WeTek Hub and Play dt-bindings: vendor-prefix: Add wetek vendor prefix ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes ARM64: dts: meson-gxbb-vega-s95: Add LED ARM64: dts: meson-gx: add the serial CTS and RTS pin groups ARM64: dts: meson-gx: add the missing uart_AO_B clk: meson-gxbb: Export HDMI clocks ARM64: dts: meson-gxm: add SCPI configuration for GXM ARM64: dts: meson-gx: move the SCPI and SRAM nodes to meson-gx
This commit is contained in:
Arnd Bergmann
commit
3e011039a3
17 changed files with 523 additions and 66 deletions
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@ -564,6 +564,46 @@ static struct clk_gate gxbb_clk81 = {
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},
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};
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static struct clk_mux gxbb_sar_adc_clk_sel = {
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.reg = (void *)HHI_SAR_CLK_CNTL,
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.mask = 0x3,
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.shift = 9,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "sar_adc_clk_sel",
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.ops = &clk_mux_ops,
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/* NOTE: The datasheet doesn't list the parents for bit 10 */
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.parent_names = (const char *[]){ "xtal", "clk81", },
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.num_parents = 2,
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},
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};
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static struct clk_divider gxbb_sar_adc_clk_div = {
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.reg = (void *)HHI_SAR_CLK_CNTL,
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.shift = 0,
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.width = 8,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "sar_adc_clk_div",
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.ops = &clk_divider_ops,
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.parent_names = (const char *[]){ "sar_adc_clk_sel" },
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.num_parents = 1,
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},
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};
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static struct clk_gate gxbb_sar_adc_clk = {
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.reg = (void *)HHI_SAR_CLK_CNTL,
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.bit_idx = 8,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "sar_adc_clk",
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.ops = &clk_gate_ops,
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.parent_names = (const char *[]){ "sar_adc_clk_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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/* Everything Else (EE) domain gates */
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static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
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static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
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@ -754,6 +794,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
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[CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
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[CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
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[CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
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[CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
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[CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
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[CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
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},
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.num = NR_CLKS,
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};
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@ -856,6 +899,7 @@ static struct clk_gate *gxbb_clk_gates[] = {
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&gxbb_emmc_a,
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&gxbb_emmc_b,
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&gxbb_emmc_c,
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&gxbb_sar_adc_clk,
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};
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static int gxbb_clkc_probe(struct platform_device *pdev)
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@ -888,6 +932,10 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
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gxbb_mpeg_clk_sel.reg = clk_base + (u64)gxbb_mpeg_clk_sel.reg;
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gxbb_mpeg_clk_div.reg = clk_base + (u64)gxbb_mpeg_clk_div.reg;
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/* Populate the base address for the SAR ADC clks */
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gxbb_sar_adc_clk_sel.reg = clk_base + (u64)gxbb_sar_adc_clk_sel.reg;
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gxbb_sar_adc_clk_div.reg = clk_base + (u64)gxbb_sar_adc_clk_div.reg;
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/* Populate base address for gates */
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for (i = 0; i < ARRAY_SIZE(gxbb_clk_gates); i++)
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gxbb_clk_gates[i]->reg = clk_base +
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@ -191,7 +191,7 @@
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#define CLKID_PERIPHS 20
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#define CLKID_SPICC 21
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/* CLKID_I2C */
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#define CLKID_SAR_ADC 23
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/* #define CLKID_SAR_ADC */
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#define CLKID_SMART_CARD 24
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#define CLKID_RNG0 25
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#define CLKID_UART0 26
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@ -204,7 +204,7 @@
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#define CLKID_ASSIST_MISC 33
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/* CLKID_SPI */
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#define CLKID_I2S_SPDIF 35
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#define CLKID_ETH 36
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/* CLKID_ETH */
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#define CLKID_DEMUX 37
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#define CLKID_AIU_GLUE 38
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#define CLKID_IEC958 39
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@ -231,13 +231,13 @@
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#define CLKID_AHB_DATA_BUS 60
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#define CLKID_AHB_CTRL_BUS 61
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#define CLKID_HDMI_INTR_SYNC 62
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#define CLKID_HDMI_PCLK 63
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/* CLKID_HDMI_PCLK */
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/* CLKID_USB1_DDR_BRIDGE */
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/* CLKID_USB0_DDR_BRIDGE */
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#define CLKID_MMC_PCLK 66
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#define CLKID_DVIN 67
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#define CLKID_UART2 68
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#define CLKID_SANA 69
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/* #define CLKID_SANA */
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#define CLKID_VPU_INTR 70
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#define CLKID_SEC_AHB_AHB3_BRIDGE 71
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#define CLKID_CLK81_A53 72
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@ -245,7 +245,7 @@
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#define CLKID_VCLK2_VENCI1 74
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#define CLKID_VCLK2_VENCP0 75
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#define CLKID_VCLK2_VENCP1 76
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#define CLKID_GCLK_VENCI_INT0 77
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/* CLKID_GCLK_VENCI_INT0 */
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#define CLKID_GCLK_VENCI_INT 78
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#define CLKID_DAC_CLK 79
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#define CLKID_AOCLK_GATE 80
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@ -265,8 +265,11 @@
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/* CLKID_SD_EMMC_A */
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/* CLKID_SD_EMMC_B */
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/* CLKID_SD_EMMC_C */
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/* CLKID_SAR_ADC_CLK */
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/* CLKID_SAR_ADC_SEL */
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#define CLKID_SAR_ADC_DIV 99
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#define NR_CLKS 97
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#define NR_CLKS 100
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/* include the CLKIDs that have been made part of the stable DT binding */
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#include <dt-bindings/clock/gxbb-clkc.h>
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