From 3e06d3c4f2625ddb02fed8032fbc25a7f01311f2 Mon Sep 17 00:00:00 2001 From: Yimin Peng Date: Tue, 5 Jan 2021 17:02:57 +0800 Subject: [PATCH] clk: qcom: Add USB2 virtio clocks for sa8195p These virtio clocks are necessary for USB2 pass-through on sa8195p virtual machine. Change-Id: Ieef15c9ee8652ff2b182cc08f5d6ac7b3738c1a1 Signed-off-by: Yimin Peng --- drivers/clk/qcom/virtio_clk_sa8195p.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/clk/qcom/virtio_clk_sa8195p.c b/drivers/clk/qcom/virtio_clk_sa8195p.c index b1010e99fc2f..4987bbb4f9e4 100644 --- a/drivers/clk/qcom/virtio_clk_sa8195p.c +++ b/drivers/clk/qcom/virtio_clk_sa8195p.c @@ -53,6 +53,15 @@ static const char * const sa8195p_gcc_virtio_clocks[] = { [GCC_USB3_SEC_PHY_PIPE_CLK] = "gcc_usb3_sec_phy_pipe_clk", [GCC_USB3_SEC_CLKREF_CLK] = "gcc_usb3_sec_clkref_en", [GCC_USB3_SEC_PHY_COM_AUX_CLK] = "gcc_usb3_sec_phy_com_aux_clk", + [GCC_USB30_MP_MASTER_CLK] = "gcc_usb30_mp_master_clk", + [GCC_CFG_NOC_USB3_MP_AXI_CLK] = "gcc_cfg_noc_usb3_mp_axi_clk", + [GCC_AGGRE_USB3_MP_AXI_CLK] = "gcc_aggre_usb3_mp_axi_clk", + [GCC_USB30_MP_MOCK_UTMI_CLK] = "gcc_usb30_mp_mock_utmi_clk", + [GCC_USB30_MP_SLEEP_CLK] = "gcc_usb30_mp_sleep_clk", + [GCC_USB3_MP_PHY_AUX_CLK] = "gcc_usb3_mp_phy_aux_clk", + [GCC_USB3_MP_PHY_PIPE_0_CLK] = "gcc_usb3_mp_phy_pipe_0_clk", + [GCC_USB3_MP_PHY_COM_AUX_CLK] = "gcc_usb3_mp_phy_com_aux_clk", + [GCC_USB3_MP_PHY_PIPE_1_CLK] = "gcc_usb3_mp_phy_pipe_1_clk", [GCC_PCIE_0_PIPE_CLK] = "gcc_pcie_0_pipe_clk", [GCC_PCIE_0_AUX_CLK] = "gcc_pcie_0_aux_clk", [GCC_PCIE_0_CFG_AHB_CLK] = "gcc_pcie_0_cfg_ahb_clk", @@ -105,8 +114,15 @@ static const char * const sa8195p_gcc_virtio_clocks[] = { static const char * const sa8195p_gcc_virtio_resets[] = { [GCC_QUSB2PHY_PRIM_BCR] = "gcc_qusb2phy_prim_bcr", [GCC_QUSB2PHY_SEC_BCR] = "gcc_qusb2phy_sec_bcr", + [GCC_QUSB2PHY_MP0_BCR] = "gcc_qusb2phy_mp0_bcr", + [GCC_QUSB2PHY_MP1_BCR] = "gcc_qusb2phy_mp1_bcr", [GCC_USB30_PRIM_BCR] = "gcc_usb30_prim_master_clk", [GCC_USB30_SEC_BCR] = "gcc_usb30_sec_master_clk", + [GCC_USB30_MP_BCR] = "gcc_usb30_mp_master_clk", + [GCC_USB3_UNIPHY_MP0_BCR] = "gcc_usb3_uniphy_mp0_bcr", + [GCC_USB3UNIPHY_PHY_MP0_BCR] = "gcc_usb3uniphy_phy_mp0_bcr", + [GCC_USB3_UNIPHY_MP1_BCR] = "gcc_usb3_uniphy_mp1_bcr", + [GCC_USB3UNIPHY_PHY_MP1_BCR] = "gcc_usb3uniphy_phy_mp1_bcr", [GCC_PCIE_0_BCR] = "gcc_pcie_0_mstr_axi_clk", [GCC_PCIE_0_PHY_BCR] = "gcc_pcie_0_phy_bcr", [GCC_PCIE_1_BCR] = "gcc_pcie_1_mstr_axi_clk",