mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-14 08:36:12 -04:00
ARM: dts: msm: Add CNSS2 node for shima
Add CNSS2 device tree entry for shima. Change-Id: I2518f6af5e071263131e01549f3d79eb9dade3ca
This commit is contained in:
Mohammed Siddiq
parent
dc16988518
commit
3e3dc7be79
2 changed files with 202 additions and 0 deletions
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@ -2916,6 +2916,36 @@
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};
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};
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};
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cnss_pins {
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cnss_wlan_en_active: cnss_wlan_en_active {
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mux {
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pins = "gpio64";
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function = "gpio";
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};
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config {
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pins = "gpio64";
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drive-strength = <16>;
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output-high;
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bias-pull-up;
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};
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};
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cnss_wlan_en_sleep: cnss_wlan_en_sleep {
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mux {
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pins = "gpio64";
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function = "gpio";
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};
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config {
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pins = "gpio64";
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drive-strength = <2>;
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output-low;
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bias-pull-down;
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};
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};
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};
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};
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};
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172
qcom/shima.dtsi
172
qcom/shima.dtsi
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@ -341,6 +341,14 @@
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size = <0 0xA000000>;
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};
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cnss_wlan_mem: cnss_wlan_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1400000>;
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};
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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compatible = "shared-dma-pool";
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@ -2296,6 +2304,148 @@
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bits = <5 1>;
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};
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};
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wlan: qcom,cnss-qca6490@b0000000 {
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status = "disabled";
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compatible = "qcom,cnss-qca6490";
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reg = <0xb0000000 0x10000>;
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reg-names = "smmu_iova_ipa";
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wlan-en-gpio = <&tlmm 64 0>;
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pinctrl-names = "wlan_en_active", "wlan_en_sleep";
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pinctrl-0 = <&cnss_wlan_en_active>;
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pinctrl-1 = <&cnss_wlan_en_sleep>;
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qcom,wlan-rc-num = <0>;
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qcom,wlan-ramdump-dynamic = <0x420000>;
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qcom,wlan-cbc-enabled;
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vdd-wlan-aon-supply = <&S2C>;
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qcom,vdd-wlan-aon-config = <950000 952000 0 0 1>;
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vdd-wlan-dig-supply = <&S2C>;
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qcom,vdd-wlan-dig-config = <950000 952000 0 0 1>;
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vdd-wlan-io-supply = <&S10B>;
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qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>;
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vdd-wlan-rfa1-supply = <&S11B>;
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qcom,vdd-wlan-rfa1-config = <1880000 1880000 0 0 1>;
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vdd-wlan-rfa2-supply = <&S12B>;
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qcom,vdd-wlan-rfa2-config = <1350000 1350000 0 0 1>;
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wlan-ant-switch-supply = <&L11C>;
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qcom,wlan-ant-switch-config = <2800000 2800000 0 0 0>;
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mhi,max-channels = <30>;
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mhi,timeout = <10000>;
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mhi,buffer-len = <0x8000>;
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mhi,m2-no-db-access;
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mhi_channels {
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#address-cells = <1>;
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#size-cells = <0>;
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mhi_chan@0 {
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reg = <0>;
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label = "LOOPBACK";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <1>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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};
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mhi_chan@1 {
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reg = <1>;
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label = "LOOPBACK";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <2>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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};
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mhi_chan@4 {
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reg = <4>;
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label = "DIAG";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <1>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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};
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mhi_chan@5 {
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reg = <5>;
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label = "DIAG";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <2>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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};
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mhi_chan@20 {
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reg = <20>;
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label = "IPCR";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <1>;
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mhi,data-type = <1>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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mhi,auto-start;
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};
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mhi_chan@21 {
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reg = <21>;
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label = "IPCR";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <2>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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mhi,auto-queue;
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mhi,auto-start;
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};
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};
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mhi_events {
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mhi_event@0 {
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mhi,num-elements = <32>;
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mhi,intmod = <0>;
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mhi,msi = <1>;
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mhi,priority = <1>;
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mhi,brstmode = <2>;
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mhi,data-type = <1>;
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};
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mhi_event@1 {
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mhi,num-elements = <256>;
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mhi,intmod = <0>;
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mhi,msi = <2>;
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mhi,priority = <1>;
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mhi,brstmode = <2>;
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};
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mhi_event@2 {
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mhi,num-elements = <32>;
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mhi,intmod = <0>;
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mhi,msi = <0>;
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mhi,priority = <2>;
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mhi,brstmode = <2>;
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mhi,data-type = <3>;
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};
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};
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mhi_devices {
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mhi_qrtr {
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mhi,chan = "IPCR";
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qcom,net-id = <0>;
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qcom,low-latency;
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};
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};
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};
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};
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#include "shima-pinctrl.dtsi"
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@ -2314,6 +2464,28 @@
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#include "shima-gpu.dtsi"
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#include "shima-audio.dtsi"
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&pcie0_rp {
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#address-cells = <5>;
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#size-cells = <0>;
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cnss_pci: cnss_pci {
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reg = <0 0 0 0 0>;
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qcom,iommu-group = <&cnss_pci_iommu_group>;
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memory-region = <&cnss_wlan_mem>;
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#address-cells = <1>;
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#size-cells = <1>;
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cnss_pci_iommu_group: cnss_pci_iommu_group {
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qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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qcom,iommu-pagetable = "coherent";
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qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE",
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"non-fatal";
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};
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};
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};
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&gcc_pcie_0_gdsc {
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status = "ok"
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};
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