A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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Merge branch 'next/arm64' into next/dt

Browse source 
Merging in the few patches I had kept separate from main next/dt, since others
got merged here directly.

* next/arm64:
  arm64: defconfig: Enable PCI generic host bridge by default
  arm64: Juno: Add support for the PCIe host bridge on Juno R1
  Documentation: of: Document the bindings used by Juno R1 PCIe host bridge
  arm64: dts: mt8173: Add clocks for SCPSYS unit
  arm64: dts: mt8173: Add subsystem clock controller device nodes
  + Linux 4.3-rc5
This commit is contained in:
Olof Johansson 2015-11-09 16:35:19 -08:00
commit 3e4dda70cc
150 changed files with 938 additions and 394 deletions
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1
arch/arm/boot/dts/exynos5250-smdk5250.dts
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@ -197,6 +197,7 @@
regulator-name = "P1.8V_LDO_OUT10";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo11_reg: LDO11 {

2
arch/arm/boot/dts/exynos5420.dtsi
View file

@ -1117,7 +1117,7 @@
interrupt-parent = <&combiner>;
interrupts = <3 0>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
power-domains = <&disp_pd>;
#iommu-cells = <0>;
};

2
arch/arm/boot/dts/imx53-qsrb.dts
View file

@ -36,7 +36,7 @@
pinctrl-0 = <&pinctrl_pmic>;
reg = <0x08>;
interrupt-parent = <&gpio5>;
interrupts = <23 0x8>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
regulators {
sw1_reg: sw1a {
regulator-name = "SW1";

1
arch/arm/boot/dts/imx53.dtsi
View file

@ -15,6 +15,7 @@
#include <dt-bindings/clock/imx5-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
aliases {

2
arch/arm/boot/dts/imx6qdl-rex.dtsi
View file

@ -35,7 +35,6 @@
compatible = "regulator-fixed";
reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
regulator-name = "usbh1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@ -47,7 +46,6 @@
compatible = "regulator-fixed";
reg = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;

1
arch/arm/boot/dts/r8a7790.dtsi
View file

@ -1627,6 +1627,7 @@
"mix.0", "mix.1",
"dvc.0", "dvc.1",
"clk_a", "clk_b", "clk_c", "clk_i";
power-domains = <&cpg_clocks>;
status = "disabled";

1
arch/arm/boot/dts/r8a7791.dtsi
View file

@ -1677,6 +1677,7 @@
"mix.0", "mix.1",
"dvc.0", "dvc.1",
"clk_a", "clk_b", "clk_c", "clk_i";
power-domains = <&cpg_clocks>;
status = "disabled";

27
arch/arm/mach-exynos/mcpm-exynos.c
View file

@ -20,6 +20,7 @@
#include <asm/cputype.h>
#include <asm/cp15.h>
#include <asm/mcpm.h>
#include <asm/smp_plat.h>
#include "regs-pmu.h"
#include "common.h"
@ -70,7 +71,31 @@ static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster)
cluster >= EXYNOS5420_NR_CLUSTERS)
return -EINVAL;
exynos_cpu_power_up(cpunr);
if (!exynos_cpu_power_state(cpunr)) {
exynos_cpu_power_up(cpunr);
/*
* This assumes the cluster number of the big cores(Cortex A15)
* is 0 and the Little cores(Cortex A7) is 1.
* When the system was booted from the Little core,
* they should be reset during power up cpu.
*/
if (cluster &&
cluster == MPIDR_AFFINITY_LEVEL(cpu_logical_map(0), 1)) {
/*
* Before we reset the Little cores, we should wait
* the SPARE2 register is set to 1 because the init
* codes of the iROM will set the register after
* initialization.
*/
while (!pmu_raw_readl(S5P_PMU_SPARE2))
udelay(10);
pmu_raw_writel(EXYNOS5420_KFC_CORE_RESET(cpu),
EXYNOS_SWRESET);
}
}
return 0;
}

6
arch/arm/mach-exynos/regs-pmu.h
View file

@ -513,6 +513,12 @@ static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
#define SPREAD_ENABLE 0xF
#define SPREAD_USE_STANDWFI 0xF
#define EXYNOS5420_KFC_CORE_RESET0 BIT(8)
#define EXYNOS5420_KFC_ETM_RESET0 BIT(20)
#define EXYNOS5420_KFC_CORE_RESET(_nr) \
((EXYNOS5420_KFC_CORE_RESET0 | EXYNOS5420_KFC_ETM_RESET0) << (_nr))
#define EXYNOS5420_BB_CON1 0x0784
#define EXYNOS5420_BB_SEL_EN BIT(31)
#define EXYNOS5420_BB_PMOS_EN BIT(7)