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usb: phy: Reset and initialize HSPHY in host mode when EUD is enable
EUD HUB functionality is relevant into USB device mode only. Hence when using USB host mode, continue performing reset and initialization functionality with HSPHY even though EUD is enable. If EUD is enable while starting host mode, re-enable EUD whie exiting host mode. Change-Id: Ifc2a105d8a02511dd2fc58be5fbc788d46546ba0 Signed-off-by: Mayank Rana <mrana@codeaurora.org>
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732a1ae2a0
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2 changed files with 31 additions and 10 deletions
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@ -4582,11 +4582,11 @@ static int dwc3_otg_start_host(struct dwc3_msm *mdwc, int on)
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if (on) {
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dev_dbg(mdwc->dev, "%s: turn on host\n", __func__);
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mdwc->hs_phy->flags |= PHY_HOST_MODE;
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dbg_event(0xFF, "hs_phy_flag:%x", mdwc->hs_phy->flags);
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pm_runtime_get_sync(mdwc->dev);
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dbg_event(0xFF, "StrtHost gync",
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atomic_read(&mdwc->dev->power.usage_count));
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mdwc->hs_phy->flags |= PHY_HOST_MODE;
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if (dwc->maximum_speed >= USB_SPEED_SUPER) {
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mdwc->ss_phy->flags |= PHY_HOST_MODE;
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usb_phy_notify_connect(mdwc->ss_phy,
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@ -21,6 +21,8 @@
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#include <linux/usb/dwc3-msm.h>
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#include <linux/reset.h>
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#include <linux/debugfs.h>
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#include <linux/qcom_scm.h>
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#include <linux/types.h>
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#define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c)
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#define OPMODE_MASK (0x3 << 3)
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@ -82,7 +84,9 @@
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struct msm_hsphy {
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struct usb_phy phy;
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void __iomem *base;
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phys_addr_t eud_reg;
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void __iomem *eud_enable_reg;
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bool re_enable_eud;
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struct clk *ref_clk_src;
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struct clk *cfg_ahb_clk;
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@ -331,18 +335,28 @@ static void hsusb_phy_write_seq(void __iomem *base, u32 *seq, int cnt,
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}
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}
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#define EUD_EN2 BIT(0)
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static int msm_hsphy_init(struct usb_phy *uphy)
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{
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struct msm_hsphy *phy = container_of(uphy, struct msm_hsphy, phy);
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int ret;
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u32 rcal_code = 0;
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u32 rcal_code = 0, eud_csr_reg = 0;
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dev_dbg(uphy->dev, "%s\n", __func__);
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if (phy->eud_enable_reg && readl_relaxed(phy->eud_enable_reg)) {
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dev_err(phy->phy.dev, "eud is enabled\n");
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ret = msm_hsphy_enable_power(phy, true);
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return ret;
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dev_dbg(uphy->dev, "%s phy_flags:0x%x\n", __func__, phy->phy.flags);
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if (phy->eud_enable_reg) {
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eud_csr_reg = readl_relaxed(phy->eud_enable_reg);
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if (eud_csr_reg & EUD_EN2) {
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dev_dbg(phy->phy.dev, "csr:0x%x eud is enabled\n",
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eud_csr_reg);
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/* if in host mode, disable EUD */
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if (phy->phy.flags & PHY_HOST_MODE) {
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qcom_scm_io_writel(phy->eud_reg, 0x0);
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phy->re_enable_eud = true;
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} else {
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ret = msm_hsphy_enable_power(phy, true);
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return ret;
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}
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}
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}
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ret = msm_hsphy_enable_power(phy, true);
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@ -486,6 +500,12 @@ suspend:
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} else {/* Cable disconnect */
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mutex_lock(&phy->phy_lock);
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dev_dbg(uphy->dev, "phy->flags:0x%x\n", phy->phy.flags);
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if (phy->re_enable_eud) {
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dev_dbg(uphy->dev, "re-enabling EUD\n");
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qcom_scm_io_writel(phy->eud_reg, 0x1);
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phy->re_enable_eud = false;
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}
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if (!phy->dpdm_enable) {
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if (!(phy->phy.flags & EUD_SPOOF_DISCONNECT)) {
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dev_dbg(uphy->dev, "turning off clocks/ldo\n");
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@ -703,6 +723,7 @@ static int msm_hsphy_probe(struct platform_device *pdev)
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dev_err(dev, "err getting eud_enable_reg address\n");
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return PTR_ERR(phy->eud_enable_reg);
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}
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phy->eud_reg = res->start;
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}
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/* ref_clk_src is needed irrespective of SE_CLK or DIFF_CLK usage */
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