From 3e5d5f6b7701b8b3b352b8454977fc29a899fee1 Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Fri, 12 Jun 2020 12:30:15 -0700 Subject: [PATCH] pci: controller: msm: Poll for L0s state when disallowing L1 If L0s link state is enabled, API to disallow L1 also needs to poll for L0s while checking for L0. It is possible that link goes to L0s from L0 by the time LTSSM state is checked again. Change-Id: Ib614860dad8c92a55f993cdb1c38bf8ebfca17a2 Signed-off-by: Hemant Kumar --- drivers/pci/controller/pci-msm.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pci-msm.c b/drivers/pci/controller/pci-msm.c index bd3c94137c33..ce3edb01f0c3 100644 --- a/drivers/pci/controller/pci-msm.c +++ b/drivers/pci/controller/pci-msm.c @@ -2274,6 +2274,19 @@ static int msm_pcie_is_link_up(struct msm_pcie_dev_t *dev) PCIE20_CAP_LINKCTRLSTATUS) & BIT(29); } +static bool msm_pcie_check_ltssm_state(struct msm_pcie_dev_t *dev, u32 state) +{ + u32 ltssm; + + ltssm = readl_relaxed(dev->parf + PCIE20_PARF_LTSSM) & + MSM_PCIE_LTSSM_MASK; + + if (ltssm == state) + return true; + + return false; +} + /** * msm_pcie_iatu_config - configure outbound address translation region * @dev: root commpex @@ -5768,9 +5781,9 @@ int msm_pcie_prevent_l1(struct pci_dev *pci_dev) PCI_EXP_LNKCTL_ASPM_L1, 0); msm_pcie_write_mask(pcie_dev->parf + PCIE20_PARF_PM_CTRL, 0, BIT(5)); - /* confirm link is in L0 */ - while (((readl_relaxed(pcie_dev->parf + PCIE20_PARF_LTSSM) & - MSM_PCIE_LTSSM_MASK)) != MSM_PCIE_LTSSM_L0) { + /* confirm link is in L0/L0s */ + while (!msm_pcie_check_ltssm_state(pcie_dev, MSM_PCIE_LTSSM_L0) && + !msm_pcie_check_ltssm_state(pcie_dev, MSM_PCIE_LTSSM_L0S)) { if (unlikely(cnt++ >= cnt_max)) { PCIE_ERR(pcie_dev, "PCIe: RC%d: %02x:%02x.%01x: failed to transition to L0\n",