diff --git a/drivers/thermal/qcom/qmi_cooling.c b/drivers/thermal/qcom/qmi_cooling.c
index adf68228b7f5..8637ae0a8d1e 100644
--- a/drivers/thermal/qcom/qmi_cooling.c
+++ b/drivers/thermal/qcom/qmi_cooling.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  */
 
 #define pr_fmt(fmt) "%s:%s " fmt, KBUILD_MODNAME, __func__
@@ -76,7 +76,26 @@ static char  device_clients[][QMI_CLIENT_NAME_LENGTH] = {
 	{"cdsp_sw"},
 	{"cdsp_hw"},
 	{"cpuv_restriction_cold"},
-	{"cpr_cold"}
+	{"cpr_cold"},
+	{"modem_lte_dsc"},
+	{"modem_nr_dsc"},
+	{"modem_nr_scg_dsc"},
+	{"sdr0_lte_dsc"},
+	{"sdr1_lte_dsc"},
+	{"sdr0_nr_dsc"},
+	{"sdr1_nr_dsc"},
+	{"pa_sdr0_dsc"},
+	{"pa_sdr1_dsc"},
+	{"pa_fr1_sdr0_dsc"},
+	{"pa_fr1_sdr1_dsc"},
+	{"pa_fr1_sdr0_scg_dsc"},
+	{"pa_fr1_sdr1_scg_dsc"},
+	{"mmw0_dsc"},
+	{"mmw1_dsc"},
+	{"mmw2_dsc"},
+	{"mmw3_dsc"},
+	{"mmw_ul_throttling_dsc"},
+	{"mmw_ific_dsc"},
 };
 
 static int qmi_get_max_state(struct thermal_cooling_device *cdev,
diff --git a/include/dt-bindings/thermal/thermal_qti.h b/include/dt-bindings/thermal/thermal_qti.h
index 6ae6ce40aef8..8ff38dc176f2 100644
--- a/include/dt-bindings/thermal/thermal_qti.h
+++ b/include/dt-bindings/thermal/thermal_qti.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/* Copyright (c) 2020, The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */
 
 #include <dt-bindings/thermal/thermal.h>
 
@@ -41,7 +41,7 @@
 #define QMI_MMW_PA2		27
 #define QMI_MMW_PA3		28
 #define QMI_SDR_MMW		29
-#define QMI_MSM_SKIN	30
+#define QMI_MSM_SKIN		30
 #define QMI_BEAMER_N_THERM	31
 #define QMI_BEAMER_E_THERM	32
 #define QMI_BEAMER_W_THERM	33
@@ -51,6 +51,27 @@
 #define QMI_QFE_WTR_PA2_FR1	37
 #define QMI_QFE_WTR_PA3_FR1	38
 #define QMI_QFE_WTR0_FR1	39
+#define QMI_QTM_THERM		40
+#define QMI_BCL_WARN		41
+#define QMI_SDR0_PA0		42
+#define QMI_SDR0_PA1		43
+#define QMI_SDR0_PA2		44
+#define QMI_SDR0_PA3		45
+#define QMI_SDR0_PA4		46
+#define QMI_SDR0_PA5		47
+#define QMI_SDR0		48
+#define QMI_SDR1_PA0		49
+#define QMI_SDR1_PA1		50
+#define QMI_SDR1_PA2		51
+#define QMI_SDR1_PA3		52
+#define QMI_SDR1_PA4		53
+#define QMI_SDR1_PA5		54
+#define QMI_SDR1		55
+#define QMI_MMW0		56
+#define QMI_MMW1		57
+#define QMI_MMW2		58
+#define QMI_MMW3		59
+#define QMI_MMW_IFIC0		60
 
 #define QMI_MODEM_INST_ID	0x0
 #define QMI_ADSP_INST_ID	0x1