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Merge "serial: msm_geni_serial: Set clock freq correctly for RUMI"

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This commit is contained in:
qctecmdr 2020-03-04 00:26:50 -08:00 • committed by Gerrit - the friendly Code Review server
commit 3f59866d28
1 changed files with 28 additions and 0 deletions
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28
drivers/tty/serial/msm_geni_serial.c
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@ -172,6 +172,7 @@ struct msm_geni_serial_port {
u32 cur_tx_remaining;
bool startup_in_progress;
bool is_console;
bool rumi_platform;
};
static const struct uart_ops msm_geni_serial_pops;
@ -1983,6 +1984,14 @@ static void msm_geni_serial_set_termios(struct uart_port *uport,
unsigned long clk_rate;
unsigned long flags;
/* QUP_2.5.0 and older RUMI has sampling rate as 32 */
if (IS_ENABLED(CONFIG_SERIAL_MSM_GENI_HALF_SAMPLING) &&
port->rumi_platform && port->is_console) {
geni_write_reg_nolog(0x21, uport->membase, GENI_SER_M_CLK_CFG);
geni_write_reg_nolog(0x21, uport->membase, GENI_SER_S_CLK_CFG);
geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG);
}
if (!uart_console(uport)) {
int ret = msm_geni_serial_power_on(uport);
@ -2321,6 +2330,13 @@ msm_geni_serial_earlycon_setup(struct earlycon_device *dev,
*/
msm_geni_serial_poll_cancel_tx(uport);
if (IS_ENABLED(CONFIG_SERIAL_MSM_GENI_HALF_SAMPLING)) {
/* Only for earlyconsole */
geni_write_reg_nolog(0x21, uport->membase, GENI_SER_M_CLK_CFG);
geni_write_reg_nolog(0x21, uport->membase, GENI_SER_S_CLK_CFG);
geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG);
}
se_get_packing_config(8, 1, false, &cfg0, &cfg1);
geni_se_init(uport->membase, (DEF_FIFO_DEPTH_WORDS >> 1),
(DEF_FIFO_DEPTH_WORDS - 2));
@ -2637,6 +2653,10 @@ static int msm_geni_serial_probe(struct platform_device *pdev)
dev_port->serial_rsc.ctrl_dev = &pdev->dev;
dev_port->is_console = is_console;
/* RUMI specific */
dev_port->rumi_platform = of_property_read_bool(pdev->dev.of_node,
"qcom,rumi_platform");
if (of_property_read_u32(pdev->dev.of_node, "qcom,wakeup-byte",
&wake_char)) {
dev_dbg(&pdev->dev, "No Wakeup byte specified\n");
@ -2769,6 +2789,14 @@ static int msm_geni_serial_probe(struct platform_device *pdev)
pm_runtime_enable(&pdev->dev);
}
if (IS_ENABLED(CONFIG_SERIAL_MSM_GENI_HALF_SAMPLING) &&
dev_port->rumi_platform && dev_port->is_console) {
/* No ver info available, if do later then RUMI console fails */
geni_write_reg_nolog(0x21, uport->membase, GENI_SER_M_CLK_CFG);
geni_write_reg_nolog(0x21, uport->membase, GENI_SER_S_CLK_CFG);
geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG);
}
dev_info(&pdev->dev, "Serial port%d added.FifoSize %d is_console%d\n",
line, uport->fifosize, is_console);
device_create_file(uport->dev, &dev_attr_loopback);