mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-13 00:00:00 -04:00
Merge "clk: qcom: debugcc-shima: Remove measure support for unregistered clocks"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
3f83f41dfe
1 changed files with 77 additions and 24 deletions
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@ -289,7 +289,6 @@ static struct clk_debug_mux disp_cc_debug_mux = {
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static const char *const gcc_debug_mux_parent_names[] = {
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"apss_cc_debug_mux",
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"cam_cc_debug_mux",
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"core_bi_pll_test_se",
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"disp_cc_debug_mux",
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"gcc_aggre_noc_pcie_0_axi_clk",
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"gcc_aggre_noc_pcie_1_axi_clk",
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@ -300,7 +299,6 @@ static const char *const gcc_debug_mux_parent_names[] = {
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"gcc_camera_sf_axi_clk",
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"gcc_camera_xo_clk",
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"gcc_cfg_noc_usb3_prim_axi_clk",
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"gcc_cpuss_ahb_clk",
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"gcc_ddrss_gpu_axi_clk",
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"gcc_disp_ahb_clk",
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"gcc_disp_gpll0_clk_src",
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@ -355,13 +353,10 @@ static const char *const gcc_debug_mux_parent_names[] = {
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"gcc_qupv3_wrap1_s2_clk",
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"gcc_qupv3_wrap1_s3_clk",
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"gcc_qupv3_wrap1_s4_clk",
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"gcc_qupv3_wrap1_s5_clk",
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"gcc_qupv3_wrap1_s6_clk",
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"gcc_qupv3_wrap1_s7_clk",
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"gcc_qupv3_wrap_0_m_ahb_clk",
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"gcc_qupv3_wrap_0_s_ahb_clk",
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"gcc_qupv3_wrap_1_m_ahb_clk",
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"gcc_qupv3_wrap_1_s_ahb_clk",
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"gcc_sdcc1_ahb_clk",
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"gcc_sdcc1_apps_clk",
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"gcc_sdcc1_ice_core_clk",
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@ -369,7 +364,6 @@ static const char *const gcc_debug_mux_parent_names[] = {
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"gcc_sdcc2_apps_clk",
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"gcc_sdcc4_ahb_clk",
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"gcc_sdcc4_apps_clk",
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"gcc_sys_noc_cpuss_ahb_clk",
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"gcc_throttle_pcie_ahb_clk",
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"gcc_titan_nrt_throttle_core_clk",
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"gcc_titan_rt_throttle_core_clk",
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@ -396,22 +390,22 @@ static const char *const gcc_debug_mux_parent_names[] = {
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"gpu_cc_debug_mux",
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"mc_cc_debug_mux",
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"measure_only_cnoc_clk",
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"measure_only_core_bi_pll_test_se",
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"measure_only_ipa_2x_clk",
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"measure_only_memnoc_clk",
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"measure_only_pcie_0_pipe_clk",
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"measure_only_pcie_1_pipe_clk",
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"measure_only_snoc_clk",
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"pcie_0_pipe_clk",
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"pcie_1_pipe_clk",
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"ufs_phy_rx_symbol_0_clk",
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"ufs_phy_rx_symbol_1_clk",
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"ufs_phy_tx_symbol_0_clk",
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"usb3_phy_wrapper_gcc_usb30_pipe_clk",
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"measure_only_ufs_phy_rx_symbol_0_clk",
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"measure_only_ufs_phy_rx_symbol_1_clk",
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"measure_only_ufs_phy_tx_symbol_0_clk",
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"measure_only_usb3_phy_wrapper_gcc_usb30_pipe_clk",
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"video_cc_debug_mux",
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};
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static int gcc_debug_mux_sels[] = {
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0xE3, /* apss_cc_debug_mux */
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0x4D, /* cam_cc_debug_mux */
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0x5, /* core_bi_pll_test_se */
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0x53, /* disp_cc_debug_mux */
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0x122, /* gcc_aggre_noc_pcie_0_axi_clk */
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0x123, /* gcc_aggre_noc_pcie_1_axi_clk */
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@ -422,7 +416,6 @@ static int gcc_debug_mux_sels[] = {
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0x4A, /* gcc_camera_sf_axi_clk */
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0x4C, /* gcc_camera_xo_clk */
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0x1B, /* gcc_cfg_noc_usb3_prim_axi_clk */
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0xDE, /* gcc_cpuss_ahb_clk */
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0xC3, /* gcc_ddrss_gpu_axi_clk */
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0x4E, /* gcc_disp_ahb_clk */
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0x44, /* gcc_disp_gpll0_clk_src */
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@ -477,13 +470,10 @@ static int gcc_debug_mux_sels[] = {
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0x92, /* gcc_qupv3_wrap1_s2_clk */
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0x93, /* gcc_qupv3_wrap1_s3_clk */
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0x94, /* gcc_qupv3_wrap1_s4_clk */
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0x95, /* gcc_qupv3_wrap1_s5_clk */
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0x96, /* gcc_qupv3_wrap1_s6_clk */
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0x97, /* gcc_qupv3_wrap1_s7_clk */
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0x80, /* gcc_qupv3_wrap_0_m_ahb_clk */
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0x81, /* gcc_qupv3_wrap_0_s_ahb_clk */
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0x8C, /* gcc_qupv3_wrap_1_m_ahb_clk */
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0x8D, /* gcc_qupv3_wrap_1_s_ahb_clk */
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0x153, /* gcc_sdcc1_ahb_clk */
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0x154, /* gcc_sdcc1_apps_clk */
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0x155, /* gcc_sdcc1_ice_core_clk */
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@ -491,7 +481,6 @@ static int gcc_debug_mux_sels[] = {
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0x7C, /* gcc_sdcc2_apps_clk */
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0x7F, /* gcc_sdcc4_ahb_clk */
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0x7E, /* gcc_sdcc4_apps_clk */
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0xA, /* gcc_sys_noc_cpuss_ahb_clk */
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0x39, /* gcc_throttle_pcie_ahb_clk */
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0x4B, /* gcc_titan_nrt_throttle_core_clk */
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0x49, /* gcc_titan_rt_throttle_core_clk */
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@ -518,15 +507,16 @@ static int gcc_debug_mux_sels[] = {
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0x13C, /* gpu_cc_debug_mux */
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0xCD, /* mc_cc_debug_mux or ddrss_gcc_debug_clk */
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0x17, /* measure_only_cnoc_clk */
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0x5, /* measure_only_core_bi_pll_test_se */
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0x128, /* measure_only_ipa_2x_clk */
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0xC9, /* measure_only_memnoc_clk */
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0xF8, /* measure_only_pcie_0_pipe_clk */
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0x101, /* measure_only_pcie_1_pipe_clk */
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0x9, /* measure_only_snoc_clk */
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0xF8, /* pcie_0_pipe_clk */
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0x101, /* pcie_1_pipe_clk */
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0x108, /* ufs_phy_rx_symbol_0_clk */
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0x10D, /* ufs_phy_rx_symbol_1_clk */
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0x107, /* ufs_phy_tx_symbol_0_clk */
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0x78, /* usb3_phy_wrapper_gcc_usb30_pipe_clk */
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0x108, /* measure_only_ufs_phy_rx_symbol_0_clk */
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0x10D, /* measure_only_ufs_phy_rx_symbol_1_clk */
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0x107, /* measure_only_ufs_phy_tx_symbol_0_clk */
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0x78, /* measure_only_usb3_phy_wrapper_gcc_usb30_pipe_clk */
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0x5C, /* video_cc_debug_mux */
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};
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@ -715,6 +705,14 @@ static struct clk_dummy measure_only_cnoc_clk = {
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},
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};
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static struct clk_dummy measure_only_core_bi_pll_test_se = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_core_bi_pll_test_se",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gpu_cc_cb_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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@ -771,6 +769,22 @@ static struct clk_dummy measure_only_memnoc_clk = {
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},
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};
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static struct clk_dummy measure_only_pcie_0_pipe_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_pcie_0_pipe_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_pcie_1_pipe_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_pcie_1_pipe_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_snoc_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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@ -779,12 +793,45 @@ static struct clk_dummy measure_only_snoc_clk = {
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},
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};
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static struct clk_dummy measure_only_ufs_phy_rx_symbol_0_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_ufs_phy_rx_symbol_0_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_ufs_phy_rx_symbol_1_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_ufs_phy_rx_symbol_1_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_ufs_phy_tx_symbol_0_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_ufs_phy_tx_symbol_0_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_usb3_phy_wrapper_gcc_usb30_pipe_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_usb3_phy_wrapper_gcc_usb30_pipe_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_hw *debugcc_shima_hws[] = {
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&measure_only_apcs_gold_post_acd_clk.hw,
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&measure_only_apcs_goldplus_post_acd_clk.hw,
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&measure_only_apcs_l3_post_acd_clk.hw,
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&measure_only_apcs_silver_post_acd_clk.hw,
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&measure_only_cnoc_clk.hw,
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&measure_only_core_bi_pll_test_se.hw,
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&measure_only_gpu_cc_cb_clk.hw,
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&measure_only_gpu_cc_cx_gfx3d_clk.hw,
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&measure_only_gpu_cc_cx_gfx3d_slv_clk.hw,
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@ -792,7 +839,13 @@ static struct clk_hw *debugcc_shima_hws[] = {
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&measure_only_mccc_clk.hw,
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&measure_only_ipa_2x_clk.hw,
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&measure_only_memnoc_clk.hw,
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&measure_only_pcie_0_pipe_clk.hw,
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&measure_only_pcie_1_pipe_clk.hw,
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&measure_only_snoc_clk.hw,
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&measure_only_ufs_phy_rx_symbol_0_clk.hw,
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&measure_only_ufs_phy_rx_symbol_1_clk.hw,
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&measure_only_ufs_phy_tx_symbol_0_clk.hw,
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&measure_only_usb3_phy_wrapper_gcc_usb30_pipe_clk.hw,
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};
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static const struct of_device_id clk_debug_match_table[] = {
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