From ef808f2559fce97b6a17a7fb29f9d2c9a9d203be Mon Sep 17 00:00:00 2001
From: Mohammed Siddiq <msiddiq@qti.qualcomm.com>
Date: Mon, 7 Sep 2020 11:57:54 +0530
Subject: [PATCH] ARM: dts: msm: Update cnss dt node for bus bandwidth for
 shima

Configure bandwidth vote data for individual platform
interconnect paths.

Change-Id: Ic8d97324109e31092169a06ab0e690ac61eccc92
---
 qcom/shima.dtsi | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi
index 4170db3da48b..b418926e5ee7 100644
--- a/qcom/shima.dtsi
+++ b/qcom/shima.dtsi
@@ -3398,6 +3398,40 @@
 		wlan-ant-switch-supply = <&L11C>;
 		qcom,wlan-ant-switch-config = <2800000 2800000 0 0 0>;
 
+		interconnects =
+		<&aggre2_noc MASTER_PCIE_0 &aggre2_noc SLAVE_ANOC_PCIE_GEM_NOC>,
+		<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
+		interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
+
+		qcom,icc-path-count = <2>;
+		qcom,bus-bw-cfg-count = <7>;
+		qcom,bus-bw-cfg =
+		/** ICC Path 1 **/
+		<0 0>, /* no vote */
+		/* idle: 0-18 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
+		<2250 390000>,
+		/* low: 18-60 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
+		<7500 390000>,
+		/* medium: 60-240 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */
+		<30000 790000>,
+		/* high: 240-1080 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */
+		<100000 790000>,
+		/* very high: > 1080 Mbps snoc/anoc: 403 Mhz ddr: 451.2 MHz */
+		<175000 1600000>,
+		/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz
+		 * ddr: 547.2 MHz
+		 */
+		<7500 390000>,
+
+		/** ICC Path 2 **/
+		<0 0>,
+		<2250 1804800>,
+		<7500 1804800>,
+		<30000 1804800>,
+		<100000 1804800>,
+		<175000 6220800>,
+		<7500 2188800>;
+
 		mhi,max-channels = <30>;
 		mhi,timeout = <10000>;
 		mhi,buffer-len = <0x8000>;