From 9bfbf55881ec24bb8dc8f566465ef08bf71473b5 Mon Sep 17 00:00:00 2001 From: Harshdeep Dhatt Date: Fri, 24 Jan 2020 18:05:17 -0700 Subject: [PATCH 1/2] msm: kgsl: Add BICUBIC registers to power up register list These registers are driver owned and need to be saved/restored across preemption and IFPC. Change-Id: Ic9ccff0a047fb5566a7c20e860aefc9dd87284a0 Signed-off-by: Harshdeep Dhatt Signed-off-by: Raghu Ananya Arabolu --- drivers/gpu/msm/adreno_a6xx.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c index aa202252195a..9ea2918c76cd 100644 --- a/drivers/gpu/msm/adreno_a6xx.c +++ b/drivers/gpu/msm/adreno_a6xx.c @@ -102,12 +102,14 @@ static u32 a6xx_ifpc_pwrup_reglist[] = { A6XX_CP_AHB_CNTL, }; -/* - * a620, a650 and a660 need to program A6XX_CP_PROTECT_REG_47 - * for the infinite span - */ +/* Applicable to a620, a650 and a660 */ static u32 a650_pwrup_reglist[] = { - A6XX_CP_PROTECT_REG + 47, + A6XX_CP_PROTECT_REG + 47, /* Programmed for infinite span */ + A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, + A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, + A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, + A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, + A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, }; static u32 a615_pwrup_reglist[] = { From 8c7cf67d61169ee20fae21e95a90635d2615b83e Mon Sep 17 00:00:00 2001 From: Rajesh Kemisetti Date: Tue, 17 Dec 2019 20:09:18 +0530 Subject: [PATCH 2/2] msm: kgsl: Add GPU_RBBM_GBIF_CLIENT_QOS_CNTL to powerup register list GPU_RBBM_GBIF_CLIENT_QOS_CNTL register is getting updated for every wake up sequence but not retained across IFPC. Add this register to GPU specific powerup register list so as to restore its value across IFPC. Change-Id: I3fe15ad43af1f0f1adc49764e749bb89e4cf8a65 Signed-off-by: Rajesh Kemisetti Signed-off-by: Raghu Ananya Arabolu --- drivers/gpu/msm/adreno_a6xx.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c index 9ea2918c76cd..3e8c402c93e5 100644 --- a/drivers/gpu/msm/adreno_a6xx.c +++ b/drivers/gpu/msm/adreno_a6xx.c @@ -63,7 +63,6 @@ static u32 a6xx_pwrup_reglist[] = { /* IFPC only static powerup restore list */ static u32 a6xx_ifpc_pwrup_reglist[] = { - A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, A6XX_CP_CHICKEN_DBG, A6XX_CP_DBG_ECO_CNTL, A6XX_CP_PROTECT_CNTL, @@ -337,6 +336,18 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) lock->list_length += reglist[i].count * 2; } + if (adreno_is_a630(adreno_dev)) { + *dest++ = A6XX_RBBM_VBIF_CLIENT_QOS_CNTL; + kgsl_regread(KGSL_DEVICE(adreno_dev), + A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, dest++); + } else { + *dest++ = A6XX_RBBM_GBIF_CLIENT_QOS_CNTL; + kgsl_regread(KGSL_DEVICE(adreno_dev), + A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, dest++); + } + + lock->list_length += 2; + /* * The overall register list is composed of * 1. Static IFPC-only registers