mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
Merge "Merge android-5.4.7 (861433ef) into msm-5.4"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
3ffb183dd9
572 changed files with 69794 additions and 61780 deletions
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@ -29,6 +29,13 @@ struct pinctrl_dt_map {
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static void dt_free_map(struct pinctrl_dev *pctldev,
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struct pinctrl_map *map, unsigned num_maps)
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{
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int i;
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for (i = 0; i < num_maps; ++i) {
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kfree_const(map[i].dev_name);
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map[i].dev_name = NULL;
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}
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if (pctldev) {
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const struct pinctrl_ops *ops = pctldev->desc->pctlops;
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if (ops->dt_free_map)
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@ -63,7 +70,13 @@ static int dt_remember_or_free_map(struct pinctrl *p, const char *statename,
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/* Initialize common mapping table entry fields */
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for (i = 0; i < num_maps; i++) {
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map[i].dev_name = dev_name(p->dev);
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const char *devname;
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devname = kstrdup_const(dev_name(p->dev), GFP_KERNEL);
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if (!devname)
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goto err_free_map;
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map[i].dev_name = devname;
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map[i].name = statename;
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if (pctldev)
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map[i].ctrl_dev_name = dev_name(pctldev->dev);
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@ -71,10 +84,8 @@ static int dt_remember_or_free_map(struct pinctrl *p, const char *statename,
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/* Remember the converted mapping table entries */
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dt_map = kzalloc(sizeof(*dt_map), GFP_KERNEL);
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if (!dt_map) {
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dt_free_map(pctldev, map, num_maps);
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return -ENOMEM;
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}
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if (!dt_map)
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goto err_free_map;
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dt_map->pctldev = pctldev;
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dt_map->map = map;
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@ -82,6 +93,10 @@ static int dt_remember_or_free_map(struct pinctrl *p, const char *statename,
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list_add_tail(&dt_map->node, &p->dt_maps);
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return pinctrl_register_map(map, num_maps, false);
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err_free_map:
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dt_free_map(pctldev, map, num_maps);
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return -ENOMEM;
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}
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struct pinctrl_dev *of_pinctrl_get(struct device_node *np)
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@ -110,7 +110,6 @@ struct byt_gpio {
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struct platform_device *pdev;
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struct pinctrl_dev *pctl_dev;
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struct pinctrl_desc pctl_desc;
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raw_spinlock_t lock;
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const struct intel_pinctrl_soc_data *soc_data;
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struct intel_community *communities_copy;
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struct byt_gpio_pin_context *saved_context;
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@ -549,6 +548,8 @@ static const struct intel_pinctrl_soc_data *byt_soc_data[] = {
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NULL
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};
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static DEFINE_RAW_SPINLOCK(byt_lock);
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static struct intel_community *byt_get_community(struct byt_gpio *vg,
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unsigned int pin)
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{
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@ -658,7 +659,7 @@ static void byt_set_group_simple_mux(struct byt_gpio *vg,
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unsigned long flags;
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int i;
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raw_spin_lock_irqsave(&vg->lock, flags);
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raw_spin_lock_irqsave(&byt_lock, flags);
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for (i = 0; i < group.npins; i++) {
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void __iomem *padcfg0;
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@ -678,7 +679,7 @@ static void byt_set_group_simple_mux(struct byt_gpio *vg,
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writel(value, padcfg0);
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}
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raw_spin_unlock_irqrestore(&vg->lock, flags);
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raw_spin_unlock_irqrestore(&byt_lock, flags);
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}
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static void byt_set_group_mixed_mux(struct byt_gpio *vg,
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@ -688,7 +689,7 @@ static void byt_set_group_mixed_mux(struct byt_gpio *vg,
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unsigned long flags;
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int i;
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raw_spin_lock_irqsave(&vg->lock, flags);
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raw_spin_lock_irqsave(&byt_lock, flags);
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for (i = 0; i < group.npins; i++) {
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void __iomem *padcfg0;
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@ -708,7 +709,7 @@ static void byt_set_group_mixed_mux(struct byt_gpio *vg,
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writel(value, padcfg0);
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}
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raw_spin_unlock_irqrestore(&vg->lock, flags);
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raw_spin_unlock_irqrestore(&byt_lock, flags);
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}
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static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
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@ -749,11 +750,11 @@ static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset)
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unsigned long flags;
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u32 value;
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raw_spin_lock_irqsave(&vg->lock, flags);
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raw_spin_lock_irqsave(&byt_lock, flags);
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value = readl(reg);
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value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
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writel(value, reg);
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raw_spin_unlock_irqrestore(&vg->lock, flags);
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raw_spin_unlock_irqrestore(&byt_lock, flags);
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}
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static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
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@ -765,7 +766,7 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
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u32 value, gpio_mux;
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unsigned long flags;
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raw_spin_lock_irqsave(&vg->lock, flags);
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raw_spin_lock_irqsave(&byt_lock, flags);
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/*
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* In most cases, func pin mux 000 means GPIO function.
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@ -787,7 +788,7 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
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"pin %u forcibly re-configured as GPIO\n", offset);
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}
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raw_spin_unlock_irqrestore(&vg->lock, flags);
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raw_spin_unlock_irqrestore(&byt_lock, flags);
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pm_runtime_get(&vg->pdev->dev);
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@ -815,7 +816,7 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
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unsigned long flags;
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u32 value;
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raw_spin_lock_irqsave(&vg->lock, flags);
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raw_spin_lock_irqsave(&byt_lock, flags);
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value = readl(val_reg);
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value &= ~BYT_DIR_MASK;
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@ -832,7 +833,7 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
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"Potential Error: Setting GPIO with direct_irq_en to output");
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writel(value, val_reg);
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raw_spin_unlock_irqrestore(&vg->lock, flags);
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raw_spin_unlock_irqrestore(&byt_lock, flags);
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return 0;
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}
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@ -901,11 +902,11 @@ static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
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u32 conf, pull, val, debounce;
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u16 arg = 0;
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raw_spin_lock_irqsave(&vg->lock, flags);
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raw_spin_lock_irqsave(&byt_lock, flags);
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conf = readl(conf_reg);
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pull = conf & BYT_PULL_ASSIGN_MASK;
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val = readl(val_reg);
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raw_spin_unlock_irqrestore(&vg->lock, flags);
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raw_spin_unlock_irqrestore(&byt_lock, flags);
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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@ -932,9 +933,9 @@ static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
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if (!(conf & BYT_DEBOUNCE_EN))
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return -EINVAL;
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raw_spin_lock_irqsave(&vg->lock, flags);
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raw_spin_lock_irqsave(&byt_lock, flags);
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debounce = readl(db_reg);
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raw_spin_unlock_irqrestore(&vg->lock, flags);
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raw_spin_unlock_irqrestore(&byt_lock, flags);
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switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
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case BYT_DEBOUNCE_PULSE_375US:
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@ -986,7 +987,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
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u32 conf, val, debounce;
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int i, ret = 0;
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raw_spin_lock_irqsave(&vg->lock, flags);
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raw_spin_lock_irqsave(&byt_lock, flags);
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conf = readl(conf_reg);
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val = readl(val_reg);
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@ -1094,7 +1095,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
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if (!ret)
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writel(conf, conf_reg);
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raw_spin_unlock_irqrestore(&vg->lock, flags);
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raw_spin_unlock_irqrestore(&byt_lock, flags);
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return ret;
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}
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@ -1119,9 +1120,9 @@ static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
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unsigned long flags;
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u32 val;
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raw_spin_lock_irqsave(&vg->lock, flags);
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raw_spin_lock_irqsave(&byt_lock, flags);
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val = readl(reg);
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raw_spin_unlock_irqrestore(&vg->lock, flags);
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raw_spin_unlock_irqrestore(&byt_lock, flags);
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return !!(val & BYT_LEVEL);
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}
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@ -1136,13 +1137,13 @@ static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
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if (!reg)
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return;
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raw_spin_lock_irqsave(&vg->lock, flags);
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raw_spin_lock_irqsave(&byt_lock, flags);
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old_val = readl(reg);
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if (value)
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writel(old_val | BYT_LEVEL, reg);
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else
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writel(old_val & ~BYT_LEVEL, reg);
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raw_spin_unlock_irqrestore(&vg->lock, flags);
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raw_spin_unlock_irqrestore(&byt_lock, flags);
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}
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static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
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@ -1155,9 +1156,9 @@ static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
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if (!reg)
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return -EINVAL;
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raw_spin_lock_irqsave(&vg->lock, flags);
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raw_spin_lock_irqsave(&byt_lock, flags);
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value = readl(reg);
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raw_spin_unlock_irqrestore(&vg->lock, flags);
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raw_spin_unlock_irqrestore(&byt_lock, flags);
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if (!(value & BYT_OUTPUT_EN))
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return 0;
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@ -1200,14 +1201,14 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
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const char *label;
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unsigned int pin;
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raw_spin_lock_irqsave(&vg->lock, flags);
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raw_spin_lock_irqsave(&byt_lock, flags);
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pin = vg->soc_data->pins[i].number;
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reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
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if (!reg) {
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seq_printf(s,
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"Could not retrieve pin %i conf0 reg\n",
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pin);
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raw_spin_unlock_irqrestore(&vg->lock, flags);
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raw_spin_unlock_irqrestore(&byt_lock, flags);
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continue;
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}
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conf0 = readl(reg);
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@ -1216,11 +1217,11 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
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if (!reg) {
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seq_printf(s,
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"Could not retrieve pin %i val reg\n", pin);
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raw_spin_unlock_irqrestore(&vg->lock, flags);
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raw_spin_unlock_irqrestore(&byt_lock, flags);
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continue;
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}
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val = readl(reg);
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raw_spin_unlock_irqrestore(&vg->lock, flags);
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raw_spin_unlock_irqrestore(&byt_lock, flags);
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comm = byt_get_community(vg, pin);
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if (!comm) {
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|
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@ -1304,9 +1305,9 @@ static void byt_irq_ack(struct irq_data *d)
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|||
if (!reg)
|
||||
return;
|
||||
|
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raw_spin_lock(&vg->lock);
|
||||
raw_spin_lock(&byt_lock);
|
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writel(BIT(offset % 32), reg);
|
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raw_spin_unlock(&vg->lock);
|
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raw_spin_unlock(&byt_lock);
|
||||
}
|
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|
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static void byt_irq_mask(struct irq_data *d)
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|
|
@ -1330,7 +1331,7 @@ static void byt_irq_unmask(struct irq_data *d)
|
|||
if (!reg)
|
||||
return;
|
||||
|
||||
raw_spin_lock_irqsave(&vg->lock, flags);
|
||||
raw_spin_lock_irqsave(&byt_lock, flags);
|
||||
value = readl(reg);
|
||||
|
||||
switch (irqd_get_trigger_type(d)) {
|
||||
|
|
@ -1353,7 +1354,7 @@ static void byt_irq_unmask(struct irq_data *d)
|
|||
|
||||
writel(value, reg);
|
||||
|
||||
raw_spin_unlock_irqrestore(&vg->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&byt_lock, flags);
|
||||
}
|
||||
|
||||
static int byt_irq_type(struct irq_data *d, unsigned int type)
|
||||
|
|
@ -1367,7 +1368,7 @@ static int byt_irq_type(struct irq_data *d, unsigned int type)
|
|||
if (!reg || offset >= vg->chip.ngpio)
|
||||
return -EINVAL;
|
||||
|
||||
raw_spin_lock_irqsave(&vg->lock, flags);
|
||||
raw_spin_lock_irqsave(&byt_lock, flags);
|
||||
value = readl(reg);
|
||||
|
||||
WARN(value & BYT_DIRECT_IRQ_EN,
|
||||
|
|
@ -1389,7 +1390,7 @@ static int byt_irq_type(struct irq_data *d, unsigned int type)
|
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else if (type & IRQ_TYPE_LEVEL_MASK)
|
||||
irq_set_handler_locked(d, handle_level_irq);
|
||||
|
||||
raw_spin_unlock_irqrestore(&vg->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&byt_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1425,9 +1426,9 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
|
|||
continue;
|
||||
}
|
||||
|
||||
raw_spin_lock(&vg->lock);
|
||||
raw_spin_lock(&byt_lock);
|
||||
pending = readl(reg);
|
||||
raw_spin_unlock(&vg->lock);
|
||||
raw_spin_unlock(&byt_lock);
|
||||
for_each_set_bit(pin, &pending, 32) {
|
||||
virq = irq_find_mapping(vg->chip.irq.domain, base + pin);
|
||||
generic_handle_irq(virq);
|
||||
|
|
@ -1638,8 +1639,6 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
|
|||
return PTR_ERR(vg->pctl_dev);
|
||||
}
|
||||
|
||||
raw_spin_lock_init(&vg->lock);
|
||||
|
||||
ret = byt_gpio_probe(vg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
@ -1654,8 +1653,11 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
|
|||
static int byt_gpio_suspend(struct device *dev)
|
||||
{
|
||||
struct byt_gpio *vg = dev_get_drvdata(dev);
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
raw_spin_lock_irqsave(&byt_lock, flags);
|
||||
|
||||
for (i = 0; i < vg->soc_data->npins; i++) {
|
||||
void __iomem *reg;
|
||||
u32 value;
|
||||
|
|
@ -1676,14 +1678,18 @@ static int byt_gpio_suspend(struct device *dev)
|
|||
vg->saved_context[i].val = value;
|
||||
}
|
||||
|
||||
raw_spin_unlock_irqrestore(&byt_lock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int byt_gpio_resume(struct device *dev)
|
||||
{
|
||||
struct byt_gpio *vg = dev_get_drvdata(dev);
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
raw_spin_lock_irqsave(&byt_lock, flags);
|
||||
|
||||
for (i = 0; i < vg->soc_data->npins; i++) {
|
||||
void __iomem *reg;
|
||||
u32 value;
|
||||
|
|
@ -1721,6 +1727,7 @@ static int byt_gpio_resume(struct device *dev)
|
|||
}
|
||||
}
|
||||
|
||||
raw_spin_unlock_irqrestore(&byt_lock, flags);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -540,7 +540,8 @@ static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
|
|||
irqreturn_t ret = IRQ_NONE;
|
||||
unsigned int i, irqnr;
|
||||
unsigned long flags;
|
||||
u32 *regs, regval;
|
||||
u32 __iomem *regs;
|
||||
u32 regval;
|
||||
u64 status, mask;
|
||||
|
||||
/* Read the wake status */
|
||||
|
|
|
|||
|
|
@ -77,6 +77,7 @@ enum {
|
|||
.intr_cfg_reg = 0, \
|
||||
.intr_status_reg = 0, \
|
||||
.intr_target_reg = 0, \
|
||||
.tile = SOUTH, \
|
||||
.mux_bit = -1, \
|
||||
.pull_bit = pull, \
|
||||
.drv_bit = drv, \
|
||||
|
|
@ -102,6 +103,7 @@ enum {
|
|||
.intr_cfg_reg = 0, \
|
||||
.intr_status_reg = 0, \
|
||||
.intr_target_reg = 0, \
|
||||
.tile = SOUTH, \
|
||||
.mux_bit = -1, \
|
||||
.pull_bit = 3, \
|
||||
.drv_bit = 0, \
|
||||
|
|
@ -1087,14 +1089,14 @@ static const struct msm_pingroup sc7180_groups[] = {
|
|||
[116] = PINGROUP(116, WEST, qup04, qup04, _, _, _, _, _, _, _),
|
||||
[117] = PINGROUP(117, WEST, dp_hot, _, _, _, _, _, _, _, _),
|
||||
[118] = PINGROUP(118, WEST, _, _, _, _, _, _, _, _, _),
|
||||
[119] = UFS_RESET(ufs_reset, 0x97f000),
|
||||
[120] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x97a000, 15, 0),
|
||||
[121] = SDC_QDSD_PINGROUP(sdc1_clk, 0x97a000, 13, 6),
|
||||
[122] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x97a000, 11, 3),
|
||||
[123] = SDC_QDSD_PINGROUP(sdc1_data, 0x97a000, 9, 0),
|
||||
[124] = SDC_QDSD_PINGROUP(sdc2_clk, 0x97b000, 14, 6),
|
||||
[125] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x97b000, 11, 3),
|
||||
[126] = SDC_QDSD_PINGROUP(sdc2_data, 0x97b000, 9, 0),
|
||||
[119] = UFS_RESET(ufs_reset, 0x7f000),
|
||||
[120] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x7a000, 15, 0),
|
||||
[121] = SDC_QDSD_PINGROUP(sdc1_clk, 0x7a000, 13, 6),
|
||||
[122] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x7a000, 11, 3),
|
||||
[123] = SDC_QDSD_PINGROUP(sdc1_data, 0x7a000, 9, 0),
|
||||
[124] = SDC_QDSD_PINGROUP(sdc2_clk, 0x7b000, 14, 6),
|
||||
[125] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x7b000, 11, 3),
|
||||
[126] = SDC_QDSD_PINGROUP(sdc2_data, 0x7b000, 9, 0),
|
||||
};
|
||||
|
||||
static const struct msm_pinctrl_soc_data sc7180_pinctrl = {
|
||||
|
|
|
|||
|
|
@ -448,6 +448,8 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
|
|||
#define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0))
|
||||
|
||||
/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
|
||||
#define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1)
|
||||
#define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
|
||||
#define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
|
||||
#define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1)
|
||||
#define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
|
||||
|
|
@ -468,7 +470,8 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
|
|||
|
||||
#define PINMUX_MOD_SELS \
|
||||
\
|
||||
MOD_SEL0_30_29 \
|
||||
MOD_SEL1_31 \
|
||||
MOD_SEL0_30_29 MOD_SEL1_30 \
|
||||
MOD_SEL1_29 \
|
||||
MOD_SEL0_28 MOD_SEL1_28 \
|
||||
MOD_SEL0_27_26 \
|
||||
|
|
@ -1058,7 +1061,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
|
||||
PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0),
|
||||
PINMUX_IPSR_GPSR(IP10_27_24, SSI_SCK2_B),
|
||||
PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1),
|
||||
PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
|
||||
|
|
@ -1067,7 +1070,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
|
||||
PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0),
|
||||
PINMUX_IPSR_GPSR(IP10_31_28, SSI_WS2_B),
|
||||
PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1),
|
||||
PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0),
|
||||
|
||||
/* IPSR11 */
|
||||
|
|
@ -1085,13 +1088,13 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0),
|
||||
PINMUX_IPSR_GPSR(IP11_11_8, SSI_SCK2_A),
|
||||
PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0),
|
||||
PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC),
|
||||
PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A),
|
||||
PINMUX_IPSR_GPSR(IP11_15_12, SSI_WS2_A),
|
||||
PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0),
|
||||
PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0),
|
||||
PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1),
|
||||
|
||||
|
|
@ -1196,7 +1199,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0),
|
||||
PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1),
|
||||
PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1),
|
||||
PINMUX_IPSR_GPSR(IP13_19_16, SIM0_D_A),
|
||||
PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT),
|
||||
PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1),
|
||||
|
|
@ -1264,7 +1267,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2),
|
||||
PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3),
|
||||
PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1),
|
||||
PINMUX_IPSR_GPSR(IP15_15_12, SIM0_D_B),
|
||||
PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6),
|
||||
PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
|
||||
|
|
@ -4957,11 +4960,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL0_1_0 ))
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
|
||||
GROUP(2, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 1,
|
||||
2, 2, 2, 1, 1, 2, 1, 4),
|
||||
GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
|
||||
1, 2, 2, 2, 1, 1, 2, 1, 4),
|
||||
GROUP(
|
||||
/* RESERVED 31, 30 */
|
||||
0, 0, 0, 0,
|
||||
MOD_SEL1_31
|
||||
MOD_SEL1_30
|
||||
MOD_SEL1_29
|
||||
MOD_SEL1_28
|
||||
/* RESERVED 27 */
|
||||
|
|
|
|||
|
|
@ -1450,7 +1450,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
|
|||
GPIO_FN(ET0_ETXD2_A),
|
||||
GPIO_FN(EX_CS5), GPIO_FN(SD1_CMD_A), GPIO_FN(ATADIR), GPIO_FN(QSSL_B),
|
||||
GPIO_FN(ET0_ETXD3_A),
|
||||
GPIO_FN(RD_WR), GPIO_FN(TCLK1_B),
|
||||
GPIO_FN(RD_WR), GPIO_FN(TCLK0), GPIO_FN(CAN_CLK_B), GPIO_FN(ET0_ETXD4),
|
||||
GPIO_FN(EX_WAIT0), GPIO_FN(TCLK1_B),
|
||||
GPIO_FN(EX_WAIT1), GPIO_FN(SD1_DAT0_A), GPIO_FN(DREQ2),
|
||||
GPIO_FN(CAN1_TX_C), GPIO_FN(ET0_LINK_C), GPIO_FN(ET0_ETXD5_A),
|
||||
|
|
@ -1949,7 +1949,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
/* IP3_20 [1] */
|
||||
FN_EX_WAIT0, FN_TCLK1_B,
|
||||
/* IP3_19_18 [2] */
|
||||
FN_RD_WR, FN_TCLK1_B, 0, 0,
|
||||
FN_RD_WR, FN_TCLK0, FN_CAN_CLK_B, FN_ET0_ETXD4,
|
||||
/* IP3_17_15 [3] */
|
||||
FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B,
|
||||
FN_ET0_ETXD3_A, 0, 0, 0,
|
||||
|
|
|
|||
Loading…
Reference in a new issue