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cnss2: Dump PCIE SOC scratch registers along with mhi reg dumps

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Add code to dump PCIE SOC scratch registers along with mhi reg
dumps to enhance debug info.

Change-Id: I65fc8324a8cccac6f5ffe73f6fc9513a561ee32e
Signed-off-by: Mohammed Siddiq <msiddiq@codeaurora.org>
This commit is contained in:
Mohammed Siddiq 2021-09-06 19:55:36 +05:30
commit 404f28d635
2 changed files with 49 additions and 0 deletions
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44
drivers/net/wireless/cnss2/pci.c
View file

@ -135,6 +135,13 @@ static struct cnss_pci_reg qdss_csr[] = {
{ NULL },
};
static struct cnss_pci_reg pci_scratch[] = {
{ "PCIE_SCRATCH_0", PCIE_SCRATCH_0_SOC_PCIE_REG },
{ "PCIE_SCRATCH_1", PCIE_SCRATCH_1_SOC_PCIE_REG },
{ "PCIE_SCRATCH_2", PCIE_SCRATCH_2_SOC_PCIE_REG },
{ NULL },
};
/* First field of the structure is the device bit mask. Use
* enum cnss_pci_reg_mask as reference for the value.
*/
@ -1082,6 +1089,36 @@ retry:
return ret;
}
static void cnss_pci_soc_scratch_reg_dump(struct cnss_pci_data *pci_priv)
{
u32 reg_offset, val;
int i;
switch (pci_priv->device_id) {
case QCA6390_DEVICE_ID:
case QCA6490_DEVICE_ID:
break;
default:
return;
}
if (in_interrupt() || irqs_disabled())
return;
if (cnss_pci_check_link_status(pci_priv))
return;
cnss_pr_dbg("Start to dump SOC Scratch registers\n");
for (i = 0; pci_scratch[i].name; i++) {
reg_offset = pci_scratch[i].offset;
if (cnss_pci_reg_read(pci_priv, reg_offset, &val))
return;
cnss_pr_dbg("PCIE_SOC_REG_%s = 0x%x\n",
pci_scratch[i].name, val);
}
}
int cnss_suspend_pci_link(struct cnss_pci_data *pci_priv)
{
int ret = 0;
@ -1202,6 +1239,7 @@ int cnss_pci_recover_link_down(struct cnss_pci_data *pci_priv)
jiffies + msecs_to_jiffies(DEV_RDDM_TIMEOUT));
mhi_debug_reg_dump(pci_priv->mhi_ctrl);
cnss_pci_soc_scratch_reg_dump(pci_priv);
return 0;
}
@ -1568,6 +1606,7 @@ static int cnss_pci_handle_mhi_poweron_timeout(struct cnss_pci_data *pci_priv)
} else {
cnss_pr_dbg("RDDM cookie is not set\n");
mhi_debug_reg_dump(pci_priv->mhi_ctrl);
cnss_pci_soc_scratch_reg_dump(pci_priv);
/* Dump PBL/SBL error log if RDDM cookie is not set */
cnss_pci_dump_bl_sram_mem(pci_priv);
return -ETIMEDOUT;
@ -4783,6 +4822,7 @@ static void cnss_pci_dump_debug_reg(struct cnss_pci_data *pci_priv)
cnss_pr_dbg("Start to dump debug registers\n");
mhi_debug_reg_dump(pci_priv->mhi_ctrl);
cnss_pci_soc_scratch_reg_dump(pci_priv);
cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_COMMON);
cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_09);
cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_10);
@ -4809,6 +4849,7 @@ int cnss_pci_force_fw_assert_hdlr(struct cnss_pci_data *pci_priv)
if (!cnss_pci_check_link_status(pci_priv))
mhi_debug_reg_dump(pci_priv->mhi_ctrl);
cnss_pci_soc_scratch_reg_dump(pci_priv);
cnss_pci_dump_misc_reg(pci_priv);
cnss_pci_dump_shadow_reg(pci_priv);
@ -4990,6 +5031,7 @@ void cnss_pci_collect_dump_info(struct cnss_pci_data *pci_priv, bool in_panic)
}
mhi_debug_reg_dump(pci_priv->mhi_ctrl);
cnss_pci_soc_scratch_reg_dump(pci_priv);
cnss_pci_dump_misc_reg(pci_priv);
cnss_pci_dump_shadow_reg(pci_priv);
cnss_pci_dump_qdss_reg(pci_priv);
@ -5271,6 +5313,7 @@ static void cnss_dev_rddm_timeout_hdlr(struct timer_list *t)
cnss_pr_err("Unable to collect ramdumps due to abrupt reset\n");
mhi_debug_reg_dump(pci_priv->mhi_ctrl);
cnss_pci_soc_scratch_reg_dump(pci_priv);
cnss_schedule_recovery(&pci_priv->pci_dev->dev, CNSS_REASON_TIMEOUT);
}
@ -5298,6 +5341,7 @@ static void cnss_boot_debug_timeout_hdlr(struct timer_list *t)
cnss_pr_dbg("Dump MHI/PBL/SBL debug data every %ds during MHI power on\n",
BOOT_DEBUG_TIMEOUT_MS / 1000);
mhi_debug_reg_dump(pci_priv->mhi_ctrl);
cnss_pci_soc_scratch_reg_dump(pci_priv);
cnss_pci_dump_bl_sram_mem(pci_priv);
mod_timer(&pci_priv->boot_debug_timer,

5
drivers/net/wireless/cnss2/reg.h
View file

@ -324,4 +324,9 @@
#define QCA6390_PCIE_BHI_ERRDBG3_REG 0x01E0E23C
#define QCA6390_PBL_WLAN_BOOT_CFG 0x01E22B34
#define QCA6390_PBL_BOOTSTRAP_STATUS 0x01910008
/* PCIE SOC scratch registers, address same for QCA6390 & QCA6490*/
#define PCIE_SCRATCH_0_SOC_PCIE_REG 0x1E04040
#define PCIE_SCRATCH_1_SOC_PCIE_REG 0x1E04044
#define PCIE_SCRATCH_2_SOC_PCIE_REG 0x1E0405C
#endif