A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-29 11:11:45 -04:00
Code Issues Projects Releases Packages Wiki Activity

Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Browse source 
Pull irq updates from Thomas Gleixner:
 "The irq departement delivers:

   - plug a potential race related to chained interrupt handlers

   - core updates which address the needs of the x86 irqdomain conversion

   - new irqchip callback to support affinity settings for VCPUs

   - the usual pile of updates to interrupt chip drivers

   - a few helper functions to allow further cleanups and
     simplifications

  I have a largish pile of coccinelle scripted/verified cleanups and
  simplifications pending on top of that, but I prefer to send that
  towards the end of the merge window when the arch/driver changes have
  hit your tree to avoid API change wreckage as far as possible"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (34 commits)
  genirq: Remove bogus restriction in irq_move_mask_irq()
  irqchip: atmel-aic5: Add sama5d2 support
  irq: spear-shirq: Fix race in installing chained IRQ handler
  irq: irq-keystone: Fix race in installing chained IRQ handler
  gpio: gpio-tegra: Fix race in installing chained IRQ handler
  gpio: gpio-mxs: Fix race in installing chained IRQ handler
  gpio: gpio-mxc: Fix race in installing chained IRQ handler
  ARM: gemini: Fix race in installing GPIO chained IRQ handler
  GPU: ipu: Fix race in installing IPU chained IRQ handler
  ARM: sa1100: convert SA11x0 related code to use new chained handler helper
  irq: Add irq_set_chained_handler_and_data()
  irqchip: exynos-combiner: Save IRQ enable set on suspend
  genirq: Introduce helper function irq_data_get_affinity_mask()
  genirq: Introduce helper function irq_data_get_node()
  genirq: Introduce struct irq_common_data to host shared irq data
  genirq: Prevent crash in irq_move_irq()
  genirq: Enhance irq_data_to_desc() to support hierarchy irqdomain
  irqchip: gic: Simplify gic_configure_irq by using IRQCHIP_SET_TYPE_MASKED
  irqchip: renesas: intc-irqpin: Improve binding documentation
  genirq: Set IRQCHIP_SKIP_SET_WAKE for no_irq_chip
  ...
This commit is contained in:
Linus Torvalds 2015-06-22 19:42:56 -07:00
commit 407a2c7205
49 changed files with 378 additions and 191 deletions
Download patch file Download diff file Expand all files Collapse all files

1
drivers/irqchip/Kconfig
View file

@ -30,6 +30,7 @@ config ARM_GIC_V3_ITS
config ARM_NVIC
bool
select IRQ_DOMAIN
select IRQ_DOMAIN_HIERARCHY
select GENERIC_IRQ_CHIP
config ARM_VIC

66
drivers/irqchip/exynos-combiner.c
View file

@ -13,6 +13,7 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/syscore_ops.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/interrupt.h>
@ -34,9 +35,14 @@ struct combiner_chip_data {
unsigned int irq_mask;
void __iomem *base;
unsigned int parent_irq;
#ifdef CONFIG_PM
u32 pm_save;
#endif
};
static struct combiner_chip_data *combiner_data;
static struct irq_domain *combiner_irq_domain;
static unsigned int max_nr = 20;
static inline void __iomem *combiner_base(struct irq_data *data)
{
@ -164,18 +170,16 @@ static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
return 0;
}
static struct irq_domain_ops combiner_irq_domain_ops = {
static const struct irq_domain_ops combiner_irq_domain_ops = {
.xlate = combiner_irq_domain_xlate,
.map = combiner_irq_domain_map,
};
static void __init combiner_init(void __iomem *combiner_base,
struct device_node *np,
unsigned int max_nr)
struct device_node *np)
{
int i, irq;
unsigned int nr_irq;
struct combiner_chip_data *combiner_data;
nr_irq = max_nr * IRQ_IN_COMBINER;
@ -201,11 +205,59 @@ static void __init combiner_init(void __iomem *combiner_base,
}
}
#ifdef CONFIG_PM
/**
* combiner_suspend - save interrupt combiner state before suspend
*
* Save the interrupt enable set register for all combiner groups since
* the state is lost when the system enters into a sleep state.
*
*/
static int combiner_suspend(void)
{
int i;
for (i = 0; i < max_nr; i++)
combiner_data[i].pm_save =
__raw_readl(combiner_data[i].base + COMBINER_ENABLE_SET);
return 0;
}
/**
* combiner_resume - restore interrupt combiner state after resume
*
* Restore the interrupt enable set register for all combiner groups since
* the state is lost when the system enters into a sleep state on suspend.
*
*/
static void combiner_resume(void)
{
int i;
for (i = 0; i < max_nr; i++) {
__raw_writel(combiner_data[i].irq_mask,
combiner_data[i].base + COMBINER_ENABLE_CLEAR);
__raw_writel(combiner_data[i].pm_save,
combiner_data[i].base + COMBINER_ENABLE_SET);
}
}
#else
#define combiner_suspend NULL
#define combiner_resume NULL
#endif
static struct syscore_ops combiner_syscore_ops = {
.suspend = combiner_suspend,
.resume = combiner_resume,
};
static int __init combiner_of_init(struct device_node *np,
struct device_node *parent)
{
void __iomem *combiner_base;
unsigned int max_nr = 20;
combiner_base = of_iomap(np, 0);
if (!combiner_base) {
@ -219,7 +271,9 @@ static int __init combiner_of_init(struct device_node *np,
__func__, max_nr);
}
combiner_init(combiner_base, np, max_nr);
combiner_init(combiner_base, np);
register_syscore_ops(&combiner_syscore_ops);
return 0;
}

2
drivers/irqchip/irq-armada-370-xp.c
View file

@ -409,7 +409,7 @@ static struct notifier_block mpic_cascaded_cpu_notifier = {
};
#endif /* CONFIG_SMP */
static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
.map = armada_370_xp_mpic_irq_map,
.xlate = irq_domain_xlate_onecell,
};

9
drivers/irqchip/irq-atmel-aic5.c
View file

@ -339,6 +339,15 @@ static int __init aic5_of_init(struct device_node *node,
return 0;
}
#define NR_SAMA5D2_IRQS 77
static int __init sama5d2_aic5_of_init(struct device_node *node,
struct device_node *parent)
{
return aic5_of_init(node, parent, NR_SAMA5D2_IRQS);
}
IRQCHIP_DECLARE(sama5d2_aic5, "atmel,sama5d2-aic", sama5d2_aic5_of_init);
#define NR_SAMA5D3_IRQS 48
static int __init sama5d3_aic5_of_init(struct device_node *node,

2
drivers/irqchip/irq-bcm2835.c
View file

@ -135,7 +135,7 @@ static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
return 0;
}
static struct irq_domain_ops armctrl_ops = {
static const struct irq_domain_ops armctrl_ops = {
.xlate = armctrl_xlate
};

17
drivers/irqchip/irq-gic-common.c
View file

@ -24,11 +24,8 @@
int gic_configure_irq(unsigned int irq, unsigned int type,
void __iomem *base, void (*sync_access)(void))
{
u32 enablemask = 1 << (irq % 32);
u32 enableoff = (irq / 32) * 4;
u32 confmask = 0x2 << ((irq % 16) * 2);
u32 confoff = (irq / 16) * 4;
bool enabled = false;
u32 val, oldval;
int ret = 0;
@ -42,17 +39,6 @@ int gic_configure_irq(unsigned int irq, unsigned int type,
else if (type & IRQ_TYPE_EDGE_BOTH)
val |= confmask;
/*
* As recommended by the spec, disable the interrupt before changing
* the configuration
*/
if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
if (sync_access)
sync_access();
enabled = true;
}
/*
* Write back the new configuration, and possibly re-enable
* the interrupt. If we tried to write a new configuration and failed,
@ -62,9 +48,6 @@ int gic_configure_irq(unsigned int irq, unsigned int type,
if (readl_relaxed(base + GIC_DIST_CONFIG + confoff) != val && val != oldval)
ret = -EINVAL;
if (enabled)
writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
if (sync_access)
sync_access();

1
drivers/irqchip/irq-gic-v3.c
View file

@ -658,6 +658,7 @@ static struct irq_chip gic_chip = {
.irq_set_affinity = gic_set_affinity,
.irq_get_irqchip_state = gic_irq_get_irqchip_state,
.irq_set_irqchip_state = gic_irq_set_irqchip_state,
.flags = IRQCHIP_SET_TYPE_MASKED,
};
#define GIC_ID_NR (1U << gic_data.rdists.id_bits)

1
drivers/irqchip/irq-gic.c
View file

@ -324,6 +324,7 @@ static struct irq_chip gic_chip = {
#endif
.irq_get_irqchip_state = gic_irq_get_irqchip_state,
.irq_set_irqchip_state = gic_irq_set_irqchip_state,
.flags = IRQCHIP_SET_TYPE_MASKED,
};
void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)

1
drivers/irqchip/irq-hip04.c
View file

@ -202,6 +202,7 @@ static struct irq_chip hip04_irq_chip = {
#ifdef CONFIG_SMP
.irq_set_affinity = hip04_irq_set_affinity,
#endif
.flags = IRQCHIP_SET_TYPE_MASKED,
};
static u16 hip04_get_cpumask(struct hip04_irq_data *intc)

5
drivers/irqchip/irq-keystone.c
View file

@ -131,7 +131,7 @@ static int keystone_irq_map(struct irq_domain *h, unsigned int virq,
return 0;
}
static struct irq_domain_ops keystone_irq_ops = {
static const struct irq_domain_ops keystone_irq_ops = {
.map = keystone_irq_map,
.xlate = irq_domain_xlate_onecell,
};
@ -184,8 +184,7 @@ static int keystone_irq_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, kirq);
irq_set_chained_handler(kirq->irq, keystone_irq_handler);
irq_set_handler_data(kirq->irq, kirq);
irq_set_chained_handler_and_data(kirq->irq, keystone_irq_handler, kirq);
/* clear all source bits */
keystone_irq_writel(kirq, ~0x0);

2
drivers/irqchip/irq-mips-gic.c
View file

@ -746,7 +746,7 @@ static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
return 0;
}
static struct irq_domain_ops gic_irq_domain_ops = {
static const struct irq_domain_ops gic_irq_domain_ops = {
.map = gic_irq_domain_map,
.xlate = gic_irq_domain_xlate,
};

4
drivers/irqchip/irq-mtk-sysirq.c
View file

@ -111,7 +111,7 @@ static int mtk_sysirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_data);
}
static struct irq_domain_ops sysirq_domain_ops = {
static const struct irq_domain_ops sysirq_domain_ops = {
.xlate = mtk_sysirq_domain_xlate,
.alloc = mtk_sysirq_domain_alloc,
.free = irq_domain_free_irqs_common,
@ -144,7 +144,7 @@ static int __init mtk_sysirq_of_init(struct device_node *node,
chip_data->intpol_base = ioremap(res.start, size);
if (!chip_data->intpol_base) {
pr_err("mtk_sysirq: unable to map sysirq register\n");
ret = PTR_ERR(chip_data->intpol_base);
ret = -ENXIO;
goto out_free;
}

2
drivers/irqchip/irq-mxs.c
View file

@ -90,7 +90,7 @@ static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
return 0;
}
static struct irq_domain_ops icoll_irq_domain_ops = {
static const struct irq_domain_ops icoll_irq_domain_ops = {
.map = icoll_irq_domain_map,
.xlate = irq_domain_xlate_onecell,
};

28
drivers/irqchip/irq-nvic.c
View file

@ -49,6 +49,31 @@ nvic_handle_irq(irq_hw_number_t hwirq, struct pt_regs *regs)
handle_IRQ(irq, regs);
}
static int nvic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *arg)
{
int i, ret;
irq_hw_number_t hwirq;
unsigned int type = IRQ_TYPE_NONE;
struct of_phandle_args *irq_data = arg;
ret = irq_domain_xlate_onecell(domain, irq_data->np, irq_data->args,
irq_data->args_count, &hwirq, &type);
if (ret)
return ret;
for (i = 0; i < nr_irqs; i++)
irq_map_generic_chip(domain, virq + i, hwirq + i);
return 0;
}
static const struct irq_domain_ops nvic_irq_domain_ops = {
.xlate = irq_domain_xlate_onecell,
.alloc = nvic_irq_domain_alloc,
.free = irq_domain_free_irqs_top,
};
static int __init nvic_of_init(struct device_node *node,
struct device_node *parent)
{
@ -70,7 +95,8 @@ static int __init nvic_of_init(struct device_node *node,
irqs = NVIC_MAX_IRQ;
nvic_irq_domain =
irq_domain_add_linear(node, irqs, &irq_generic_chip_ops, NULL);
irq_domain_add_linear(node, irqs, &nvic_irq_domain_ops, NULL);
if (!nvic_irq_domain) {
pr_warn("Failed to allocate irq domain\n");
return -ENOMEM;

2
drivers/irqchip/irq-renesas-intc-irqpin.c
View file

@ -347,7 +347,7 @@ static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
return 0;
}
static struct irq_domain_ops intc_irqpin_irq_domain_ops = {
static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
.map = intc_irqpin_irq_domain_map,
.xlate = irq_domain_xlate_twocell,
};

19
drivers/irqchip/irq-renesas-irqc.c
View file

@ -29,7 +29,6 @@
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_data/irq-renesas-irqc.h>
#include <linux/pm_runtime.h>
#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */
@ -62,7 +61,6 @@ struct irqc_priv {
void __iomem *iomem;
void __iomem *cpu_int_base;
struct irqc_irq irq[IRQC_IRQ_MAX];
struct renesas_irqc_config config;
unsigned int number_of_irqs;
struct platform_device *pdev;
struct irq_chip irq_chip;
@ -168,14 +166,13 @@ static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq,
return 0;
}
static struct irq_domain_ops irqc_irq_domain_ops = {
static const struct irq_domain_ops irqc_irq_domain_ops = {
.map = irqc_irq_domain_map,
.xlate = irq_domain_xlate_twocell,
};
static int irqc_probe(struct platform_device *pdev)
{
struct renesas_irqc_config *pdata = pdev->dev.platform_data;
struct irqc_priv *p;
struct resource *io;
struct resource *irq;
@ -191,10 +188,6 @@ static int irqc_probe(struct platform_device *pdev)
goto err0;
}
/* deal with driver instance configuration */
if (pdata)
memcpy(&p->config, pdata, sizeof(*pdata));
p->pdev = pdev;
platform_set_drvdata(pdev, p);
@ -251,8 +244,7 @@ static int irqc_probe(struct platform_device *pdev)
irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
p->number_of_irqs,
p->config.irq_base,
p->number_of_irqs, 0,
&irqc_irq_domain_ops, p);
if (!p->irq_domain) {
ret = -ENXIO;
@ -272,13 +264,6 @@ static int irqc_probe(struct platform_device *pdev)
dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);
/* warn in case of mismatch if irq base is specified */
if (p->config.irq_base) {
if (p->config.irq_base != p->irq[0].domain_irq)
dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n",
p->config.irq_base, p->irq[0].domain_irq);
}
return 0;
err3:
while (--k >= 0)

4
drivers/irqchip/irq-s3c24xx.c
View file

@ -502,7 +502,7 @@ err:
return -EINVAL;
}
static struct irq_domain_ops s3c24xx_irq_ops = {
static const struct irq_domain_ops s3c24xx_irq_ops = {
.map = s3c24xx_irq_map,
.xlate = irq_domain_xlate_twocell,
};
@ -1228,7 +1228,7 @@ static int s3c24xx_irq_xlate_of(struct irq_domain *d, struct device_node *n,
return 0;
}
static struct irq_domain_ops s3c24xx_irq_ops_of = {
static const struct irq_domain_ops s3c24xx_irq_ops_of = {
.map = s3c24xx_irq_map_of,
.xlate = s3c24xx_irq_xlate_of,
};

2
drivers/irqchip/irq-sun4i.c
View file

@ -89,7 +89,7 @@ static int sun4i_irq_map(struct irq_domain *d, unsigned int virq,
return 0;
}
static struct irq_domain_ops sun4i_irq_ops = {
static const struct irq_domain_ops sun4i_irq_ops = {
.map = sun4i_irq_map,
.xlate = irq_domain_xlate_onecell,
};

2
drivers/irqchip/irq-versatile-fpga.c
View file

@ -132,7 +132,7 @@ static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
return 0;
}
static struct irq_domain_ops fpga_irqdomain_ops = {
static const struct irq_domain_ops fpga_irqdomain_ops = {
.map = fpga_irqdomain_map,
.xlate = irq_domain_xlate_onetwocell,
};

28
drivers/irqchip/irq-vf610-mscm-ir.c
View file

@ -47,6 +47,7 @@ struct vf610_mscm_ir_chip_data {
void __iomem *mscm_ir_base;
u16 cpu_mask;
u16 saved_irsprc[MSCM_IRSPRC_NUM];
bool is_nvic;
};
static struct vf610_mscm_ir_chip_data *mscm_ir_data;
@ -101,7 +102,7 @@ static void vf610_mscm_ir_enable(struct irq_data *data)
writew_relaxed(chip_data->cpu_mask,
chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
irq_chip_unmask_parent(data);
irq_chip_enable_parent(data);
}
static void vf610_mscm_ir_disable(struct irq_data *data)
@ -111,7 +112,7 @@ static void vf610_mscm_ir_disable(struct irq_data *data)
writew_relaxed(0x0, chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
irq_chip_mask_parent(data);
irq_chip_disable_parent(data);
}
static struct irq_chip vf610_mscm_ir_irq_chip = {
@ -143,10 +144,17 @@ static int vf610_mscm_ir_domain_alloc(struct irq_domain *domain, unsigned int vi
domain->host_data);
gic_data.np = domain->parent->of_node;
gic_data.args_count = 3;
gic_data.args[0] = GIC_SPI;
gic_data.args[1] = irq_data->args[0];
gic_data.args[2] = irq_data->args[1];
if (mscm_ir_data->is_nvic) {
gic_data.args_count = 1;
gic_data.args[0] = irq_data->args[0];
} else {
gic_data.args_count = 3;
gic_data.args[0] = GIC_SPI;
gic_data.args[1] = irq_data->args[0];
gic_data.args[2] = irq_data->args[1];
}
return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_data);
}
@ -174,10 +182,9 @@ static int __init vf610_mscm_ir_of_init(struct device_node *node,
return -ENOMEM;
mscm_ir_data->mscm_ir_base = of_io_request_and_map(node, 0, "mscm-ir");
if (!mscm_ir_data->mscm_ir_base) {
if (IS_ERR(mscm_ir_data->mscm_ir_base)) {
pr_err("vf610_mscm_ir: unable to map mscm register\n");
ret = -ENOMEM;
ret = PTR_ERR(mscm_ir_data->mscm_ir_base);
goto out_free;
}
@ -199,6 +206,9 @@ static int __init vf610_mscm_ir_of_init(struct device_node *node,
goto out_unmap;
}
if (of_device_is_compatible(domain->parent->of_node, "arm,armv7m-nvic"))
mscm_ir_data->is_nvic = true;
cpu_pm_register_notifier(&mscm_ir_notifier_block);
return 0;

2
drivers/irqchip/irq-vic.c
View file

@ -256,7 +256,7 @@ static void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
} while (handled);
}
static struct irq_domain_ops vic_irqdomain_ops = {
static const struct irq_domain_ops vic_irqdomain_ops = {
.map = vic_irqdomain_map,
.xlate = irq_domain_xlate_onetwocell,
};

2
drivers/irqchip/irq-vt8500.c
View file

@ -173,7 +173,7 @@ static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
return 0;
}
static struct irq_domain_ops vt8500_irq_domain_ops = {
static const struct irq_domain_ops vt8500_irq_domain_ops = {
.map = vt8500_irq_map,
.xlate = irq_domain_xlate_onecell,
};

3
drivers/irqchip/spear-shirq.c
View file

@ -207,8 +207,7 @@ static void __init spear_shirq_register(struct spear_shirq *shirq,
if (!shirq->irq_chip)
return;
irq_set_chained_handler(parent_irq, shirq_handler);
irq_set_handler_data(parent_irq, shirq);
irq_set_chained_handler_and_data(parent_irq, shirq_handler, shirq);
for (i = 0; i < shirq->nr_irqs; i++) {
irq_set_chip_and_handler(shirq->virq_base + i,