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Merge "ARM: dts: msm: Add ddr qos devfreq device to lahaina gpu"

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This commit is contained in:
qctecmdr 2021-01-14 06:21:52 -08:00 • committed by Gerrit - the friendly Code Review server
commit 40a36781c1
2 changed files with 54 additions and 2 deletions
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34
qcom/lahaina-gpu.dtsi
View file

@ -9,6 +9,13 @@
memory-region = <&pil_gpu_mem>;
};
kgsl_ddr_qos: qcom,kgsl-ddr-qos {
compatible = "qcom,devfreq-qoslat";
governor = "powersave";
operating-points-v2 = <&qoslat_opp_table>;
mboxes = <&qmp_aop 0>;
};
msm_gpu: qcom,kgsl-3d0@3d00000 {
compatible = "qcom,kgsl-3d0";
status = "ok"
@ -57,8 +64,9 @@
qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr";
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
interconnect-names = "gpu_icc_path";
interconnect-names = "gpu_icc_path", "l3_path";
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>,
<&epss_l3_cpu MASTER_EPSS_L3_APPS &epss_l3_cpu SLAVE_EPSS_L3_SHARED>;
qcom,bus-table-ddr7 =
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
@ -93,6 +101,28 @@
<0>, /* Off */
<100>; /* On */
qcom,l3-pwrlevels {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,l3-pwrlevels";
qcom,l3-pwrlevel@0 {
reg = <0>;
qcom,l3-freq = <0>;
};
qcom,l3-pwrlevel@1 {
reg = <1>;
qcom,l3-freq = <614400000>;
};
qcom,l3-pwrlevel@2 {
reg = <2>;
qcom,l3-freq = <1516800000>;
};
};
qcom,gpu-mempools {
#address-cells = <1>;
#size-cells = <0>;

22
qcom/lahaina-v2-gpu.dtsi
View file

@ -4,6 +4,28 @@
/delete-property/qcom,initial-pwrlevel;
/delete-node/qcom,gpu-pwrlevels;
qcom,l3-pwrlevels {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,l3-pwrlevels";
qcom,l3-pwrlevel@0 {
reg = <0>;
qcom,l3-freq = <0>;
};
qcom,l3-pwrlevel@1 {
reg = <1>;
qcom,l3-freq = <614400000>;
};
qcom,l3-pwrlevel@2 {
reg = <2>;
qcom,l3-freq = <1593600000>;
};
};
/* Power levels bins */
qcom,gpu-pwrlevel-bins {
compatible="qcom,gpu-pwrlevel-bins";