From 40bc88748d65d5312ec294e43df689f02745c04a Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Wed, 19 Feb 2020 18:26:15 -0800 Subject: [PATCH] clk: qcom: remove flags for byte div clk src The change removes CLK_SET_RATE_PARENT flag for byte div clk src dividers, as it would result in a set rate of byte clock again after it has been set to the required rate. Change-Id: Iff81adf9df2ad5457cc947190e5c10768fd5b270 Signed-off-by: Satya Rama Aditya Pinapala --- drivers/clk/qcom/dispcc-lahaina.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/clk/qcom/dispcc-lahaina.c b/drivers/clk/qcom/dispcc-lahaina.c index 41c03d5b7628..eb9b6ee4dbbc 100644 --- a/drivers/clk/qcom/dispcc-lahaina.c +++ b/drivers/clk/qcom/dispcc-lahaina.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -805,7 +805,6 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_regmap_div_ops, }, }; @@ -820,7 +819,6 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { .hw = &disp_cc_mdss_byte1_clk_src.clkr.hw, }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_regmap_div_ops, }, };