From 0b2074ce23f7b81db5373521e20afd0aa8601998 Mon Sep 17 00:00:00 2001 From: Jack Pham Date: Tue, 28 Jan 2020 22:07:57 -0800 Subject: [PATCH] ARM: dts: msm: Fix USB PHY resets The HS and SS PHY devices were pointing to the wrong reset instances. Change-Id: I40a4764b5dc694aed85a506d5cb942f90cc480ab --- qcom/lahaina-usb.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi index e94628ce378c..9b357e34f4a7 100644 --- a/qcom/lahaina-usb.dtsi +++ b/qcom/lahaina-usb.dtsi @@ -112,7 +112,7 @@ clocks = <&clock_rpmh RPMH_CXO_CLK>; clock-names = "ref_clk_src"; - resets = <&clock_gcc GCC_USB3_PHY_PRIM_BCR>; + resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>; reset-names = "phy_reset"; }; @@ -138,7 +138,7 @@ "com_aux_clk"; resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&clock_gcc GCC_USB3PHY_PHY_PRIM_BCR>; + <&clock_gcc GCC_USB3_PHY_PRIM_BCR>; reset-names = "global_phy_reset", "phy_reset"; qcom,qmp-phy-reg-offset = ; clock-names = "ref_clk_src"; - resets = <&clock_gcc GCC_USB3_PHY_SEC_BCR>; + resets = <&clock_gcc GCC_QUSB2PHY_SEC_BCR>; reset-names = "phy_reset"; }; @@ -416,7 +416,7 @@ "pipe_clk_ext_src", "ref_clk_src", "ref_clk", "com_aux_clk"; - resets = <&clock_gcc GCC_USB3_DP_PHY_SEC_BCR>, + resets = <&clock_gcc GCC_USB3_PHY_SEC_BCR>, <&clock_gcc GCC_USB3PHY_PHY_SEC_BCR>; reset-names = "phy_reset", "phy_phy_reset"; qcom,qmp-phy-reg-offset =