diff --git a/bindings/cpufreq/cpufreq-qcom-hw.txt b/bindings/cpufreq/cpufreq-qcom-hw.txt
index 251ea7dcca40..4ece108cbbb0 100644
--- a/bindings/cpufreq/cpufreq-qcom-hw.txt
+++ b/bindings/cpufreq/cpufreq-qcom-hw.txt
@@ -50,6 +50,12 @@ Properties:
 			should have the "pdmem-domainX" to indicate the
 			corresponding bases.
 
+- qcom,sdpm-cx-mx-<id>
+	Usage:		Optional
+	Value type:	<prop-encoded-array>
+	Definition:	Addresses and sizes for the SDPM memory of the HW bases
+			in each frequency domain, indicated by an "id"(0/1/2).
+
 * Property qcom,freq-domain
 Devices supporting freq-domain must set their "qcom,freq-domain" property with
 phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node.
@@ -181,6 +187,8 @@ DCVS state together.
 
 		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
 		clock-names = "xo", "alternate";
+		qcom,sdpm-cx-mx-1 = <0x00636f08 0x4>;
+		qcom,sdpm-cx-mx-2 = <0x00636f0c 0x4>;
 
 		#freq-domain-cells = <1>;
 	};
diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi
index dabe7c2b05d4..0e2b511671a1 100644
--- a/qcom/yupik.dtsi
+++ b/qcom/yupik.dtsi
@@ -1162,6 +1162,9 @@
 				<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "dcvsh0_int", "dcvsh1_int", "dcvsh2_int";
 
+		qcom,sdpm-cx-mx-1 = <0x00636f08 0x4>;
+		qcom,sdpm-cx-mx-2 = <0x00636f0c 0x4>;
+
 		#freq-domain-cells = <2>;
 	};