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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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msm: pcie: replace all memory barriers with readbacks
Memory barrier cannot fully guarantee the write has completed before issuing the next one. Replace all memory barriers with readbacks to ensure the writes have completed. Change-Id: I5d9f3b5df4786d7d4bca096ce04aff83ddc2d381 Signed-off-by: Tony Truong <truong@codeaurora.org>
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Tony Truong
Gerrit - the friendly Code Review server
parent
f9c0b494bb
commit
4119f9fbde
1 changed files with 47 additions and 58 deletions
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@ -980,7 +980,7 @@ static void msm_pcie_write_reg(void __iomem *base, u32 offset, u32 value)
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{
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writel_relaxed(value, base + offset);
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/* ensure that changes propagated to the hardware */
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wmb();
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readl_relaxed(base + offset);
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}
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static void msm_pcie_write_reg_field(void __iomem *base, u32 offset,
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@ -993,7 +993,7 @@ static void msm_pcie_write_reg_field(void __iomem *base, u32 offset,
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val = tmp | (val << shift);
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writel_relaxed(val, base + offset);
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/* ensure that changes propagated to the hardware */
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wmb();
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readl_relaxed(base + offset);
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}
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static void msm_pcie_config_clear_set_dword(struct pci_dev *pdev,
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@ -1016,24 +1016,24 @@ static void msm_pcie_rumi_init(struct msm_pcie_dev_t *pcie_dev)
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PCIE_DBG(pcie_dev, "PCIe: RC%d: enter.\n", pcie_dev->rc_idx);
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val = readl_relaxed(pcie_dev->rumi + phy_ctrl_offs) | 0x1000;
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writel_relaxed(val, pcie_dev->rumi + phy_ctrl_offs);
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msm_pcie_write_reg(pcie_dev->rumi, phy_ctrl_offs, val);
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usleep_range(10000, 10001);
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writel_relaxed(0x800, pcie_dev->rumi + reset_offs);
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msm_pcie_write_reg(pcie_dev->rumi, reset_offs, 0x800);
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usleep_range(50000, 50001);
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writel_relaxed(0xFFFFFFFF, pcie_dev->rumi + reset_offs);
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msm_pcie_write_reg(pcie_dev->rumi, reset_offs, 0xFFFFFFFF);
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usleep_range(50000, 50001);
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writel_relaxed(0x800, pcie_dev->rumi + reset_offs);
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msm_pcie_write_reg(pcie_dev->rumi, reset_offs, 0x800);
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usleep_range(50000, 50001);
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writel_relaxed(0, pcie_dev->rumi + reset_offs);
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msm_pcie_write_reg(pcie_dev->rumi, reset_offs, 0);
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usleep_range(50000, 50001);
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val = readl_relaxed(pcie_dev->rumi + phy_ctrl_offs) & 0xFFFFEFFF;
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writel_relaxed(val, pcie_dev->rumi + phy_ctrl_offs);
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msm_pcie_write_reg(pcie_dev->rumi, phy_ctrl_offs, val);
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usleep_range(10000, 10001);
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val = readl_relaxed(pcie_dev->rumi + phy_ctrl_offs) & 0xFFFFFFFE;
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writel_relaxed(val, pcie_dev->rumi + phy_ctrl_offs);
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msm_pcie_write_reg(pcie_dev->rumi, phy_ctrl_offs, val);
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}
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static void pcie_phy_dump(struct msm_pcie_dev_t *dev)
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@ -1148,9 +1148,7 @@ static void msm_pcie_cfg_recover(struct msm_pcie_dev_t *dev, bool rc)
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PCIE_DBG3(dev,
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"PCIe: shadow_dw[%d]:cfg 0x%x:0x%x\n",
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j, j * 4, val);
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writel_relaxed(val, cfg + j * 4);
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/* ensure changes propagated to the hardware */
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wmb();
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msm_pcie_write_reg(cfg, j * 4, val);
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PCIE_DBG3(dev,
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"PCIe: after recovery:cfg 0x%x:0x%x\n\n",
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j * 4, readl_relaxed(cfg + j * 4));
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@ -1171,7 +1169,8 @@ static void msm_pcie_write_mask(void __iomem *addr,
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val = (readl_relaxed(addr) & ~clear_mask) | set_mask;
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writel_relaxed(val, addr);
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wmb(); /* ensure data is written to hardware register */
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/* ensure data is written to hardware register */
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readl_relaxed(addr);
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}
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static void pcie_parf_dump(struct msm_pcie_dev_t *dev)
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@ -1191,7 +1190,7 @@ static void pcie_parf_dump(struct msm_pcie_dev_t *dev)
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readl_relaxed(dev->parf + PCIE20_PARF_SYS_CTRL),
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readl_relaxed(dev->parf + PCIE20_PARF_TEST_BUS));
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}
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writel_relaxed(original, dev->parf + PCIE20_PARF_SYS_CTRL);
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msm_pcie_write_reg(dev->parf, PCIE20_PARF_SYS_CTRL, original);
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PCIE_DUMP(dev, "PCIe: RC%d PARF register dump\n", dev->rc_idx);
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@ -2660,33 +2659,23 @@ static void msm_pcie_iatu_config(struct msm_pcie_dev_t *dev, int nr, u8 type,
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}
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/* select region */
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if (iatu_viewport_offset) {
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writel_relaxed(nr, iatu_base + iatu_viewport_offset);
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/* ensure that hardware locks it */
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wmb();
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}
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if (iatu_viewport_offset)
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msm_pcie_write_reg(iatu_base, iatu_viewport_offset, nr);
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/* switch off region before changing it */
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writel_relaxed(0, iatu_base + iatu_ctrl2_offset);
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/* and wait till it propagates to the hardware */
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wmb();
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msm_pcie_write_reg(iatu_base, iatu_ctrl2_offset, 0);
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writel_relaxed(type, iatu_base + iatu_ctrl1_offset);
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writel_relaxed(lower_32_bits(host_addr),
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iatu_base + iatu_lbar_offset);
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writel_relaxed(upper_32_bits(host_addr),
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iatu_base + iatu_ubar_offset);
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writel_relaxed(host_end, iatu_base + iatu_lar_offset);
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writel_relaxed(lower_32_bits(target_addr),
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iatu_base + iatu_ltar_offset);
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writel_relaxed(upper_32_bits(target_addr),
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iatu_base + iatu_utar_offset);
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/* ensure that changes propagated to the hardware */
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wmb();
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writel_relaxed(BIT(31), iatu_base + iatu_ctrl2_offset);
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/* ensure that changes propagated to the hardware */
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wmb();
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msm_pcie_write_reg(iatu_base, iatu_ctrl1_offset, type);
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msm_pcie_write_reg(iatu_base, iatu_lbar_offset,
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lower_32_bits(host_addr));
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msm_pcie_write_reg(iatu_base, iatu_ubar_offset,
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upper_32_bits(host_addr));
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msm_pcie_write_reg(iatu_base, iatu_lar_offset, host_end);
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msm_pcie_write_reg(iatu_base, iatu_ltar_offset,
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lower_32_bits(target_addr));
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msm_pcie_write_reg(iatu_base, iatu_utar_offset,
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upper_32_bits(target_addr));
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msm_pcie_write_reg(iatu_base, iatu_ctrl2_offset, BIT(31));
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if (dev->enumerated) {
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PCIE_DBG2(dev, "IATU for Endpoint %02x:%02x.%01x\n",
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@ -2872,8 +2861,7 @@ static int msm_pcie_oper_conf(struct pci_bus *bus, u32 devfn, int oper,
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if ((bus->number == 0) && (where == 0x3c))
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wr_val = wr_val | (3 << 16);
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writel_relaxed(wr_val, config_base + word_offset);
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wmb(); /* ensure config data is written to hardware register */
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msm_pcie_write_reg(config_base, word_offset, wr_val);
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if (dev->shadow_en) {
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if (rd_val == PCIE_LINK_DOWN &&
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@ -4158,9 +4146,9 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev)
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msm_pcie_write_mask(dev->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);
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/* change DBI base address */
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writel_relaxed(0, dev->parf + PCIE20_PARF_DBI_BASE_ADDR);
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msm_pcie_write_reg(dev->parf, PCIE20_PARF_DBI_BASE_ADDR, 0);
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writel_relaxed(0x365E, dev->parf + PCIE20_PARF_SYS_CTRL);
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msm_pcie_write_reg(dev->parf, PCIE20_PARF_SYS_CTRL, 0x365E);
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msm_pcie_write_mask(dev->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL,
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0, BIT(4));
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@ -4186,8 +4174,8 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev)
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dev->rc_idx,
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readl_relaxed(dev->parf + PCIE20_PARF_INT_ALL_MASK));
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writel_relaxed(dev->slv_addr_space_size, dev->parf +
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PCIE20_PARF_SLV_ADDR_SPACE_SIZE);
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msm_pcie_write_reg(dev->parf, PCIE20_PARF_SLV_ADDR_SPACE_SIZE,
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dev->slv_addr_space_size);
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val = dev->wr_halt_size ? dev->wr_halt_size :
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readl_relaxed(dev->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
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@ -4496,9 +4484,9 @@ static void msm_pcie_config_sid(struct msm_pcie_dev_t *dev)
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if (dev->enumerated) {
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for (i = 0; i < dev->sid_info_len; i++)
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writel_relaxed(dev->sid_info[i].value,
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bdf_to_sid_base + dev->sid_info[i].hash *
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sizeof(u32));
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msm_pcie_write_reg(bdf_to_sid_base,
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dev->sid_info[i].hash * sizeof(u32),
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dev->sid_info[i].value);
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return;
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}
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@ -4524,8 +4512,8 @@ static void msm_pcie_config_sid(struct msm_pcie_dev_t *dev)
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int j;
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val |= (u32)hash;
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writel_relaxed(val, bdf_to_sid_base +
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current_hash * sizeof(u32));
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msm_pcie_write_reg(bdf_to_sid_base,
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current_hash * sizeof(u32), val);
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/* sid_info of current hash and update it */
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for (j = 0; j < dev->sid_info_len; j++) {
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@ -4545,7 +4533,7 @@ static void msm_pcie_config_sid(struct msm_pcie_dev_t *dev)
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/* BDF [31:16] | SID [15:8] | NEXT [7:0] */
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val = sid_info->bdf << 16 | sid_info->pcie_sid << 8 | 0;
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writel_relaxed(val, bdf_to_sid_base + hash * sizeof(u32));
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msm_pcie_write_reg(bdf_to_sid_base, hash * sizeof(u32), val);
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sid_info->hash = hash;
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sid_info->value = val;
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@ -6598,29 +6586,30 @@ static void __msm_pcie_l1ss_timeout_disable(struct msm_pcie_dev_t *pcie_dev)
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{
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msm_pcie_write_mask(pcie_dev->parf + PCIE20_PARF_DEBUG_INT_EN, BIT(0),
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0);
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writel_relaxed(0, pcie_dev->parf + PCIE20_PARF_L1SUB_AHB_CLK_MAX_TIMER);
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msm_pcie_write_reg(pcie_dev->parf, PCIE20_PARF_L1SUB_AHB_CLK_MAX_TIMER,
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0);
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}
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static void __msm_pcie_l1ss_timeout_enable(struct msm_pcie_dev_t *pcie_dev)
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{
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u32 val = BIT(31);
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writel_relaxed(val, pcie_dev->parf +
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PCIE20_PARF_L1SUB_AHB_CLK_MAX_TIMER);
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msm_pcie_write_reg(pcie_dev->parf, PCIE20_PARF_L1SUB_AHB_CLK_MAX_TIMER,
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val);
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/* 3 AUX clock cycles so that RESET will sync with timer logic */
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usleep_range(3, 4);
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val |= L1SS_TIMEOUT_US_TO_TICKS(L1SS_TIMEOUT_US);
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writel_relaxed(val, pcie_dev->parf +
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PCIE20_PARF_L1SUB_AHB_CLK_MAX_TIMER);
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msm_pcie_write_reg(pcie_dev->parf, PCIE20_PARF_L1SUB_AHB_CLK_MAX_TIMER,
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val);
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/* 1 AUX clock cycle so that CNT_MAX will sync with timer logic */
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usleep_range(1, 2);
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val &= ~BIT(31);
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writel_relaxed(val, pcie_dev->parf +
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PCIE20_PARF_L1SUB_AHB_CLK_MAX_TIMER);
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msm_pcie_write_reg(pcie_dev->parf, PCIE20_PARF_L1SUB_AHB_CLK_MAX_TIMER,
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val);
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msm_pcie_write_mask(pcie_dev->parf +
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PCIE20_PARF_DEBUG_INT_EN, 0, BIT(0));
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