diff --git a/drivers/gpu/msm/adreno-gpulist.h b/drivers/gpu/msm/adreno-gpulist.h index 7d5c269af96a..f18c43715ef2 100644 --- a/drivers/gpu/msm/adreno-gpulist.h +++ b/drivers/gpu/msm/adreno-gpulist.h @@ -30,6 +30,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306 = { .gmem_size = SZ_128K, .busy_mask = 0x7ffffffe, .bus_width = 0, + .snapshot_size = 600 * SZ_1K, }, .pm4fw_name = "a300_pm4.fw", .pfpfw_name = "a300_pfp.fw", @@ -52,6 +53,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306a = { .gmem_size = SZ_128K, .busy_mask = 0x7ffffffe, .bus_width = 16, + .snapshot_size = 600 * SZ_1K, }, .pm4fw_name = "a300_pm4.fw", .pfpfw_name = "a300_pfp.fw", @@ -72,6 +74,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a304 = { .gmem_size = (SZ_64K + SZ_32K), .busy_mask = 0x7ffffffe, .bus_width = 0, + .snapshot_size = 600 * SZ_1K, }, .pm4fw_name = "a300_pm4.fw", .pfpfw_name = "a300_pfp.fw", @@ -196,6 +199,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v2 = { .gmem_size = SZ_1M, .busy_mask = 0xfffffffe, .bus_width = 32, + .snapshot_size = SZ_1M, }, .gpmu_tsens = 0x00060007, .max_power = 5448, @@ -208,6 +212,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v2 = { .hwcg_count = ARRAY_SIZE(a530_hwcg_regs), .vbif = a530_vbif_regs, .vbif_count = ARRAY_SIZE(a530_vbif_regs), + .highest_bank_bit = 15, }; static const struct adreno_a5xx_core adreno_gpu_core_a530v3 = { @@ -221,6 +226,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v3 = { .gmem_size = SZ_1M, .busy_mask = 0xfffffffe, .bus_width = 32, + .snapshot_size = SZ_1M, }, .gpmu_tsens = 0x00060007, .max_power = 5448, @@ -233,6 +239,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v3 = { .hwcg_count = ARRAY_SIZE(a530_hwcg_regs), .vbif = a530_vbif_regs, .vbif_count = ARRAY_SIZE(a530_vbif_regs), + .highest_bank_bit = 15, }; /* For a505, a506 and a508 */ @@ -286,6 +293,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a505 = { .gmem_size = (SZ_128K + SZ_8K), .busy_mask = 0xfffffffe, .bus_width = 16, + .snapshot_size = SZ_1M, }, .pm4fw_name = "a530_pm4.fw", .pfpfw_name = "a530_pfp.fw", @@ -305,6 +313,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a506 = { .gmem_size = (SZ_128K + SZ_8K), .busy_mask = 0xfffffffe, .bus_width = 16, + .snapshot_size = SZ_1M, }, .pm4fw_name = "a530_pm4.fw", .pfpfw_name = "a530_pfp.fw", @@ -313,6 +322,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a506 = { .hwcg_count = ARRAY_SIZE(a50x_hwcg_regs), .vbif = a530_vbif_regs, .vbif_count = ARRAY_SIZE(a530_vbif_regs), + .highest_bank_bit = 14, }; static const struct adreno_reglist a510_hwcg_regs[] = { @@ -382,6 +392,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a510 = { .gmem_size = SZ_256K, .busy_mask = 0xfffffffe, .bus_width = 16, + .snapshot_size = SZ_1M, }, .pm4fw_name = "a530_pm4.fw", .pfpfw_name = "a530_pfp.fw", @@ -507,6 +518,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a540v2 = { .gmem_size = SZ_1M, .busy_mask = 0xfffffffe, .bus_width = 32, + .snapshot_size = SZ_1M, }, .gpmu_tsens = 0x000c000d, .max_power = 5448, @@ -518,6 +530,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a540v2 = { .hwcg_count = ARRAY_SIZE(a540_hwcg_regs), .vbif = a540_vbif_regs, .vbif_count = ARRAY_SIZE(a540_vbif_regs), + .highest_bank_bit = 15, }; static const struct adreno_reglist a512_hwcg_regs[] = { @@ -589,12 +602,14 @@ static const struct adreno_a5xx_core adreno_gpu_core_a512 = { .gmem_size = (SZ_256K + SZ_16K), .busy_mask = 0xfffffffe, .bus_width = 32, + .snapshot_size = SZ_1M, }, .pm4fw_name = "a530_pm4.fw", .pfpfw_name = "a530_pfp.fw", .zap_name = "a512_zap", .hwcg = a512_hwcg_regs, .hwcg_count = ARRAY_SIZE(a512_hwcg_regs), + .highest_bank_bit = 14, }; static const struct adreno_a5xx_core adreno_gpu_core_a508 = { @@ -607,6 +622,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a508 = { .gmem_size = (SZ_128K + SZ_8K), .busy_mask = 0xfffffffe, .bus_width = 32, + .snapshot_size = SZ_1M, }, .pm4fw_name = "a530_pm4.fw", .pfpfw_name = "a530_pfp.fw", @@ -615,6 +631,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a508 = { .hwcg_count = ARRAY_SIZE(a50x_hwcg_regs), .vbif = a530_vbif_regs, .vbif_count = ARRAY_SIZE(a530_vbif_regs), + .highest_bank_bit = 14, }; DEFINE_DEPRECATED_CORE(a630v1, ADRENO_REV_A630, 6, 3, 0, 0); @@ -781,6 +798,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = { .gmem_size = SZ_1M, .busy_mask = 0xfffffffe, .bus_width = 32, + .snapshot_size = SZ_1M, }, .prim_fifo_threshold = 0x0018000, .pdc_address_offset = 0x00030080, @@ -795,6 +813,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = { .vbif_count = ARRAY_SIZE(a630_vbif_regs), .hang_detect_cycles = 0xcfffff, .protected_regs = a630_protected_regs, + .highest_bank_bit = 15, }; /* For a615, a616 and a618 */ @@ -880,6 +899,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a615 = { .gmem_size = SZ_512K, .busy_mask = 0xfffffffe, .bus_width = 32, + .snapshot_size = 600 * SZ_1K, }, .prim_fifo_threshold = 0x0018000, .pdc_address_offset = 0x00030080, @@ -894,6 +914,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a615 = { .vbif_count = ARRAY_SIZE(a615_gbif_regs), .hang_detect_cycles = 0xcfffff, .protected_regs = a630_protected_regs, + .highest_bank_bit = 14, }; static const struct adreno_a6xx_core adreno_gpu_core_a618 = { @@ -907,6 +928,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a618 = { .gmem_size = SZ_512K, .busy_mask = 0xfffffffe, .bus_width = 32, + .snapshot_size = SZ_1M, }, .prim_fifo_threshold = 0x0018000, .pdc_address_offset = 0x00030090, @@ -921,6 +943,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a618 = { .vbif_count = ARRAY_SIZE(a615_gbif_regs), .hang_detect_cycles = 0x3fffff, .protected_regs = a630_protected_regs, + .highest_bank_bit = 14, }; static const struct adreno_reglist a620_hwcg_regs[] = { @@ -1035,6 +1058,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a620 = { .gmem_size = SZ_512K, .busy_mask = 0xfffffffe, .bus_width = 32, + .snapshot_size = 2 * SZ_1M, }, .prim_fifo_threshold = 0x0010000, .pdc_address_offset = 0x000300a0, @@ -1051,6 +1075,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a620 = { .hang_detect_cycles = 0x3ffff, .protected_regs = a620_protected_regs, .disable_tseskip = true, + .highest_bank_bit = 14, }; static const struct adreno_reglist a640_hwcg_regs[] = { @@ -1125,6 +1150,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a640 = { .gmem_size = SZ_1M, //Verified 1MB .busy_mask = 0xfffffffe, .bus_width = 32, + .snapshot_size = 2 * SZ_1M, }, .prim_fifo_threshold = 0x00200000, .pdc_address_offset = 0x00030090, @@ -1140,6 +1166,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a640 = { .hang_detect_cycles = 0xcfffff, .protected_regs = a630_protected_regs, .disable_tseskip = true, + .highest_bank_bit = 15, }; static const struct adreno_reglist a650_hwcg_regs[] = { @@ -1205,6 +1232,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650 = { .gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */ .busy_mask = 0xfffffffe, .bus_width = 32, + .snapshot_size = 2 * SZ_1M, }, .prim_fifo_threshold = 0x00300000, .pdc_address_offset = 0x000300A0, @@ -1220,6 +1248,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650 = { .hang_detect_cycles = 0xcfffff, .protected_regs = a620_protected_regs, .disable_tseskip = true, + .highest_bank_bit = 16, }; static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = { @@ -1234,6 +1263,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = { .gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */ .busy_mask = 0xfffffffe, .bus_width = 32, + .snapshot_size = 2 * SZ_1M, }, .prim_fifo_threshold = 0x00300000, .pdc_address_offset = 0x000300A0, @@ -1249,6 +1279,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = { .hang_detect_cycles = 0x3ffff, .protected_regs = a620_protected_regs, .disable_tseskip = true, + .highest_bank_bit = 16, }; static const struct adreno_a6xx_core adreno_gpu_core_a680 = { @@ -1260,6 +1291,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = { .gmem_size = SZ_2M, .busy_mask = 0xfffffffe, .bus_width = 32, + .snapshot_size = SZ_1M, }, .prim_fifo_threshold = 0x00400000, .pdc_address_offset = 0x00030090, @@ -1275,6 +1307,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = { .hang_detect_cycles = 0xcfffff, .protected_regs = a630_protected_regs, .disable_tseskip = true, + .highest_bank_bit = 16, }; static const struct adreno_reglist a612_hwcg_regs[] = { @@ -1337,6 +1370,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a612 = { .gmem_size = (SZ_128K + SZ_4K), .busy_mask = 0xfffffffe, .bus_width = 32, + .snapshot_size = SZ_1M, }, .prim_fifo_threshold = 0x00080000, .pdc_address_offset = 0x00030080, @@ -1349,6 +1383,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a612 = { .vbif_count = ARRAY_SIZE(a640_vbif_regs), .hang_detect_cycles = 0x3fffff, .protected_regs = a630_protected_regs, + .highest_bank_bit = 14, }; static const struct adreno_a6xx_core adreno_gpu_core_a616 = { @@ -1362,6 +1397,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = { .gmem_size = SZ_512K, .busy_mask = 0xfffffffe, .bus_width = 32, + .snapshot_size = SZ_1M, }, .prim_fifo_threshold = 0x0018000, .pdc_address_offset = 0x00030080, @@ -1376,6 +1412,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = { .vbif_count = ARRAY_SIZE(a615_gbif_regs), .hang_detect_cycles = 0xcfffff, .protected_regs = a630_protected_regs, + .highest_bank_bit = 14, }; static const struct adreno_a6xx_core adreno_gpu_core_a610 = { @@ -1398,6 +1435,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a610 = { .vbif_count = ARRAY_SIZE(a640_vbif_regs), .hang_detect_cycles = 0x3ffff, .protected_regs = a630_protected_regs, + .highest_bank_bit = 14, }; static const struct adreno_gpu_core *adreno_gpulist[] = { diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c index 8c08415310db..5c1f34a38a13 100644 --- a/drivers/gpu/msm/adreno.c +++ b/drivers/gpu/msm/adreno.c @@ -46,9 +46,6 @@ static struct adreno_device device_3d0 = { .pwrscale = KGSL_PWRSCALE_INIT(&adreno_tz_data), .name = DEVICE_3D0_NAME, .id = 0, - .pwrctrl = { - .irq_name = "kgsl_3d0_irq", - }, .iomemname = "kgsl_3d0_reg_memory", .ftbl = &adreno_functable, }, @@ -1109,15 +1106,6 @@ static int adreno_of_get_power(struct adreno_device *adreno_dev, struct kgsl_device *device = KGSL_DEVICE(adreno_dev); struct device_node *node = pdev->dev.of_node; struct resource *res; - unsigned int timeout; - - if (of_property_read_string(node, "label", &pdev->name)) { - dev_err(device->dev, "Unable to read 'label'\n"); - return -EINVAL; - } - - if (adreno_of_read_property(device->dev, node, "qcom,id", &pdev->id)) - return -EINVAL; /* Get starting physical address of device registers */ res = platform_get_resource_byname(device->pdev, IORESOURCE_MEM, @@ -1144,10 +1132,8 @@ static int adreno_of_get_power(struct adreno_device *adreno_dev, l3_pwrlevel_probe(device, node); - if (of_property_read_u32(node, "qcom,idle-timeout", &timeout)) - timeout = 80; - - device->pwrctrl.interval_timeout = msecs_to_jiffies(timeout); + /* Default timeout is 80 ms across all targets */ + device->pwrctrl.interval_timeout = msecs_to_jiffies(80); device->pwrctrl.bus_control = of_property_read_bool(node, "qcom,bus-control"); @@ -1345,6 +1331,7 @@ static int adreno_probe(struct platform_device *pdev) struct kgsl_device *device; int status; unsigned int priv; + u32 size; of_id = of_match_device(adreno_match_table, &pdev->dev); if (!of_id) @@ -1441,6 +1428,19 @@ static int adreno_probe(struct platform_device *pdev) if (status) goto out; + /* Initialize the snapshot engine */ + size = adreno_dev->gpucore->snapshot_size; + + /* + * Use a default size if one wasn't specified, but print a warning so + * the developer knows to fix it + */ + + if (WARN(!size, "The snapshot size was not specified in the gpucore\n")) + size = SZ_1M; + + kgsl_device_snapshot_probe(device, size); + status = adreno_ringbuffer_probe(adreno_dev); if (status) goto out; @@ -3790,7 +3790,7 @@ static struct platform_driver adreno_platform_driver = { .resume = kgsl_resume_driver, .id_table = adreno_id_table, .driver = { - .name = DEVICE_3D_NAME, + .name = "kgsl-3d", .pm = &kgsl_pm_ops, .of_match_table = adreno_match_table, } diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h index 4da91ae742fa..d9ddfc6e7e3a 100644 --- a/drivers/gpu/msm/adreno.h +++ b/drivers/gpu/msm/adreno.h @@ -13,7 +13,6 @@ #include "adreno_ringbuffer.h" #include "kgsl_sharedmem.h" -#define DEVICE_3D_NAME "kgsl-3d" #define DEVICE_3D0_NAME "kgsl-3d0" /* ADRENO_DEVICE - Given a kgsl_device return the adreno device struct */ @@ -363,6 +362,8 @@ struct adreno_gpu_core { size_t gmem_size; unsigned int busy_mask; u32 bus_width; + /** @snapshot_size: Size of the static snapshot region in bytes */ + u32 snapshot_size; }; /** diff --git a/drivers/gpu/msm/adreno_a5xx.c b/drivers/gpu/msm/adreno_a5xx.c index 75cba7ef3776..e18197d56fae 100644 --- a/drivers/gpu/msm/adreno_a5xx.c +++ b/drivers/gpu/msm/adreno_a5xx.c @@ -210,21 +210,13 @@ static int a5xx_critical_packet_construct(struct adreno_device *adreno_dev) static void a5xx_init(struct adreno_device *adreno_dev) { - struct kgsl_device *device = KGSL_DEVICE(adreno_dev); - - of_property_read_u32(device->pdev->dev.of_node, - "qcom,highest-bank-bit", &adreno_dev->highest_bank_bit); - - if (WARN(adreno_dev->highest_bank_bit < 13 || - adreno_dev->highest_bank_bit > 16, - "The highest-bank-bit property is invalid\n")) - adreno_dev->highest_bank_bit = - clamp_t(unsigned int, adreno_dev->highest_bank_bit, - 13, 16); + const struct adreno_a5xx_core *a5xx_core = to_a5xx_core(adreno_dev); if (ADRENO_FEATURE(adreno_dev, ADRENO_GPMU)) INIT_WORK(&adreno_dev->gpmu_work, a5xx_gpmu_reset); + adreno_dev->highest_bank_bit = a5xx_core->highest_bank_bit; + INIT_WORK(&adreno_dev->irq_storm_work, a5xx_irq_storm_worker); if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_CRITICAL_PACKETS)) { @@ -1557,7 +1549,6 @@ static void a5xx_start(struct adreno_device *adreno_dev) kgsl_regwrite(device, A5XX_RBBM_AHB_CNTL2, 0x0000003F); bit = adreno_dev->highest_bank_bit ? (adreno_dev->highest_bank_bit - 13) & 0x03 : 0; - /* * Program the highest DDR bank bit that was passed in * from the DT in a handful of registers. Some of these diff --git a/drivers/gpu/msm/adreno_a5xx.h b/drivers/gpu/msm/adreno_a5xx.h index 7ab85059c37a..b7d5d64e7ef1 100644 --- a/drivers/gpu/msm/adreno_a5xx.h +++ b/drivers/gpu/msm/adreno_a5xx.h @@ -36,6 +36,8 @@ struct adreno_a5xx_core { const struct adreno_reglist *vbif; /** @vbif_count: Number of registers in @vbif */ u32 vbif_count; + /** @highest_bank_bit: The bit of the highest DDR bank */ + u32 highest_bank_bit; }; #define A5XX_CP_CTXRECORD_MAGIC_REF 0x27C4BAFCUL diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c index e2fe21fe2876..518fff771c95 100644 --- a/drivers/gpu/msm/adreno_a6xx.c +++ b/drivers/gpu/msm/adreno_a6xx.c @@ -104,20 +104,11 @@ static u32 a612_pwrup_reglist[] = { static void a6xx_init(struct adreno_device *adreno_dev) { + const struct adreno_a6xx_core *a6xx_core = to_a6xx_core(adreno_dev); struct kgsl_device *device = KGSL_DEVICE(adreno_dev); - adreno_dev->highest_bank_bit = 13; - of_property_read_u32(device->pdev->dev.of_node, - "qcom,highest-bank-bit", &adreno_dev->highest_bank_bit); + adreno_dev->highest_bank_bit = a6xx_core->highest_bank_bit; - if (WARN(adreno_dev->highest_bank_bit < 13 || - adreno_dev->highest_bank_bit > 16, - "The highest-bank-bit property is invalid\n")) - adreno_dev->highest_bank_bit = - clamp_t(unsigned int, adreno_dev->highest_bank_bit, - 13, 16); - - /* LP DDR4 highest bank bit is different and needs to be overridden */ if (adreno_is_a650(adreno_dev) && of_fdt_get_ddrtype() == 0x7) adreno_dev->highest_bank_bit = 15; @@ -345,7 +336,7 @@ static void a6xx_start(struct adreno_device *adreno_dev) { struct kgsl_device *device = KGSL_DEVICE(adreno_dev); const struct adreno_a6xx_core *a6xx_core = to_a6xx_core(adreno_dev); - unsigned int bit, lower_bit, mal, mode, upper_bit; + unsigned int mal, mode, hbb_hi = 0, hbb_lo = 0; unsigned int uavflagprd_inv; unsigned int amsbc = 0; unsigned int rgb565_predicator = 0; @@ -481,27 +472,28 @@ static void a6xx_start(struct adreno_device *adreno_dev) break; } - bit = adreno_dev->highest_bank_bit ? - adreno_dev->highest_bank_bit - 13 : 0; - lower_bit = bit & 0x3; - upper_bit = (bit >> 0x2) & 1; + if (!WARN_ON(!adreno_dev->highest_bank_bit)) { + hbb_lo = (adreno_dev->highest_bank_bit - 13) & 3; + hbb_hi = ((adreno_dev->highest_bank_bit - 13) >> 2) & 1; + } + mal = (mal == 64) ? 1 : 0; uavflagprd_inv = (adreno_is_a650_family(adreno_dev)) ? 2 : 0; kgsl_regwrite(device, A6XX_RB_NC_MODE_CNTL, (rgb565_predicator << 11)| - (upper_bit << 10) | (amsbc << 4) | (mal << 3) | - (lower_bit << 1) | mode); + (hbb_hi << 10) | (amsbc << 4) | (mal << 3) | + (hbb_lo << 1) | mode); - kgsl_regwrite(device, A6XX_TPL1_NC_MODE_CNTL, (upper_bit << 4) | - (mal << 3) | (lower_bit << 1) | mode); + kgsl_regwrite(device, A6XX_TPL1_NC_MODE_CNTL, (hbb_hi << 4) | + (mal << 3) | (hbb_lo << 1) | mode); - kgsl_regwrite(device, A6XX_SP_NC_MODE_CNTL, (upper_bit << 10) | + kgsl_regwrite(device, A6XX_SP_NC_MODE_CNTL, (hbb_hi << 10) | (mal << 3) | (uavflagprd_inv << 4) | - (lower_bit << 1) | mode); + (hbb_lo << 1) | mode); kgsl_regwrite(device, A6XX_UCHE_MODE_CNTL, (mal << 23) | - (lower_bit << 21)); + (hbb_lo << 21)); kgsl_regwrite(device, A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | a6xx_core->hang_detect_cycles); diff --git a/drivers/gpu/msm/adreno_a6xx.h b/drivers/gpu/msm/adreno_a6xx.h index 7f84c58d7dab..07b7d5922516 100644 --- a/drivers/gpu/msm/adreno_a6xx.h +++ b/drivers/gpu/msm/adreno_a6xx.h @@ -68,6 +68,8 @@ struct adreno_a6xx_core { const struct a6xx_protected_regs *protected_regs; /** @disable_tseskip: True if TSESkip logic is disabled */ bool disable_tseskip; + /** @highest_bank_bit: The bit of the highest DDR bank */ + u32 highest_bank_bit; }; #define CP_CLUSTER_FE 0x0 diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c index 4b3d6b94ccc0..0ee539844f2b 100644 --- a/drivers/gpu/msm/kgsl.c +++ b/drivers/gpu/msm/kgsl.c @@ -5019,7 +5019,7 @@ int kgsl_device_platform_probe(struct kgsl_device *device) goto error_pwrctrl_close; } - status = kgsl_request_irq(device->pdev, device->pwrctrl.irq_name, + status = kgsl_request_irq(device->pdev, "kgsl_3d0_irq", kgsl_irq_handler, device); if (status < 0) goto error_pwrctrl_close; @@ -5047,9 +5047,6 @@ int kgsl_device_platform_probe(struct kgsl_device *device) device->events_wq = alloc_workqueue("kgsl-events", WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0); - /* Initialize the snapshot engine */ - kgsl_device_snapshot_init(device); - /* Initialize common sysfs entries */ kgsl_pwrctrl_init_sysfs(device); diff --git a/drivers/gpu/msm/kgsl_device.h b/drivers/gpu/msm/kgsl_device.h index 2fc4acd0991a..48a7c0047dab 100644 --- a/drivers/gpu/msm/kgsl_device.h +++ b/drivers/gpu/msm/kgsl_device.h @@ -644,7 +644,16 @@ void kgsl_device_platform_remove(struct kgsl_device *device); const char *kgsl_pwrstate_to_str(unsigned int state); -int kgsl_device_snapshot_init(struct kgsl_device *device); +/** + * kgsl_device_snapshot_probe - add resources for the device GPU snapshot + * @device: The device to initialize + * @size: The size of the static region to allocate + * + * Allocate memory for a GPU snapshot for the specified device, + * and create the sysfs files to manage it + */ +void kgsl_device_snapshot_probe(struct kgsl_device *device, u32 size); + void kgsl_device_snapshot(struct kgsl_device *device, struct kgsl_context *context, bool gmu_fault); void kgsl_device_snapshot_close(struct kgsl_device *device); diff --git a/drivers/gpu/msm/kgsl_pwrctrl.h b/drivers/gpu/msm/kgsl_pwrctrl.h index b6761a57f256..5b0fe861cad3 100644 --- a/drivers/gpu/msm/kgsl_pwrctrl.h +++ b/drivers/gpu/msm/kgsl_pwrctrl.h @@ -88,7 +88,6 @@ struct kgsl_pwrlevel { * @interval_timeout - timeout in jiffies to be idle before a power event * @clock_times - Each GPU frequency's accumulated active time in us * @pcl - bus scale identifier - * @irq_name - resource name for the IRQ * @clk_stats - structure of clock statistics * @input_disable - To disable GPU wakeup on touch input event * @bus_control - true if the bus calculation is independent @@ -131,7 +130,6 @@ struct kgsl_pwrctrl { unsigned long interval_timeout; u64 clock_times[KGSL_MAX_PWRLEVELS]; uint32_t pcl; - const char *irq_name; struct kgsl_clk_stats clk_stats; bool input_disable; bool bus_control; diff --git a/drivers/gpu/msm/kgsl_snapshot.c b/drivers/gpu/msm/kgsl_snapshot.c index d12a0a76bbc3..5ef09944112b 100644 --- a/drivers/gpu/msm/kgsl_snapshot.c +++ b/drivers/gpu/msm/kgsl_snapshot.c @@ -1103,44 +1103,15 @@ static const struct attribute *snapshot_attrs[] = { NULL, }; -/** - * kgsl_device_snapshot_init() - add resources for the device GPU snapshot - * @device: The device to initialize - * - * Allocate memory for a GPU snapshot for the specified device, - * and create the sysfs files to manage it - */ -int kgsl_device_snapshot_init(struct kgsl_device *device) +void kgsl_device_snapshot_probe(struct kgsl_device *device, u32 size) { - int ret; - - device->snapshot_memory.size = KGSL_SNAPSHOT_MEMSIZE; - - of_property_read_u32(device->pdev->dev.of_node, - "qcom,snapshot-size", &device->snapshot_memory.size); - - /* - * Choosing a memory size of 0 is essentially the same as disabling - * snapshotting - */ - if (device->snapshot_memory.size == 0) - return 0; - - /* - * I'm not sure why anybody would choose to do so but make sure - * that we can at least fit the snapshot header in the requested - * region - */ - - if (device->snapshot_memory.size < sizeof(struct kgsl_snapshot_header)) - device->snapshot_memory.size = - sizeof(struct kgsl_snapshot_header); + device->snapshot_memory.size = size; device->snapshot_memory.ptr = kzalloc(device->snapshot_memory.size, GFP_KERNEL); - if (device->snapshot_memory.ptr == NULL) - return -ENOMEM; + if (!device->snapshot_memory.ptr) + return; device->snapshot = NULL; device->snapshot_faultcount = 0; @@ -1155,18 +1126,12 @@ int kgsl_device_snapshot_init(struct kgsl_device *device) */ device->prioritize_unrecoverable = false; - ret = kobject_init_and_add(&device->snapshot_kobj, &ktype_snapshot, - &device->dev->kobj, "snapshot"); - if (ret) - return ret; + if (kobject_init_and_add(&device->snapshot_kobj, &ktype_snapshot, + &device->dev->kobj, "snapshot")) + return; - ret = sysfs_create_bin_file(&device->snapshot_kobj, &snapshot_attr); - if (ret) - return ret; - - ret = sysfs_create_files(&device->snapshot_kobj, snapshot_attrs); - - return ret; + sysfs_create_bin_file(&device->snapshot_kobj, &snapshot_attr); + sysfs_create_files(&device->snapshot_kobj, snapshot_attrs); } /**