A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-14 00:24:41 -04:00
Code Issues Projects Releases Packages Wiki Activity

Merge "msm: pcie: add support for gcc_aggre_noc_pcie_*_axi_clk"

Browse source
This commit is contained in:
qctecmdr 2021-02-26 06:40:50 -08:00 • committed by Gerrit - the friendly Code Review server
commit 4255c3c603
1 changed files with 54 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

60
drivers/pci/controller/pci-msm.c
View file

@ -192,9 +192,9 @@
#define MAX_RC_NAME_LEN (15)
#define MSM_PCIE_MAX_VREG (5)
#define MSM_PCIE_VREG_0P9 (2)
#define MSM_PCIE_MAX_CLK (18)
#define MSM_PCIE_MAX_CLK (21)
#define MSM_PCIE_MAX_PIPE_CLK (1)
#define MAX_RC_NUM (4)
#define MAX_RC_NUM (5)
#define MAX_DEVICE_NUM (20)
#define PCIE_TLP_RD_SIZE (0x5)
#define PCIE_LOG_PAGES (50)
@ -936,6 +936,13 @@ msm_pcie_reset_info[MAX_RC_NUM][MSM_PCIE_MAX_RESET] = {
{NULL, "pcie_phy_com_reset", false},
{NULL, "pcie_phy_nocsr_com_phy_reset", false},
{NULL, "pcie_3_phy_reset", false}
},
{
{NULL, "pcie_4_core_reset", false},
{NULL, "pcie_phy_reset", false},
{NULL, "pcie_phy_com_reset", false},
{NULL, "pcie_phy_nocsr_com_phy_reset", false},
{NULL, "pcie_4_phy_reset", false}
}
};
@ -953,6 +960,9 @@ msm_pcie_pipe_reset_info[MAX_RC_NUM][MSM_PCIE_MAX_PIPE_RESET] = {
},
{
{NULL, "pcie_3_phy_pipe_reset", false}
},
{
{NULL, "pcie_4_phy_pipe_reset", false}
}
};
@ -977,7 +987,10 @@ static struct msm_pcie_clk_info_t
{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
{NULL, "pcie_phy_aux_clk", 0, false, false},
{NULL, "pcie_pipe_clk_mux", 0, false, false},
{NULL, "pcie_pipe_clk_ext_src", 0, false, false}
{NULL, "pcie_pipe_clk_ext_src", 0, false, false},
{NULL, "pcie_aggre_noc_south_sf_axi_clk", 0, false, false},
{NULL, "pcie_aggre_noc_4_axi_clk", 0, false, false},
{NULL, "pcie_0_pipediv2_clk", 0, false, false}
},
{
{NULL, "pcie_1_ref_clk_src", 0, false, false},
@ -997,7 +1010,10 @@ static struct msm_pcie_clk_info_t
{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
{NULL, "pcie_phy_aux_clk", 0, false, false},
{NULL, "pcie_pipe_clk_mux", 0, false, false},
{NULL, "pcie_pipe_clk_ext_src", 0, false, false}
{NULL, "pcie_pipe_clk_ext_src", 0, false, false},
{NULL, "pcie_aggre_noc_south_sf_axi_clk", 0, false, false},
{NULL, "pcie_aggre_noc_4_axi_clk", 0, false, false},
{NULL, "pcie_1_pipediv2_clk", 0, false, false}
},
{
{NULL, "pcie_2_ref_clk_src", 0, false, false},
@ -1017,7 +1033,10 @@ static struct msm_pcie_clk_info_t
{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
{NULL, "pcie_phy_aux_clk", 0, false, false},
{NULL, "pcie_pipe_clk_mux", 0, false, false},
{NULL, "pcie_pipe_clk_ext_src", 0, false, false}
{NULL, "pcie_pipe_clk_ext_src", 0, false, false},
{NULL, "pcie_aggre_noc_south_sf_axi_clk", 0, false, false},
{NULL, "pcie_aggre_noc_4_axi_clk", 0, false, false},
{NULL, "pcie_2_pipediv2_clk", 0, false, false}
},
{
{NULL, "pcie_3_ref_clk_src", 0, false, false},
@ -1037,7 +1056,33 @@ static struct msm_pcie_clk_info_t
{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
{NULL, "pcie_phy_aux_clk", 0, false, false},
{NULL, "pcie_pipe_clk_mux", 0, false, false},
{NULL, "pcie_pipe_clk_ext_src", 0, false, false}
{NULL, "pcie_pipe_clk_ext_src", 0, false, false},
{NULL, "pcie_aggre_noc_south_sf_axi_clk", 0, false, false},
{NULL, "pcie_aggre_noc_4_axi_clk", 0, false, false},
{NULL, "pcie_3_pipediv2_clk", 0, false, false}
},
{
{NULL, "pcie_4_ref_clk_src", 0, false, false},
{NULL, "pcie_4_aux_clk", 1010000, true, false},
{NULL, "pcie_4_cfg_ahb_clk", 0, true, false},
{NULL, "pcie_4_mstr_axi_clk", 0, true, false},
{NULL, "pcie_4_slv_axi_clk", 0, true, false},
{NULL, "pcie_4_ldo", 0, true, true},
{NULL, "pcie_4_smmu_clk", 0, false, false},
{NULL, "pcie_4_slv_q2a_axi_clk", 0, false, false},
{NULL, "pcie_4_sleep_clk", 0, false, false},
{NULL, "pcie_phy_refgen_clk", 0, false, false},
{NULL, "pcie_tbu_clk", 0, false, false},
{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false},
{NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false},
{NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false},
{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
{NULL, "pcie_phy_aux_clk", 0, false, false},
{NULL, "pcie_pipe_clk_mux", 0, false, false},
{NULL, "pcie_pipe_clk_ext_src", 0, false, false},
{NULL, "pcie_aggre_noc_south_sf_axi_clk", 0, false, false},
{NULL, "pcie_aggre_noc_4_axi_clk", 0, false, false},
{NULL, "pcie_4_pipediv2_clk", 0, false, false}
}
};
@ -1055,6 +1100,9 @@ static struct msm_pcie_clk_info_t
},
{
{NULL, "pcie_3_pipe_clk", 125000000, true, false},
},
{
{NULL, "pcie_4_pipe_clk", 125000000, true, false},
}
};