mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
Merge branch 'for-linus2' of git://git.profusion.mobi/users/lucas/linux-2.6
* 'for-linus2' of git://git.profusion.mobi/users/lucas/linux-2.6: Fix common misspellings
This commit is contained in:
Linus Torvalds
commit
42933bac11
2463 changed files with 4249 additions and 4249 deletions
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@ -1699,7 +1699,7 @@ int drm_mode_addfb(struct drm_device *dev,
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mutex_lock(&dev->mode_config.mutex);
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/* TODO check buffer is sufficently large */
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/* TODO check buffer is sufficiently large */
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/* TODO setup destructor callback */
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fb = dev->mode_config.funcs->fb_create(dev, file_priv, r);
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@ -1750,7 +1750,7 @@ int drm_mode_rmfb(struct drm_device *dev,
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mutex_lock(&dev->mode_config.mutex);
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obj = drm_mode_object_find(dev, *id, DRM_MODE_OBJECT_FB);
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/* TODO check that we realy get a framebuffer back. */
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/* TODO check that we really get a framebuffer back. */
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if (!obj) {
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DRM_ERROR("mode invalid framebuffer id\n");
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ret = -EINVAL;
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@ -551,7 +551,7 @@ EXPORT_SYMBOL(drm_mm_scan_add_block);
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* corrupted.
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*
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* When the scan list is empty, the selected memory nodes can be freed. An
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* immediatly following drm_mm_search_free with best_match = 0 will then return
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* immediately following drm_mm_search_free with best_match = 0 will then return
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* the just freed block (because its at the top of the free_stack list).
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*
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* Returns one if this block should be evicted, zero otherwise. Will always
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@ -630,7 +630,7 @@ typedef struct drm_i915_private {
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* Flag if the hardware appears to be wedged.
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*
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* This is set when attempts to idle the device timeout.
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* It prevents command submission from occuring and makes
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* It prevents command submission from occurring and makes
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* every pending request fail
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*/
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atomic_t wedged;
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@ -213,7 +213,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
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return MODE_PANEL;
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}
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/* only refuse the mode on non eDP since we have seen some wierd eDP panels
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/* only refuse the mode on non eDP since we have seen some weird eDP panels
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which are outside spec tolerances but somehow work by magic */
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if (!is_edp(intel_dp) &&
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(intel_dp_link_required(connector->dev, intel_dp, mode->clock)
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@ -230,7 +230,7 @@ struct intel_sdvo_set_target_input_args {
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} __attribute__((packed));
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/**
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* Takes a struct intel_sdvo_output_flags of which outputs are targetted by
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* Takes a struct intel_sdvo_output_flags of which outputs are targeted by
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* future output commands.
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*
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* Affected commands inclue SET_OUTPUT_TIMINGS_PART[12],
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@ -426,7 +426,7 @@ int mga_driver_load(struct drm_device *dev, unsigned long flags)
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* Bootstrap the driver for AGP DMA.
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*
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* \todo
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* Investigate whether there is any benifit to storing the WARP microcode in
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* Investigate whether there is any benefit to storing the WARP microcode in
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* AGP memory. If not, the microcode may as well always be put in PCI
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* memory.
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*
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@ -200,7 +200,7 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
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/* disable the fifo caches */
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pfifo->reassign(dev, false);
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/* Construct inital RAMFC for new channel */
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/* Construct initial RAMFC for new channel */
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ret = pfifo->create_context(chan);
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if (ret) {
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nouveau_channel_put(&chan);
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@ -278,7 +278,7 @@ nouveau_channel_put_unlocked(struct nouveau_channel **pchan)
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return;
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}
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/* noone wants the channel anymore */
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/* no one wants the channel anymore */
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NV_DEBUG(dev, "freeing channel %d\n", chan->id);
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nouveau_debugfs_channel_fini(chan);
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@ -216,7 +216,7 @@ struct nouveau_channel {
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/* mapping of the fifo itself */
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struct drm_local_map *map;
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/* mapping of the regs controling the fifo */
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/* mapping of the regs controlling the fifo */
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void __iomem *user;
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uint32_t user_get;
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uint32_t user_put;
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@ -963,7 +963,7 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
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if (ret)
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goto err_mmio;
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/* Map PRAMIN BAR, or on older cards, the aperture withing BAR0 */
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/* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
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if (dev_priv->card_type >= NV_40) {
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int ramin_bar = 2;
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if (pci_resource_len(dev->pdev, ramin_bar) == 0)
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@ -164,7 +164,7 @@ nv_crtc_dpms(struct drm_crtc *crtc, int mode)
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NV_DEBUG_KMS(dev, "Setting dpms mode %d on CRTC %d\n", mode,
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nv_crtc->index);
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if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
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if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */
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return;
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nv_crtc->last_dpms = mode;
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@ -677,7 +677,7 @@ static void nv_crtc_prepare(struct drm_crtc *crtc)
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NVBlankScreen(dev, nv_crtc->index, true);
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/* Some more preperation. */
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/* Some more preparation. */
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NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
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if (dev_priv->card_type == NV_40) {
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uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900);
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@ -181,7 +181,7 @@ nv40_graph_load_context(struct nouveau_channel *chan)
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NV40_PGRAPH_CTXCTL_CUR_LOADED);
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/* 0x32E0 records the instance address of the active FIFO's PGRAPH
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* context. If at any time this doesn't match 0x40032C, you will
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* recieve PGRAPH_INTR_CONTEXT_SWITCH
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* receive PGRAPH_INTR_CONTEXT_SWITCH
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*/
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nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, inst);
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return 0;
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@ -738,13 +738,13 @@ typedef struct _ATOM_DIG_ENCODER_CONFIG_V3
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{
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#if ATOM_BIG_ENDIAN
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UCHAR ucReserved1:1;
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UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also refered as DIGA/B/C/D/E/F)
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UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
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UCHAR ucReserved:3;
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UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
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#else
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UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
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UCHAR ucReserved:3;
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UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also refered as DIGA/B/C/D/E/F)
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UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
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UCHAR ucReserved1:1;
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#endif
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}ATOM_DIG_ENCODER_CONFIG_V3;
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@ -785,13 +785,13 @@ typedef struct _ATOM_DIG_ENCODER_CONFIG_V4
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{
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#if ATOM_BIG_ENDIAN
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UCHAR ucReserved1:1;
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UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also refered as DIGA/B/C/D/E/F)
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UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
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UCHAR ucReserved:2;
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UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
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#else
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UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
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UCHAR ucReserved:2;
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UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also refered as DIGA/B/C/D/E/F)
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UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
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UCHAR ucReserved1:1;
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#endif
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}ATOM_DIG_ENCODER_CONFIG_V4;
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@ -2126,7 +2126,7 @@ typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
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// Structures used in FirmwareInfoTable
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/****************************************************************************/
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// usBIOSCapability Defintion:
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// usBIOSCapability Definition:
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// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
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// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
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// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
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@ -3341,7 +3341,7 @@ typedef struct _ATOM_SPREAD_SPECTRUM_INFO
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/****************************************************************************/
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// Structure used in AnalogTV_InfoTable (Top level)
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/****************************************************************************/
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//ucTVBootUpDefaultStd definiton:
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//ucTVBootUpDefaultStd definition:
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//ATOM_TV_NTSC 1
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//ATOM_TV_NTSCJ 2
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@ -3816,7 +3816,7 @@ typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO
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UCHAR Reserved [6]; // for potential expansion
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}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO;
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//Related definitions, all records are differnt but they have a commond header
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//Related definitions, all records are different but they have a commond header
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typedef struct _ATOM_COMMON_RECORD_HEADER
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{
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UCHAR ucRecordType; //An emun to indicate the record type
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@ -4365,14 +4365,14 @@ ucUMAChannelNumber: System memory channel numbers.
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ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default
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ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback.
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ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
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sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
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sAvail_SCLK[5]: Arrays to provide available list of SLCK and corresponding voltage, order from low to high
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ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
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ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
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ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
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ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.
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ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.
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usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%.
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usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread.
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usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
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usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.
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usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
|
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usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
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usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
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@ -4555,7 +4555,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
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#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3
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#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4
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//Byte aligned defintion for BIOS usage
|
||||
//Byte aligned definition for BIOS usage
|
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#define ATOM_S0_CRT1_MONOb0 0x01
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#define ATOM_S0_CRT1_COLORb0 0x02
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#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)
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|
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@ -4621,7 +4621,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
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#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L
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|
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|
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//Byte aligned defintion for BIOS usage
|
||||
//Byte aligned definition for BIOS usage
|
||||
#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F
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#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF
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#define ATOM_S2_DEVICE_DPMS_STATEb2 0x01
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|
|
@ -4671,7 +4671,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
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#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L
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#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L
|
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|
||||
//Byte aligned defintion for BIOS usage
|
||||
//Byte aligned definition for BIOS usage
|
||||
#define ATOM_S3_CRT1_ACTIVEb0 0x01
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#define ATOM_S3_LCD1_ACTIVEb0 0x02
|
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#define ATOM_S3_TV1_ACTIVEb0 0x04
|
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|
|
@ -4707,7 +4707,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
|
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#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L
|
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#define ATOM_S4_LCD1_REFRESH_SHIFT 8
|
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|
||||
//Byte aligned defintion for BIOS usage
|
||||
//Byte aligned definition for BIOS usage
|
||||
#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF
|
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#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0
|
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#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0
|
||||
|
|
@ -4786,7 +4786,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
|
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#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L
|
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#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L
|
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|
||||
//Byte aligned defintion for BIOS usage
|
||||
//Byte aligned definition for BIOS usage
|
||||
#define ATOM_S6_DEVICE_CHANGEb0 0x01
|
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#define ATOM_S6_SCALER_CHANGEb0 0x02
|
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#define ATOM_S6_LID_CHANGEb0 0x04
|
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|
|
@ -5027,7 +5027,7 @@ typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION
|
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|
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typedef struct _MEMORY_CLEAN_UP_PARAMETERS
|
||||
{
|
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USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address
|
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USHORT usMemoryStart; //in 8Kb boundary, offset from memory base address
|
||||
USHORT usMemorySize; //8Kb blocks aligned
|
||||
}MEMORY_CLEAN_UP_PARAMETERS;
|
||||
#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS
|
||||
|
|
@ -6855,7 +6855,7 @@ typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table
|
|||
/**************************************************************************/
|
||||
|
||||
|
||||
// Following definitions are for compatiblity issue in different SW components.
|
||||
// Following definitions are for compatibility issue in different SW components.
|
||||
#define ATOM_MASTER_DATA_TABLE_REVISION 0x01
|
||||
#define Object_Info Object_Header
|
||||
#define AdjustARB_SEQ MC_InitParameter
|
||||
|
|
|
|||
|
|
@ -442,7 +442,7 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3
|
|||
}
|
||||
ib = p->ib->ptr;
|
||||
switch (reg) {
|
||||
/* force following reg to 0 in an attemp to disable out buffer
|
||||
/* force following reg to 0 in an attempt to disable out buffer
|
||||
* which will need us to better understand how it works to perform
|
||||
* security check on it (Jerome)
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -437,7 +437,7 @@ int r300_asic_reset(struct radeon_device *rdev)
|
|||
status = RREG32(R_000E40_RBBM_STATUS);
|
||||
dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
|
||||
/* resetting the CP seems to be problematic sometimes it end up
|
||||
* hard locking the computer, but it's necessary for successfull
|
||||
* hard locking the computer, but it's necessary for successful
|
||||
* reset more test & playing is needed on R3XX/R4XX to find a
|
||||
* reliable (if any solution)
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -608,7 +608,7 @@
|
|||
* My guess is that there are two bits for each zbias primitive
|
||||
* (FILL, LINE, POINT).
|
||||
* One to enable depth test and one for depth write.
|
||||
* Yet this doesnt explain why depth writes work ...
|
||||
* Yet this doesn't explain why depth writes work ...
|
||||
*/
|
||||
#define R300_RE_OCCLUSION_CNTL 0x42B4
|
||||
# define R300_OCCLUSION_ON (1<<1)
|
||||
|
|
@ -817,7 +817,7 @@
|
|||
# define R300_TX_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 11)
|
||||
# define R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR (10 << 11)
|
||||
|
||||
/* NOTE: NEAREST doesnt seem to exist.
|
||||
/* NOTE: NEAREST doesn't seem to exist.
|
||||
* Im not seting MAG_FILTER_MASK and (3 << 11) on for all
|
||||
* anisotropy modes because that would void selected mag filter
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -921,7 +921,7 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
|
|||
return 0;
|
||||
ib = p->ib->ptr;
|
||||
switch (reg) {
|
||||
/* force following reg to 0 in an attemp to disable out buffer
|
||||
/* force following reg to 0 in an attempt to disable out buffer
|
||||
* which will need us to better understand how it works to perform
|
||||
* security check on it (Jerome)
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -334,7 +334,7 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
|
|||
r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
|
||||
/* it's unknown what these bits do excatly, but it's indeed quite usefull for debugging */
|
||||
/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
|
||||
WREG32(offset+R600_HDMI_AUDIO_DEBUG_0, 0x00FFFFFF);
|
||||
WREG32(offset+R600_HDMI_AUDIO_DEBUG_1, 0x007FFFFF);
|
||||
WREG32(offset+R600_HDMI_AUDIO_DEBUG_2, 0x00000001);
|
||||
|
|
|
|||
|
|
@ -679,11 +679,11 @@ struct radeon_wb {
|
|||
* @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
|
||||
* @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
|
||||
* @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
|
||||
* @sclk: GPU clock Mhz (core bandwith depends of this clock)
|
||||
* @sclk: GPU clock Mhz (core bandwidth depends of this clock)
|
||||
* @needed_bandwidth: current bandwidth needs
|
||||
*
|
||||
* It keeps track of various data needed to take powermanagement decision.
|
||||
* Bandwith need is used to determine minimun clock of the GPU and memory.
|
||||
* Bandwidth need is used to determine minimun clock of the GPU and memory.
|
||||
* Equation between gpu/memory clock and available bandwidth is hw dependent
|
||||
* (type of memory, bus size, efficiency, ...)
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -244,7 +244,7 @@ void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
|
|||
u32 agp_base_lo = agp_base & 0xffffffff;
|
||||
u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
|
||||
|
||||
/* R6xx/R7xx must be aligned to a 4MB boundry */
|
||||
/* R6xx/R7xx must be aligned to a 4MB boundary */
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
|
||||
RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
|
||||
else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
|
||||
|
|
|
|||
|
|
@ -226,7 +226,7 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
|
|||
y += crtc->y;
|
||||
DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
|
||||
|
||||
/* avivo cursor image can't end on 128 pixel boundry or
|
||||
/* avivo cursor image can't end on 128 pixel boundary or
|
||||
* go past the end of the frame if both crtcs are enabled
|
||||
*/
|
||||
list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {
|
||||
|
|
|
|||
|
|
@ -262,7 +262,7 @@ int radeon_wb_init(struct radeon_device *rdev)
|
|||
* Note: GTT start, end, size should be initialized before calling this
|
||||
* function on AGP platform.
|
||||
*
|
||||
* Note: We don't explictly enforce VRAM start to be aligned on VRAM size,
|
||||
* Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
|
||||
* this shouldn't be a problem as we are using the PCI aperture as a reference.
|
||||
* Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
|
||||
* not IGP.
|
||||
|
|
|
|||
|
|
@ -1492,7 +1492,7 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
|
|||
*
|
||||
* \return Flags, or'ed together as follows:
|
||||
*
|
||||
* DRM_SCANOUTPOS_VALID = Query successfull.
|
||||
* DRM_SCANOUTPOS_VALID = Query successful.
|
||||
* DRM_SCANOUTPOS_INVBL = Inside vblank.
|
||||
* DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
|
||||
* this flag means that returned position may be offset by a constant but
|
||||
|
|
|
|||
|
|
@ -271,7 +271,7 @@ typedef struct drm_radeon_private {
|
|||
|
||||
int have_z_offset;
|
||||
|
||||
/* starting from here on, data is preserved accross an open */
|
||||
/* starting from here on, data is preserved across an open */
|
||||
uint32_t flags; /* see radeon_chip_flags */
|
||||
resource_size_t fb_aper_offset;
|
||||
|
||||
|
|
|
|||
|
|
@ -87,7 +87,7 @@ static inline void radeon_bo_unreserve(struct radeon_bo *bo)
|
|||
* Returns current GPU offset of the object.
|
||||
*
|
||||
* Note: object should either be pinned or reserved when calling this
|
||||
* function, it might be usefull to add check for this for debugging.
|
||||
* function, it might be useful to add check for this for debugging.
|
||||
*/
|
||||
static inline u64 radeon_bo_gpu_offset(struct radeon_bo *bo)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -980,7 +980,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
|
|||
}
|
||||
|
||||
/* hyper z clear */
|
||||
/* no docs available, based on reverse engeneering by Stephane Marchesin */
|
||||
/* no docs available, based on reverse engineering by Stephane Marchesin */
|
||||
if ((flags & (RADEON_DEPTH | RADEON_STENCIL))
|
||||
&& (flags & RADEON_CLEAR_FASTZ)) {
|
||||
|
||||
|
|
|
|||
|
|
@ -245,7 +245,7 @@ void vmw_kms_cursor_snoop(struct vmw_surface *srf,
|
|||
/* TODO handle none page aligned offsets */
|
||||
/* TODO handle partial uploads and pitch != 256 */
|
||||
/* TODO handle more then one copy (size != 64) */
|
||||
DRM_ERROR("lazy programer, cant handle wierd stuff\n");
|
||||
DRM_ERROR("lazy programmer, can't handle weird stuff\n");
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -151,7 +151,7 @@ static inline void vga_irq_set_state(struct vga_device *vgadev, bool state)
|
|||
static void vga_check_first_use(void)
|
||||
{
|
||||
/* we should inform all GPUs in the system that
|
||||
* VGA arb has occured and to try and disable resources
|
||||
* VGA arb has occurred and to try and disable resources
|
||||
* if they can */
|
||||
if (!vga_arbiter_used) {
|
||||
vga_arbiter_used = true;
|
||||
|
|
@ -774,7 +774,7 @@ static ssize_t vga_arb_read(struct file *file, char __user * buf,
|
|||
*/
|
||||
spin_lock_irqsave(&vga_lock, flags);
|
||||
|
||||
/* If we are targetting the default, use it */
|
||||
/* If we are targeting the default, use it */
|
||||
pdev = priv->target;
|
||||
if (pdev == NULL || pdev == PCI_INVALID_CARD) {
|
||||
spin_unlock_irqrestore(&vga_lock, flags);
|
||||
|
|
|
|||
Loading…
Reference in a new issue