From 42e2132dba4637346f23922c46758b4aaa7e3c40 Mon Sep 17 00:00:00 2001 From: Vivek Kumar Date: Wed, 14 Oct 2020 10:53:12 +0530 Subject: [PATCH] ARM: dts: msm: Add pinctrl node for TLMM on Direwolf SoC Add pinctrl node with compatiability of qcom,direwolf-pinctrl, to enable Top Level Mode Multiplexer block(TLMM) on Direwolf SoC. Change-Id: I5cf4c487a59d5d38958a15f0c9f1ef8877e254c1 --- bindings/pinctrl/qcom,direwolf-pinctrl.yaml | 148 ++++++++++++++++++++ qcom/direwolf-pinctrl.dtsi | 1 + qcom/direwolf.dtsi | 13 ++ 3 files changed, 162 insertions(+) create mode 100644 bindings/pinctrl/qcom,direwolf-pinctrl.yaml create mode 100644 qcom/direwolf-pinctrl.dtsi diff --git a/bindings/pinctrl/qcom,direwolf-pinctrl.yaml b/bindings/pinctrl/qcom,direwolf-pinctrl.yaml new file mode 100644 index 000000000000..33cc8e59e26f --- /dev/null +++ b/bindings/pinctrl/qcom,direwolf-pinctrl.yaml @@ -0,0 +1,148 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,direwolf-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. DIREWOLF TLMM block + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + Direwolf platform. + +properties: + compatible: + Usage: required + Value type: + Definition: must be "qcom,direwolf-pinctrl" + + reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + + interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + + interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + + #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + + gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + + #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + + wakeup-parent: + Usage: optional + Value type: + Definition: A phandle to the wakeup interrupt controller for the SoC. + + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for + a general description of GPIO and interrupt bindings. + + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + The pin configuration nodes act as a container for an arbitrary number of + subnodes. Each of these subnodes represents some desired configuration for a + pin, a group, or a list of pins or groups. This configuration can include the + mux function to select on those pin(s)/group(s), and various pin configuration + parameters, such as pull-up, drive strength, etc. + + + PIN CONFIGURATION NODES: + + The name of each subnode is not important; all subnodes should be enumerated + and processed purely based on their content. + + Each subnode only affects those parameters that are explicitly listed. In + other words, a subnode that lists a mux function but no pin configuration + parameters implies no information about any pin configuration parameters. + Similarly, a pin subnode that describes a pullup parameter implies no + information about e.g. the mux function. + + + The following generic properties as defined in pinctrl-bindings.txt are valid + to specify in a pin configuration subnode: + + pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins: + gpio0-gpio227 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + + function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + + bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configured as no pull. + + bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull down. + + bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull up. + + output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven high. + Not valid for sdc pins. + + output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven low. + Not valid for sdc pins. + + drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + Valid values: 2, 4, 6, 8, 10, 12, 14 and 16 + +examples: + - | + tlmm: pinctrl@03000000 { + compatible = "qcom,direwolf-pinctrl"; + reg = <0x03000000 0xdc2000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + }; diff --git a/qcom/direwolf-pinctrl.dtsi b/qcom/direwolf-pinctrl.dtsi new file mode 100644 index 000000000000..8b7b9bd9baa8 --- /dev/null +++ b/qcom/direwolf-pinctrl.dtsi @@ -0,0 +1 @@ +&tlmm { }; diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 1f9eb37a4afa..a75072d5dcde 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -413,4 +413,17 @@ status = "disabled"; }; }; + + tlmm: pinctrl@f000000 { + compatible = "qcom,direwolf-pinctrl"; + reg = <0x0F000000 0x1000000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + +#include "direwolf-pinctrl.dtsi"