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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-09 05:39:54 -04:00
Merge "scsi: ufs: remove voting for hw ice clk"
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commit
42fa1dcf73
2 changed files with 35 additions and 3 deletions
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@ -1995,6 +1995,8 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
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{
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struct ufs_qcom_host *host = ufshcd_get_variant(hba);
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int err = 0;
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struct list_head *head = &hba->clk_list_head;
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struct ufs_clk_info *clki;
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/*
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* In case ufs_qcom_init() is not yet done, simply ignore.
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@ -2021,6 +2023,33 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
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return err;
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}
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}
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if (list_empty(head)) {
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dev_err(hba->dev, "%s: clk list is empty\n", __func__);
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return err;
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}
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/*
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* As per the latest hardware programming guide,
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* during Hibern8 enter with power collapse :
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* SW should disable HW clock control for UFS ICE
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* clock (GCC_UFS_ICE_CORE_CBCR.HW_CTL=0)
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* before ufs_ice_core_clk is turned off.
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* In device tree, we need to add UFS ICE clocks
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* in below fixed order:
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* clock-names =
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* "core_clk_ice";
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* "core_clk_ice_hw_ctl";
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* This way no extra check is required in UFS
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* clock enable path as clk enable order will be
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* already taken care in ufshcd_setup_clocks().
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*/
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list_for_each_entry(clki, head, list) {
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if (!IS_ERR_OR_NULL(clki->clk) &&
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!strcmp(clki->name, "core_clk_ice_hw_ctl")) {
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clk_disable_unprepare(clki->clk);
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clki->enabled = on;
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}
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}
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}
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break;
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case POST_CHANGE:
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@ -1014,7 +1014,8 @@ static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
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list_for_each_entry(clki, head, list) {
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if (!IS_ERR_OR_NULL(clki->clk)) {
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if (scale_up && clki->max_freq) {
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if (clki->curr_freq == clki->max_freq)
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if ((clki->curr_freq == clki->max_freq) ||
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(!strcmp(clki->name, "core_clk_ice_hw_ctl")))
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continue;
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ret = clk_set_rate(clki->clk, clki->max_freq);
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@ -1032,7 +1033,8 @@ static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
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clki->curr_freq = clki->max_freq;
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} else if (!scale_up && clki->min_freq) {
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if (clki->curr_freq == clki->min_freq)
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if ((clki->curr_freq == clki->min_freq) ||
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(!strcmp(clki->name, "core_clk_ice_hw_ctl")))
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continue;
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ret = clk_set_rate(clki->clk, clki->min_freq);
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@ -8316,7 +8318,8 @@ static int ufshcd_init_clocks(struct ufs_hba *hba)
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goto out;
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list_for_each_entry(clki, head, list) {
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if (!clki->name)
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if ((!clki->name) ||
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(!strcmp(clki->name, "core_clk_ice_hw_ctl")))
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continue;
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clki->clk = devm_clk_get(dev, clki->name);
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