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dt-bindings: Add snapshot for 5.3-rc4

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Add the device-tree bindings' snapshot from tmp-9855ec2fd422 for
5.3-rc4.

Change-Id: I25b0ac9b29c0347f557b87094ede86370a89a0f2
This commit is contained in:
Raghavendra Rao Ananta 2019-08-13 17:42:40 -07:00
commit 430b7fac16
288 changed files with 4680 additions and 3996 deletions
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2
bindings/.gitignore vendored
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@ -1,2 +0,0 @@
*.example.dts
processed-schema.yaml

16
bindings/arm/al,alpine.txt
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@ -1,16 +0,0 @@
Annapurna Labs Alpine Platform Device Tree Bindings
---------------------------------------------------------------
Boards in the Alpine family shall have the following properties:
* Required root node properties:
compatible: must contain "al,alpine"
* Example:
/ {
model = "Annapurna Labs Alpine Dev Board";
compatible = "al,alpine";
...
}

142
bindings/arm/amlogic.txt
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@ -1,142 +0,0 @@
Amlogic MesonX device tree bindings
-------------------------------------------
Work in progress statement:
Device tree files and bindings applying to Amlogic SoCs and boards are
considered "unstable". Any Amlogic device tree binding may change at
any time. Be sure to use a device tree binary and a kernel image
generated from the same source tree.
Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a
stable binding/ABI.
---------------------------------------------------------------
Boards with the Amlogic Meson6 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,meson6"
Boards with the Amlogic Meson8 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,meson8";
Boards with the Amlogic Meson8b SoC shall have the following properties:
Required root node property:
compatible: "amlogic,meson8b";
Boards with the Amlogic Meson8m2 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,meson8m2";
Boards with the Amlogic Meson GXBaby SoC shall have the following properties:
Required root node property:
compatible: "amlogic,meson-gxbb";
Boards with the Amlogic Meson GXL S905X SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s905x", "amlogic,meson-gxl";
Boards with the Amlogic Meson GXL S905D SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s905d", "amlogic,meson-gxl";
Boards with the Amlogic Meson GXL S805X SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s805x", "amlogic,meson-gxl";
Boards with the Amlogic Meson GXL S905W SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s905w", "amlogic,meson-gxl";
Boards with the Amlogic Meson GXM S912 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s912", "amlogic,meson-gxm";
Boards with the Amlogic Meson AXG A113D SoC shall have the following properties:
Required root node property:
compatible: "amlogic,a113d", "amlogic,meson-axg";
Boards with the Amlogic Meson G12A S905D2 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,g12a";
Board compatible values (alphabetically, grouped by SoC):
- "geniatech,atv1200" (Meson6)
- "minix,neo-x8" (Meson8)
- "endless,ec100" (Meson8b)
- "hardkernel,odroid-c1" (Meson8b)
- "tronfy,mxq" (Meson8b)
- "tronsmart,mxiii-plus" (Meson8m2)
- "amlogic,p200" (Meson gxbb)
- "amlogic,p201" (Meson gxbb)
- "friendlyarm,nanopi-k2" (Meson gxbb)
- "hardkernel,odroid-c2" (Meson gxbb)
- "nexbox,a95x" (Meson gxbb or Meson gxl s905x)
- "tronsmart,vega-s95-pro", "tronsmart,vega-s95" (Meson gxbb)
- "tronsmart,vega-s95-meta", "tronsmart,vega-s95" (Meson gxbb)
- "tronsmart,vega-s95-telos", "tronsmart,vega-s95" (Meson gxbb)
- "wetek,hub" (Meson gxbb)
- "wetek,play2" (Meson gxbb)
- "amlogic,p212" (Meson gxl s905x)
- "hwacom,amazetv" (Meson gxl s905x)
- "khadas,vim" (Meson gxl s905x)
- "libretech,cc" (Meson gxl s905x)
- "amlogic,p230" (Meson gxl s905d)
- "amlogic,p231" (Meson gxl s905d)
- "phicomm,n1" (Meson gxl s905d)
- "amlogic,p241" (Meson gxl s805x)
- "libretech,aml-s805x-ac" (Meson gxl s805x)
- "amlogic,p281" (Meson gxl s905w)
- "oranth,tx3-mini" (Meson gxl s905w)
- "amlogic,q200" (Meson gxm s912)
- "amlogic,q201" (Meson gxm s912)
- "khadas,vim2" (Meson gxm s912)
- "kingnovel,r-box-pro" (Meson gxm S912)
- "nexbox,a1" (Meson gxm s912)
- "tronsmart,vega-s96" (Meson gxm s912)
- "amlogic,s400" (Meson axg a113d)
- "amlogic,u200" (Meson g12a s905d2)
- "amediatech,x96-max" (Meson g12a s905x2)
- "seirobotics,sei510" (Meson g12a s905x2)
Amlogic Meson Firmware registers Interface
------------------------------------------
The Meson SoCs have a register bank with status and data shared with the
secure firmware.
Required properties:
- compatible: For Meson GX SoCs, must be "amlogic,meson-gx-ao-secure", "syscon"
Properties should indentify components of this register interface :
Meson GX SoC Information
------------------------
A firmware register encodes the SoC type, package and revision information on
the Meson GX SoCs.
If present, the following property should be added :
Optional properties:
- amlogic,has-chip-id: If present, the interface gives the current SoC version.
Example
-------
ao-secure@140 {
compatible = "amlogic,meson-gx-ao-secure", "syscon";
reg = <0x0 0x140 0x0 0x140>;
amlogic,has-chip-id;
};

28
bindings/arm/amlogic/amlogic,meson-gx-ao-secure.txt Normal file
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@ -0,0 +1,28 @@
Amlogic Meson Firmware registers Interface
------------------------------------------
The Meson SoCs have a register bank with status and data shared with the
secure firmware.
Required properties:
- compatible: For Meson GX SoCs, must be "amlogic,meson-gx-ao-secure", "syscon"
Properties should indentify components of this register interface :
Meson GX SoC Information
------------------------
A firmware register encodes the SoC type, package and revision information on
the Meson GX SoCs.
If present, the following property should be added :
Optional properties:
- amlogic,has-chip-id: If present, the interface gives the current SoC version.
Example
-------
ao-secure@140 {
compatible = "amlogic,meson-gx-ao-secure", "syscon";
reg = <0x0 0x140 0x0 0x140>;
amlogic,has-chip-id;
};

2
bindings/arm/arm,scmi.txt
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@ -6,7 +6,7 @@ that are provided by the hardware platform it is running on, including power
and performance functions.
This binding is intended to define the interface the firmware implementing
the SCMI as described in ARM document number ARM DUI 0922B ("ARM System Control
the SCMI as described in ARM document number ARM DEN 0056A ("ARM System Control
and Management Interface Platform Design Document")[0] provide for OSPM in
the device tree.

2
bindings/arm/arm-boards
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@ -197,7 +197,7 @@ Required nodes:
The description for the board must include:
- a "psci" node describing the boot method used for the secondary CPUs.
A detailed description of the bindings used for "psci" nodes is present
in the psci.txt file.
in the psci.yaml file.
- a "cpus" node describing the available cores and their associated
"enable-method"s. For more details see cpus.txt file.

73
bindings/arm/atmel-at91.txt
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@ -1,73 +0,0 @@
Atmel AT91 device tree bindings.
================================
Boards with a SoC of the Atmel AT91 or SMART family shall have the following
properties:
Required root node properties:
compatible: must be one of:
* "atmel,at91rm9200"
* "atmel,at91sam9" for SoCs using an ARM926EJ-S core, shall be extended with
the specific SoC family or compatible:
o "atmel,at91sam9260"
o "atmel,at91sam9261"
o "atmel,at91sam9263"
o "atmel,at91sam9x5" for the 5 series, shall be extended with the specific
SoC compatible:
- "atmel,at91sam9g15"
- "atmel,at91sam9g25"
- "atmel,at91sam9g35"
- "atmel,at91sam9x25"
- "atmel,at91sam9x35"
o "atmel,at91sam9g20"
o "atmel,at91sam9g45"
o "atmel,at91sam9n12"
o "atmel,at91sam9rl"
o "atmel,at91sam9xe"
o "microchip,sam9x60"
* "atmel,sama5" for SoCs using a Cortex-A5, shall be extended with the specific
SoC family:
o "atmel,sama5d2" shall be extended with the specific SoC compatible:
- "atmel,sama5d27"
o "atmel,sama5d3" shall be extended with the specific SoC compatible:
- "atmel,sama5d31"
- "atmel,sama5d33"
- "atmel,sama5d34"
- "atmel,sama5d35"
- "atmel,sama5d36"
o "atmel,sama5d4" shall be extended with the specific SoC compatible:
- "atmel,sama5d41"
- "atmel,sama5d42"
- "atmel,sama5d43"
- "atmel,sama5d44"
* "atmel,samv7" for MCUs using a Cortex-M7, shall be extended with the specific
SoC family:
o "atmel,sams70" shall be extended with the specific MCU compatible:
- "atmel,sams70j19"
- "atmel,sams70j20"
- "atmel,sams70j21"
- "atmel,sams70n19"
- "atmel,sams70n20"
- "atmel,sams70n21"
- "atmel,sams70q19"
- "atmel,sams70q20"
- "atmel,sams70q21"
o "atmel,samv70" shall be extended with the specific MCU compatible:
- "atmel,samv70j19"
- "atmel,samv70j20"
- "atmel,samv70n19"
- "atmel,samv70n20"
- "atmel,samv70q19"
- "atmel,samv70q20"
o "atmel,samv71" shall be extended with the specific MCU compatible:
- "atmel,samv71j19"
- "atmel,samv71j20"
- "atmel,samv71j21"
- "atmel,samv71n19"
- "atmel,samv71n20"
- "atmel,samv71n21"
- "atmel,samv71q19"
- "atmel,samv71q20"
- "atmel,samv71q21"

12
bindings/arm/axxia.txt
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@ -1,12 +0,0 @@
Axxia AXM55xx device tree bindings
Boards using the AXM55xx SoC need to have the following properties:
Required root node property:
- compatible = "lsi,axm5516"
Boards:
LSI AXM5516 Validation board (Amarillo)
compatible = "lsi,axm5516-amarillo", "lsi,axm5516"

4
bindings/arm/coresight-cpu-debug.txt
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@ -26,8 +26,8 @@ Required properties:
processor core is clocked by the internal CPU clock, so it
is enabled with CPU clock by default.
- cpu : the CPU phandle the debug module is affined to. When omitted
the module is considered to belong to CPU0.
- cpu : the CPU phandle the debug module is affined to. Do not assume it
to default to CPU0 if omitted.
Optional properties:

8
bindings/arm/coresight.txt
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@ -59,6 +59,11 @@ its hardware characteristcs.
* port or ports: see "Graph bindings for Coresight" below.
* Additional required property for Embedded Trace Macrocell (version 3.x and
version 4.x):
* cpu: the cpu phandle this ETM/PTM is affined to. Do not
assume it to default to CPU0 if omitted.
* Additional required properties for System Trace Macrocells (STM):
* reg: along with the physical base address and length of the register
set as described above, another entry is required to describe the
@ -87,9 +92,6 @@ its hardware characteristcs.
* arm,cp14: must be present if the system accesses ETM/PTM management
registers via co-processor 14.
* cpu: the cpu phandle this ETM/PTM is affined to. When omitted the
source is considered to belong to CPU0.
* Optional property for TMC:
* arm,buffer-size: size of contiguous buffer space for TMC ETR

6
bindings/arm/digicolor.txt
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@ -1,6 +0,0 @@
Conexant Digicolor Platforms Device Tree Bindings
Each device tree must specify which Conexant Digicolor SoC it uses.
Must be the following compatible string:
cnxt,cx92755

12
bindings/arm/emtrion.txt
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@ -1,12 +0,0 @@
Emtrion Devicetree Bindings
===========================
emCON Series:
-------------
Required root node properties
- compatible:
- "emtrion,emcon-mx6", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM
- "emtrion,emcon-mx6-avari", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM on Avari Base
- "emtrion,emcon-mx6", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM
- "emtrion,emcon-mx6-avari", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM on Avari Base

37
bindings/arm/freescale/fsl,scu.txt
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@ -133,6 +133,28 @@ RTC bindings based on SCU Message Protocol
Required properties:
- compatible: should be "fsl,imx8qxp-sc-rtc";
OCOTP bindings based on SCU Message Protocol
------------------------------------------------------------
Required properties:
- compatible: Should be "fsl,imx8qxp-scu-ocotp"
- #address-cells: Must be 1. Contains byte index
- #size-cells: Must be 1. Contains byte length
Optional Child nodes:
- Data cells of ocotp:
Detailed bindings are described in bindings/nvmem/nvmem.txt
Watchdog bindings based on SCU Message Protocol
------------------------------------------------------------
Required properties:
- compatible: should be:
"fsl,imx8qxp-sc-wdt"
followed by "fsl,imx-sc-wdt";
Optional properties:
- timeout-sec: contains the watchdog timeout in seconds.
Example (imx8qxp):
-------------
aliases {
@ -177,6 +199,16 @@ firmware {
...
};
ocotp: imx8qx-ocotp {
compatible = "fsl,imx8qxp-scu-ocotp";
#address-cells = <1>;
#size-cells = <1>;
fec_mac0: mac@2c4 {
reg = <0x2c4 8>;
};
};
pd: imx8qx-pd {
compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
#power-domain-cells = <1>;
@ -185,6 +217,11 @@ firmware {
rtc: rtc {
compatible = "fsl,imx8qxp-sc-rtc";
};
watchdog {
compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
timeout-sec = <60>;
};
};
};

15
bindings/arm/idle-states.txt
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@ -241,9 +241,13 @@ processor idle states, defined as device tree nodes, are listed.
- "psci"
# On ARM 32-bit systems this property is optional
The nodes describing the idle states (state) can only be defined within the
idle-states node, any other configuration is considered invalid and therefore
must be ignored.
This assumes that the "enable-method" property is set to "psci" in the cpu
node[6] that is responsible for setting up CPU idle management in the OS
implementation.
The nodes describing the idle states (state) can only be defined
within the idle-states node, any other configuration is considered invalid
and therefore must be ignored.
===========================================
4 - state node
@ -687,7 +691,7 @@ cpus {
Documentation/devicetree/bindings/arm/cpus.yaml
[2] ARM Linux Kernel documentation - PSCI bindings
Documentation/devicetree/bindings/arm/psci.txt
Documentation/devicetree/bindings/arm/psci.yaml
[3] ARM Server Base System Architecture (SBSA)
http://infocenter.arm.com/help/index.jsp
@ -697,3 +701,6 @@ cpus {
[5] Devicetree Specification
https://www.devicetree.org/specifications/
[6] ARM Linux Kernel documentation - Booting AArch64 Linux
Documentation/arm64/booting.rst

89
bindings/arm/mediatek.txt
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@ -1,89 +0,0 @@
MediaTek SoC based Platforms Device Tree Bindings
Boards with a MediaTek SoC shall have the following property:
Required root node property:
compatible: Must contain one of
"mediatek,mt2701"
"mediatek,mt2712"
"mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
"mediatek,mt6755"
"mediatek,mt6765"
"mediatek,mt6795"
"mediatek,mt6797"
"mediatek,mt7622"
"mediatek,mt7623"
"mediatek,mt7629"
"mediatek,mt8127"
"mediatek,mt8135"
"mediatek,mt8173"
"mediatek,mt8183"
Supported boards:
- Evaluation board for MT2701:
Required root node properties:
- compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
- Evaluation board for MT2712:
Required root node properties:
- compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
- Evaluation board for MT6580:
Required root node properties:
- compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
- bq Aquaris5 smart phone:
Required root node properties:
- compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589";
- Evaluation board for MT6592:
Required root node properties:
- compatible = "mediatek,mt6592-evb", "mediatek,mt6592";
- Evaluation phone for MT6755(Helio P10):
Required root node properties:
- compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
- Evaluation board for MT6765(Helio P22):
Required root node properties:
- compatible = "mediatek,mt6765-evb", "mediatek,mt6765";
- Evaluation board for MT6795(Helio X10):
Required root node properties:
- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
- Evaluation board for MT6797(Helio X20):
Required root node properties:
- compatible = "mediatek,mt6797-evb", "mediatek,mt6797";
- Mediatek X20 Development Board:
Required root node properties:
- compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797";
- Reference board variant 1 for MT7622:
Required root node properties:
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
- Bananapi BPI-R64 for MT7622:
Required root node properties:
- compatible = "bananapi,bpi-r64", "mediatek,mt7622";
- Reference board for MT7623a with eMMC:
Required root node properties:
- compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623";
- Reference board for MT7623a with NAND:
Required root node properties:
- compatible = "mediatek,mt7623a-rfb-nand", "mediatek,mt7623";
- Reference board for MT7623n with eMMC:
Required root node properties:
- compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623";
- Bananapi BPI-R2 board:
- compatible = "bananapi,bpi-r2", "mediatek,mt7623";
- Reference board for MT7629:
Required root node properties:
- compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
- MTK mt8127 tablet moose EVB:
Required root node properties:
- compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
- MTK mt8135 tablet EVB:
Required root node properties:
- compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135";
- MTK mt8173 tablet EVB:
Required root node properties:
- compatible = "mediatek,mt8173-evb", "mediatek,mt8173";
- Evaluation board for MT8183:
Required root node properties:
- compatible = "mediatek,mt8183-evb", "mediatek,mt8183";

1
bindings/arm/mediatek/mediatek,audsys.txt
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@ -10,6 +10,7 @@ Required Properties:
- "mediatek,mt7622-audsys", "syscon"
- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
- "mediatek,mt8183-audiosys", "syscon"
- "mediatek,mt8516-audsys", "syscon"
- #clock-cells: Must be 1
The AUDSYS controller uses the common clk binding from

2
bindings/arm/mediatek/mediatek,sgmiisys.txt
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@ -9,6 +9,8 @@ Required Properties:
- "mediatek,mt7622-sgmiisys", "syscon"
- "mediatek,mt7629-sgmiisys", "syscon"
- #clock-cells: Must be 1
- mediatek,physpeed: Should be one of "auto", "1000" or "2500" to match up
the capability of the target PHY.
The SGMIISYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt

12
bindings/arm/moxart.txt
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@ -1,12 +0,0 @@
MOXA ART device tree bindings
Boards with the MOXA ART SoC shall have the following properties:
Required root node property:
compatible = "moxa,moxart";
Boards:
- UC-7112-LX: embedded computer
compatible = "moxa,moxart-uc-7112-lx", "moxa,moxart"

8
bindings/arm/nxp/lpc32xx.txt
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@ -1,8 +0,0 @@
NXP LPC32xx Platforms Device Tree Bindings
------------------------------------------
Boards with the NXP LPC32xx SoC shall have the following properties:
Required root node property:
compatible: must be "nxp,lpc3220", "nxp,lpc3230", "nxp,lpc3240" or "nxp,lpc3250"

3
bindings/arm/omap/omap.txt
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@ -160,6 +160,9 @@ Boards:
- AM335X phyCORE-AM335x: Development kit
compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx"
- AM335x phyBOARD-REGOR: Single Board Computer
compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx"
- AM335X UC-8100-ME-T: Communication-centric industrial computing platform
compatible = "moxa,uc-8100-me-t", "ti,am33xx";

111
bindings/arm/psci.txt
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@ -1,111 +0,0 @@
* Power State Coordination Interface (PSCI)
Firmware implementing the PSCI functions described in ARM document number
ARM DEN 0022A ("Power State Coordination Interface System Software on ARM
processors") can be used by Linux to initiate various CPU-centric power
operations.
Issue A of the specification describes functions for CPU suspend, hotplug
and migration of secure software.
Functions are invoked by trapping to the privilege level of the PSCI
firmware (specified as part of the binding below) and passing arguments
in a manner similar to that specified by AAPCS:
r0 => 32-bit Function ID / return value
{r1 - r3} => Parameters
Note that the immediate field of the trapping instruction must be set
to #0.
Main node required properties:
- compatible : should contain at least one of:
* "arm,psci" : For implementations complying to PSCI versions prior
to 0.2.
For these cases function IDs must be provided.
* "arm,psci-0.2" : For implementations complying to PSCI 0.2.
Function IDs are not required and should be ignored by
an OS with PSCI 0.2 support, but are permitted to be
present for compatibility with existing software when
"arm,psci" is later in the compatible list.
* "arm,psci-1.0" : For implementations complying to PSCI 1.0.
PSCI 1.0 is backward compatible with PSCI 0.2 with
minor specification updates, as defined in the PSCI
specification[2].
- method : The method of calling the PSCI firmware. Permitted
values are:
"smc" : SMC #0, with the register assignments specified
in this binding.
"hvc" : HVC #0, with the register assignments specified
in this binding.
Main node optional properties:
- cpu_suspend : Function ID for CPU_SUSPEND operation
- cpu_off : Function ID for CPU_OFF operation
- cpu_on : Function ID for CPU_ON operation
- migrate : Function ID for MIGRATE operation
Device tree nodes that require usage of PSCI CPU_SUSPEND function (ie idle
state nodes, as per bindings in [1]) must specify the following properties:
- arm,psci-suspend-param
Usage: Required for state nodes[1] if the corresponding
idle-states node entry-method property is set
to "psci".
Value type: <u32>
Definition: power_state parameter to pass to the PSCI
suspend call.
Example:
Case 1: PSCI v0.1 only.
psci {
compatible = "arm,psci";
method = "smc";
cpu_suspend = <0x95c10000>;
cpu_off = <0x95c10001>;
cpu_on = <0x95c10002>;
migrate = <0x95c10003>;
};
Case 2: PSCI v0.2 only
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
Case 3: PSCI v0.2 and PSCI v0.1.
A DTB may provide IDs for use by kernels without PSCI 0.2 support,
enabling firmware and hypervisors to support existing and new kernels.
These IDs will be ignored by kernels with PSCI 0.2 support, which will
use the standard PSCI 0.2 IDs exclusively.
psci {
compatible = "arm,psci-0.2", "arm,psci";
method = "hvc";
cpu_on = < arbitrary value >;
cpu_off = < arbitrary value >;
...
};
[1] Kernel documentation - ARM idle states bindings
Documentation/devicetree/bindings/arm/idle-states.txt
[2] Power State Coordination Interface (PSCI) specification
http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf

17
bindings/arm/rda.txt
View file

@ -1,17 +0,0 @@
RDA Micro platforms device tree bindings
----------------------------------------
RDA8810PL SoC
=============
Required root node properties:
- compatible : must contain "rda,8810pl"
Boards:
Root node property compatible must contain, depending on board:
- Orange Pi 2G-IoT: "xunlong,orangepi-2g-iot"
- Orange Pi i96: "xunlong,orangepi-i96"

37
bindings/arm/stm32/mlahb.txt Normal file
View file

@ -0,0 +1,37 @@
ML-AHB interconnect bindings
These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
a Cortex-M subsystem with dedicated memories.
The MCU SRAM and RETRAM memory parts can be accessed through different addresses
(see "RAM aliases" in [1]) using different buses (see [2]) : balancing the
Cortex-M firmware accesses among those ports allows to tune the system
performance.
[1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf
[2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping
Required properties:
- compatible: should be "simple-bus"
- dma-ranges: describes memory addresses translation between the local CPU and
the remote Cortex-M processor. Each memory region, is declared with
3 parameters:
- param 1: device base address (Cortex-M processor address)
- param 2: physical base address (local CPU address)
- param 3: size of the memory region.
The Cortex-M remote processor accessed via the mlahb interconnect is described
by a child node.
Example:
mlahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
dma-ranges = <0x00000000 0x38000000 0x10000>,
<0x10000000 0x10000000 0x60000>,
<0x30000000 0x30000000 0x60000>;
m4_rproc: m4@10000000 {
...
};
};

10
bindings/arm/stm32/stm32.txt
View file

@ -1,10 +0,0 @@
STMicroelectronics STM32 Platforms Device Tree Bindings
Each device tree must specify which STM32 SoC it uses,
using one of the following compatible strings:
st,stm32f429
st,stm32f469
st,stm32f746
st,stm32h743
st,stm32mp157

3
bindings/arm/ti/k3.txt
View file

@ -13,6 +13,9 @@ architecture it uses, using one of the following compatible values:
- AM654
compatible = "ti,am654";
- J721E
compatible = "ti,j721e";
Boards
------

2
bindings/arm/xen.txt
View file

@ -54,7 +54,7 @@ hypervisor {
};
The format and meaning of the "xen,uefi-*" parameters are similar to those in
Documentation/arm/uefi.txt, which are provided by the regular UEFI stub. However
Documentation/arm/uefi.rst, which are provided by the regular UEFI stub. However
they differ because they are provided by the Xen hypervisor, together with a set
of UEFI runtime services implemented via hypercalls, see
http://xenbits.xen.org/docs/unstable/hypercall/x86_64/include,public,platform.h.html.

47
bindings/bus/sunxi-rsb.txt
View file

@ -1,47 +0,0 @@
Allwinner Reduced Serial Bus (RSB) controller
The RSB controller found on later Allwinner SoCs is an SMBus like 2 wire
serial bus with 1 master and up to 15 slaves. It is represented by a node
for the controller itself, and child nodes representing the slave devices.
Required properties :
- reg : Offset and length of the register set for the controller.
- compatible : Shall be "allwinner,sun8i-a23-rsb".
- interrupts : The interrupt line associated to the RSB controller.
- clocks : The gate clk associated to the RSB controller.
- resets : The reset line associated to the RSB controller.
- #address-cells : shall be 1
- #size-cells : shall be 0
Optional properties :
- clock-frequency : Desired RSB bus clock frequency in Hz. Maximum is 20MHz.
If not set this defaults to 3MHz.
Child nodes:
An RSB controller node can contain zero or more child nodes representing
slave devices on the bus. Child 'reg' properties should contain the slave
device's hardware address. The hardware address is hardwired in the device,
which can normally be found in the datasheet.
Example:
rsb@1f03400 {
compatible = "allwinner,sun8i-a23-rsb";
reg = <0x01f03400 0x400>;
interrupts = <0 39 4>;
clocks = <&apb0_gates 3>;
clock-frequency = <3000000>;
resets = <&apb0_rst 3>;
#address-cells = <1>;
#size-cells = <0>;
pmic@3e3 {
compatible = "...";
reg = <0x3e3>;
/* ... */
};
};

1
bindings/clock/amlogic,gxbb-clkc.txt
View file

@ -10,6 +10,7 @@ Required Properties:
"amlogic,gxl-clkc" for GXL and GXM SoC,
"amlogic,axg-clkc" for AXG SoC.
"amlogic,g12a-clkc" for G12A SoC.
"amlogic,g12b-clkc" for G12B SoC.
- clocks : list of clock phandle, one for each entry clock-names.
- clock-names : should contain the following:
* "xtal": the platform xtal

7
bindings/clock/at91-clock.txt
View file

@ -9,10 +9,11 @@ Slow Clock controller:
Required properties:
- compatible : shall be one of the following:
"atmel,at91sam9x5-sckc",
"atmel,sama5d3-sckc" or
"atmel,sama5d4-sckc":
"atmel,sama5d3-sckc",
"atmel,sama5d4-sckc" or
"microchip,sam9x60-sckc":
at91 SCKC (Slow Clock Controller)
- #clock-cells : shall be 0.
- #clock-cells : shall be 1 for "microchip,sam9x60-sckc" otherwise shall be 0.
- clocks : shall be the input parent clock phandle for the clock.
Optional properties:

22
bindings/clock/brcm,bcm63xx-clocks.txt Normal file
View file

@ -0,0 +1,22 @@
Gated Clock Controller Bindings for MIPS based BCM63XX SoCs
Required properties:
- compatible: must be one of:
"brcm,bcm3368-clocks"
"brcm,bcm6328-clocks"
"brcm,bcm6358-clocks"
"brcm,bcm6362-clocks"
"brcm,bcm6368-clocks"
"brcm,bcm63268-clocks"
- reg: Address and length of the register set
- #clock-cells: must be <1>
Example:
clkctl: clock-controller@10000004 {
compatible = "brcm,bcm6328-clocks";
reg = <0x10000004 0x4>;
#clock-cells = <1>;
};

1
bindings/clock/cirrus,lochnagar.txt
View file

@ -40,6 +40,7 @@ Optional properties:
input audio clocks from host system.
- ln-psia1-mclk, ln-psia2-mclk : Optional input audio clocks from
external connector.
- ln-spdif-mclk : Optional input audio clock from SPDIF.
- ln-spdif-clkout : Optional input audio clock from SPDIF.
- ln-adat-mclk : Optional input audio clock from ADAT.
- ln-pmic-32k : On board fixed clock.

1
bindings/clock/mvebu-core-clock.txt
View file

@ -59,6 +59,7 @@ Required properties:
"marvell,dove-core-clock" - for Dove SoC core clocks
"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
"marvell,mv98dx1135-core-clock" - for Kirkwood 98dx1135 SoC
"marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC
"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC

4
bindings/clock/qcom,gpucc.txt
View file

@ -2,13 +2,15 @@ Qualcomm Graphics Clock & Reset Controller Binding
--------------------------------------------------
Required properties :
- compatible : shall contain "qcom,sdm845-gpucc"
- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc"
- reg : shall contain base register location and length
- #clock-cells : from common clock binding, shall contain 1
- #reset-cells : from common reset binding, shall contain 1
- #power-domain-cells : from generic power domain binding, shall contain 1
- clocks : shall contain the XO clock
shall contain the gpll0 out main clock (msm8998)
- clock-names : shall be "xo"
shall be "gpll0" (msm8998)
Example:
gpucc: clock-controller@5090000 {

7
bindings/clock/renesas,r9a06g032-sysctrl.txt
View file

@ -13,6 +13,7 @@ Required Properties:
- external (optional) RGMII_REFCLK
- clock-names: Must be:
clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
- #power-domain-cells: Must be 0
Examples
--------
@ -27,6 +28,7 @@ Examples
clocks = <&ext_mclk>, <&ext_rtc_clk>,
<&ext_jtag_clk>, <&ext_rgmii_ref>;
clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
#power-domain-cells = <0>;
};
- Other nodes can use the clocks provided by SYSCTRL as in:
@ -38,6 +40,7 @@ Examples
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART0>;
clock-names = "baudclk";
clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
power-domains = <&sysctrl>;
};

162
bindings/clock/silabs,si5341.txt Normal file
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@ -0,0 +1,162 @@
Binding for Silicon Labs Si5341 and Si5340 programmable i2c clock generator.
Reference
[1] Si5341 Data Sheet
https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
[2] Si5341 Reference Manual
https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
in turn can be directed to any of the 10 (or 4) outputs through a divider.
The internal structure of the clock generators can be found in [2].
The driver can be used in "as is" mode, reading the current settings from the
chip at boot, in case you have a (pre-)programmed device. If the PLL is not
configured when the driver probes, it assumes the driver must fully initialize
it.
The device type, speed grade and revision are determined runtime by probing.
The driver currently only supports XTAL input mode, and does not support any
fancy input configurations. They can still be programmed into the chip and
the driver will leave them "as is".
==I2C device node==
Required properties:
- compatible: shall be one of the following:
"silabs,si5340" - Si5340 A/B/C/D
"silabs,si5341" - Si5341 A/B/C/D
- reg: i2c device address, usually 0x74
- #clock-cells: from common clock binding; shall be set to 2.
The first value is "0" for outputs, "1" for synthesizers.
The second value is the output or synthesizer index.
- clocks: from common clock binding; list of parent clock handles,
corresponding to inputs. Use a fixed clock for the "xtal" input.
At least one must be present.
- clock-names: One of: "xtal", "in0", "in1", "in2"
- vdd-supply: Regulator node for VDD
Optional properties:
- vdda-supply: Regulator node for VDDA
- vdds-supply: Regulator node for VDDS
- silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL
feedback divider. Must be such that the PLL output is in the valid range. For
example, to create 14GHz from a 48MHz xtal, use m-num=14000 and m-den=48. Only
the fraction matters, using 3500 and 12 will deliver the exact same result.
If these are not specified, and the PLL is not yet programmed when the driver
probes, the PLL will be set to 14GHz.
- silabs,reprogram: When present, the driver will always assume the device must
be initialized, and always performs the soft-reset routine. Since this will
temporarily stop all output clocks, don't do this if the chip is generating
the CPU clock for example.
- interrupts: Interrupt for INTRb pin.
- #address-cells: shall be set to 1.
- #size-cells: shall be set to 0.
== Child nodes: Outputs ==
The child nodes list the output clocks.
Each of the clock outputs can be overwritten individually by using a child node.
If a child node for a clock output is not set, the configuration remains
unchanged.
Required child node properties:
- reg: number of clock output.
Optional child node properties:
- vdd-supply: Regulator node for VDD for this output. The driver selects default
values for common-mode and amplitude based on the voltage.
- silabs,format: Output format, one of:
1 = differential (defaults to LVDS levels)
2 = low-power (defaults to HCSL levels)
4 = LVCMOS
- silabs,common-mode: Manually override output common mode, see [2] for values
- silabs,amplitude: Manually override output amplitude, see [2] for values
- silabs,synth-master: boolean. If present, this output is allowed to change the
multisynth frequency dynamically.
- silabs,silabs,disable-high: boolean. If set, the clock output is driven HIGH
when disabled, otherwise it's driven LOW.
==Example==
/* 48MHz reference crystal */
ref48: ref48M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
i2c-master-node {
/* Programmable clock (for logic) */
si5341: clock-generator@74 {
reg = <0x74>;
compatible = "silabs,si5341";
#clock-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&ref48>;
clock-names = "xtal";
silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
silabs,pll-m-den = <48>;
silabs,reprogram; /* Chips are not programmed, always reset */
out@0 {
reg = <0>;
silabs,format = <1>; /* LVDS 3v3 */
silabs,common-mode = <3>;
silabs,amplitude = <3>;
silabs,synth-master;
};
/*
* Output 6 configuration:
* LVDS 1v8
*/
out@6 {
reg = <6>;
silabs,format = <1>; /* LVDS 1v8 */
silabs,common-mode = <13>;
silabs,amplitude = <3>;
};
/*
* Output 8 configuration:
* HCSL 3v3
*/
out@8 {
reg = <8>;
silabs,format = <2>;
silabs,common-mode = <11>;
silabs,amplitude = <3>;
};
};
};
some-video-node {
/* Standard clock bindings */
clock-names = "pixel";
clocks = <&si5341 0 7>; /* Output 7 */
/* Set output 7 to use syntesizer 3 as its parent */
assigned-clocks = <&si5341 0 7>, <&si5341 1 3>;
assigned-clock-parents = <&si5341 1 3>;
/* Set output 7 to 148.5 MHz using a synth frequency of 594 MHz */
assigned-clock-rates = <148500000>, <594000000>;
};
some-audio-node {
clock-names = "i2s-clk";
clocks = <&si5341 0 0>;
/*
* since output 0 is a synth-master, the synth will be automatically set
* to an appropriate frequency when the audio driver requests another
* frequency. We give control over synth 2 to this output here.
*/
assigned-clocks = <&si5341 0 0>;
assigned-clock-parents = <&si5341 1 2>;
};

62
bindings/clock/sunxi-ccu.txt
View file

@ -1,62 +0,0 @@
Allwinner Clock Control Unit Binding
------------------------------------
Required properties :
- compatible: must contain one of the following compatibles:
- "allwinner,sun4i-a10-ccu"
- "allwinner,sun5i-a10s-ccu"
- "allwinner,sun5i-a13-ccu"
- "allwinner,sun6i-a31-ccu"
- "allwinner,sun7i-a20-ccu"
- "allwinner,sun8i-a23-ccu"
- "allwinner,sun8i-a33-ccu"
- "allwinner,sun8i-a83t-ccu"
- "allwinner,sun8i-a83t-r-ccu"
- "allwinner,sun8i-h3-ccu"
- "allwinner,sun8i-h3-r-ccu"
+ - "allwinner,sun8i-r40-ccu"
- "allwinner,sun8i-v3s-ccu"
- "allwinner,sun9i-a80-ccu"
- "allwinner,sun50i-a64-ccu"
- "allwinner,sun50i-a64-r-ccu"
- "allwinner,sun50i-h5-ccu"
- "allwinner,sun50i-h6-ccu"
- "allwinner,sun50i-h6-r-ccu"
- "allwinner,suniv-f1c100s-ccu"
- "nextthing,gr8-ccu"
- reg: Must contain the registers base address and length
- clocks: phandle to the oscillators feeding the CCU. Two are needed:
- "hosc": the high frequency oscillator (usually at 24MHz)
- "losc": the low frequency oscillator (usually at 32kHz)
On the A83T, this is the internal 16MHz oscillator divided by 512
- clock-names: Must contain the clock names described just above
- #clock-cells : must contain 1
- #reset-cells : must contain 1
For the main CCU on H6, one more clock is needed:
- "iosc": the SoC's internal frequency oscillator
For the PRCM CCUs on A83T/H3/A64/H6, two more clocks are needed:
- "pll-periph": the SoC's peripheral PLL from the main CCU
- "iosc": the SoC's internal frequency oscillator
Example for generic CCU:
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-h3-ccu";
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&osc32k>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
};
Example for PRCM CCU:
r_ccu: clock@1f01400 {
compatible = "allwinner,sun50i-a64-r-ccu";
reg = <0x01f01400 0x100>;
clocks = <&osc24M>, <&osc32k>, <&iosc>, <&ccu CLK_PLL_PERIPH0>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
#reset-cells = <1>;
};

17
bindings/common-properties.txt
View file

@ -5,30 +5,29 @@ Endianness
----------
The Devicetree Specification does not define any properties related to hardware
byteswapping, but endianness issues show up frequently in porting Linux to
byte swapping, but endianness issues show up frequently in porting drivers to
different machine types. This document attempts to provide a consistent
way of handling byteswapping across drivers.
way of handling byte swapping across drivers.
Optional properties:
- big-endian: Boolean; force big endian register accesses
unconditionally (e.g. ioread32be/iowrite32be). Use this if you
know the peripheral always needs to be accessed in BE mode.
know the peripheral always needs to be accessed in big endian (BE) mode.
- little-endian: Boolean; force little endian register accesses
unconditionally (e.g. readl/writel). Use this if you know the
peripheral always needs to be accessed in LE mode.
peripheral always needs to be accessed in little endian (LE) mode.
- native-endian: Boolean; always use register accesses matched to the
endianness of the kernel binary (e.g. LE vmlinux -> readl/writel,
BE vmlinux -> ioread32be/iowrite32be). In this case no byteswaps
BE vmlinux -> ioread32be/iowrite32be). In this case no byte swaps
will ever be performed. Use this if the hardware "self-adjusts"
register endianness based on the CPU's configured endianness.
If a binding supports these properties, then the binding should also
specify the default behavior if none of these properties are present.
In such cases, little-endian is the preferred default, but it is not
a requirement. The of_device_is_big_endian() and of_fdt_is_big_endian()
helper functions do assume that little-endian is the default, because
most existing (PCI-based) drivers implicitly default to LE by using
readl/writel for MMIO accesses.
a requirement. Some implementations assume that little-endian is
the default, because most existing (PCI-based) drivers implicitly
default to LE for their MMIO accesses.
Examples:
Scenario 1 : CPU in LE mode & device in LE mode.

37
bindings/cpufreq/imx-cpufreq-dt.txt Normal file
View file

@ -0,0 +1,37 @@
i.MX CPUFreq-DT OPP bindings
================================
Certain i.MX SoCs support different OPPs depending on the "market segment" and
"speed grading" value which are written in fuses. These bits are combined with
the opp-supported-hw values for each OPP to check if the OPP is allowed.
Required properties:
--------------------
For each opp entry in 'operating-points-v2' table:
- opp-supported-hw: Two bitmaps indicating:
- Supported speed grade mask
- Supported market segment mask
0: Consumer
1: Extended Consumer
2: Industrial
3: Automotive
Example:
--------
opp_table {
compatible = "operating-points-v2";
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
/* grade >= 0, consumer only */
opp-supported-hw = <0xf>, <0x3>;
};
opp-1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <1000000>;
/* grade >= 1, all segments */
opp-supported-hw = <0xe>, <0x7>;
};
}

13
bindings/crypto/atmel-crypto.txt
View file

@ -66,16 +66,3 @@ sha@f8034000 {
dmas = <&dma1 2 17>;
dma-names = "tx";
};
* Eliptic Curve Cryptography (I2C)
Required properties:
- compatible : must be "atmel,atecc508a".
- reg: I2C bus address of the device.
- clock-frequency: must be present in the i2c controller node.
Example:
atecc508a@c0 {
compatible = "atmel,atecc508a";
reg = <0xC0>;
};

38
bindings/csky/pmu.txt Normal file
View file

@ -0,0 +1,38 @@
===============================
C-SKY Performance Monitor Units
===============================
C-SKY Performance Monitor is designed for ck807/ck810/ck860 SMP soc and
it could count cpu's events for helping analysis performance issues.
============================
PMU node bindings definition
============================
Description: Describes PMU
PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: must be "csky,csky-pmu"
- interrupts
Usage: required
Value type: <u32 IRQ_TYPE_XXX>
Definition: must be pmu irq num defined by soc
- count-width
Usage: optional
Value type: <u32>
Definition: the width of pmu counter
Examples:
---------
#include <dt-bindings/interrupt-controller/irq.h>
pmu: performace-monitor {
compatible = "csky,csky-pmu";
interrupts = <23 IRQ_TYPE_EDGE_RISING>;
interrupt-parent = <&intc>;
count-width = <48>;
};

23
bindings/display/arm,komeda.txt
View file

@ -7,10 +7,13 @@ Required properties:
- clocks: A list of phandle + clock-specifier pairs, one for each entry
in 'clock-names'
- clock-names: A list of clock names. It should contain:
- "mclk": for the main processor clock
- "pclk": for the APB interface clock
- "aclk": for the main processor clock
- #address-cells: Must be 1
- #size-cells: Must be 0
- iommus: configure the stream id to IOMMU, Must be configured if want to
enable iommu in display. for how to configure this node please reference
devicetree/bindings/iommu/arm,smmu-v3.txt,
devicetree/bindings/iommu/iommu.txt
Required properties for sub-node: pipeline@nq
Each device contains one or two pipeline sub-nodes (at least one), each
@ -20,7 +23,6 @@ pipeline node should provide properties:
in 'clock-names'
- clock-names: should contain:
- "pxclk": pixel clock
- "aclk": AXI interface clock
- port: each pipeline connect to an encoder input port. The connection is
modeled using the OF graph bindings specified in
@ -42,12 +44,15 @@ Example:
compatible = "arm,mali-d71";
reg = <0xc00000 0x20000>;
interrupts = <0 168 4>;
clocks = <&dpu_mclk>, <&dpu_aclk>;
clock-names = "mclk", "pclk";
clocks = <&dpu_aclk>;
clock-names = "aclk";
iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
<&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
<&smmu 8>, <&smmu 9>;
dp0_pipe0: pipeline@0 {
clocks = <&fpgaosc2>, <&dpu_aclk>;
clock-names = "pxclk", "aclk";
clocks = <&fpgaosc2>;
clock-names = "pxclk";
reg = <0>;
port {
@ -58,8 +63,8 @@ Example:
};
dp0_pipe1: pipeline@1 {
clocks = <&fpgaosc2>, <&dpu_aclk>;
clock-names = "pxclk", "aclk";
clocks = <&fpgaosc2>;
clock-names = "pxclk";
reg = <1>;
port {

4
bindings/display/bridge/renesas,dw-hdmi.txt
View file

@ -12,10 +12,12 @@ following device-specific properties.
Required properties:
- compatible : Shall contain one or more of
- "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX
- "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
- "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
- "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
- "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 compatible HDMI TX
- "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 and RZ/G2 compatible
HDMI TX
When compatible with generic versions, nodes must list the SoC-specific
version corresponding to the platform first, followed by the

19
bindings/display/bridge/renesas,lvds.txt
View file

@ -9,6 +9,7 @@ Required properties:
- compatible : Shall contain one of
- "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders
- "renesas,r8a7744-lvds" for R8A7744 (RZ/G1N) compatible LVDS encoders
- "renesas,r8a774a1-lvds" for R8A774A1 (RZ/G2M) compatible LVDS encoders
- "renesas,r8a774c0-lvds" for R8A774C0 (RZ/G2E) compatible LVDS encoders
- "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders
- "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders
@ -45,14 +46,24 @@ OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
Each port shall have a single endpoint.
Optional properties:
- renesas,companion : phandle to the companion LVDS encoder. This property is
mandatory for the first LVDS encoder on D3 and E3 SoCs, and shall point to
the second encoder to be used as a companion in dual-link mode. It shall not
be set for any other LVDS encoder.
Example:
lvds0: lvds@feb90000 {
compatible = "renesas,r8a7790-lvds";
reg = <0 0xfeb90000 0 0x1c>;
clocks = <&cpg CPG_MOD 726>;
resets = <&cpg 726>;
compatible = "renesas,r8a77990-lvds";
reg = <0 0xfeb90000 0 0x20>;
clocks = <&cpg CPG_MOD 727>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 727>;
renesas,companion = <&lvds1>;
ports {
#address-cells = <1>;

42
bindings/display/bridge/sii902x.txt
View file

@ -5,10 +5,44 @@ Required properties:
- reg: i2c address of the bridge
Optional properties:
- interrupts: describe the interrupt line used to inform the host
- interrupts: describe the interrupt line used to inform the host
about hotplug events.
- reset-gpios: OF device-tree gpio specification for RST_N pin.
HDMI audio properties:
- #sound-dai-cells: <0> or <1>. <0> if only i2s or spdif pin
is wired, <1> if the both are wired. HDMI audio is
configured only if this property is found.
- sil,i2s-data-lanes: Array of up to 4 integers with values of 0-3
Each integer indicates which i2s pin is connected to which
audio fifo. The first integer selects i2s audio pin for the
first audio fifo#0 (HDMI channels 1&2), second for fifo#1
(HDMI channels 3&4), and so on. There is 4 fifos and 4 i2s
pins (SD0 - SD3). Any i2s pin can be connected to any fifo,
but there can be no gaps. E.g. an i2s pin must be mapped to
fifo#0 and fifo#1 before mapping a channel to fifo#2. Default
value is <0>, describing SD0 pin beiging routed to hdmi audio
fifo #0.
- clocks: phandle and clock specifier for each clock listed in
the clock-names property
- clock-names: "mclk"
Describes SII902x MCLK input. MCLK is used to produce
HDMI audio CTS values. This property is required if
"#sound-dai-cells"-property is present. This property follows
Documentation/devicetree/bindings/clock/clock-bindings.txt
consumer binding.
If HDMI audio is configured the sii902x device becomes an I2S
and/or spdif audio codec component (e.g a digital audio sink),
that can be used in configuring a full audio devices with
simple-card or audio-graph-card binding. See their binding
documents on how to describe the way the sii902x device is
connected to the rest of the audio system:
Documentation/devicetree/bindings/sound/simple-card.txt
Documentation/devicetree/bindings/sound/audio-graph-card.txt
Note: In case of the audio-graph-card binding the used port
index should be 3.
Optional subnodes:
- video input: this subnode can contain a video input port node
to connect the bridge to a display controller output (See this
@ -21,6 +55,12 @@ Example:
compatible = "sil,sii9022";
reg = <0x39>;
reset-gpios = <&pioA 1 0>;
#sound-dai-cells = <0>;
sil,i2s-data-lanes = < 0 1 2 >;
clocks = <&mclk>;
clock-names = "mclk";
ports {
#address-cells = <1>;
#size-cells = <0>;

6
bindings/display/bridge/thine,thc63lvd1024.txt
View file

@ -28,6 +28,12 @@ Optional video port nodes:
- port@1: Second LVDS input port
- port@3: Second digital CMOS/TTL parallel output
The device can operate in single-link mode or dual-link mode. In single-link
mode, all pixels are received on port@0, and port@1 shall not contain any
endpoint. In dual-link mode, even-numbered pixels are received on port@0 and
odd-numbered pixels on port@1, and both port@0 and port@1 shall contain
endpoints.
Example:
--------

1
bindings/display/bridge/toshiba,tc358767.txt
View file

@ -12,6 +12,7 @@ Optional properties:
(active high shutdown input)
- reset-gpios: OF device-tree gpio specification for RSTX pin
(active low system reset)
- toshiba,hpd-pin: TC358767 GPIO pin number to which HPD is connected to (0 or 1)
- ports: the ports node can contain video interface port nodes to connect
to a DPI/DSI source and to an eDP/DP sink according to [1][2]:
- port@0: DSI input port

44
bindings/display/ingenic,lcd.txt Normal file
View file

@ -0,0 +1,44 @@
Ingenic JZ47xx LCD driver
Required properties:
- compatible: one of:
* ingenic,jz4740-lcd
* ingenic,jz4725b-lcd
- reg: LCD registers location and length
- clocks: LCD pixclock and device clock specifiers.
The device clock is only required on the JZ4740.
- clock-names: "lcd_pclk" and "lcd"
- interrupts: Specifies the interrupt line the LCD controller is connected to.
Example:
panel {
compatible = "sharp,ls020b1dd01d";
backlight = <&backlight>;
power-supply = <&vcc>;
port {
panel_input: endpoint {
remote-endpoint = <&panel_output>;
};
};
};
lcd: lcd-controller@13050000 {
compatible = "ingenic,jz4725b-lcd";
reg = <0x13050000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <31>;
clocks = <&cgu JZ4725B_CLK_LCD>;
clock-names = "lcd";
port {
panel_output: endpoint {
remote-endpoint = <&panel_input>;
};
};
};

10
bindings/display/msm/dpu.txt
View file

@ -28,6 +28,11 @@ Required properties:
- #address-cells: number of address cells for the MDSS children. Should be 1.
- #size-cells: Should be 1.
- ranges: parent bus address space is the same as the child bus address space.
- interconnects : interconnect path specifier for MDSS according to
Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be
2 paths corresponding to 2 AXI ports.
- interconnect-names : MDSS will have 2 port names to differentiate between the
2 interconnect paths defined with interconnect specifier.
Optional properties:
- assigned-clocks: list of clock specifiers for clocks needing rate assignment
@ -86,6 +91,11 @@ Example:
interrupt-controller;
#interrupt-cells = <1>;
interconnects = <&rsc_hlos MASTER_MDP0 &rsc_hlos SLAVE_EBI1>,
<&rsc_hlos MASTER_MDP1 &rsc_hlos SLAVE_EBI1>;
interconnect-names = "mdp0-mem", "mdp1-mem";
iommus = <&apps_iommu 0>;
#address-cells = <2>;

1
bindings/display/msm/dsi.txt
View file

@ -88,6 +88,7 @@ Required properties:
* "qcom,dsi-phy-28nm-8960"
* "qcom,dsi-phy-14nm"
* "qcom,dsi-phy-10nm"
* "qcom,dsi-phy-10nm-8998"
- reg: Physical base address and length of the registers of PLL, PHY. Some
revisions require the PHY regulator base address, whereas others require the
PHY lane base address. See below for each PHY revision.

9
bindings/display/panel/armadeus,st0700-adapt.txt Normal file
View file

@ -0,0 +1,9 @@
Armadeus ST0700 Adapt. A Santek ST0700I5Y-RBSLW 7.0" WVGA (800x480) TFT with
an adapter board.
Required properties:
- compatible: "armadeus,st0700-adapt"
- power-supply: see panel-common.txt
Optional properties:
- backlight: see panel-common.txt

16
bindings/display/panel/edt,et-series.txt
View file

@ -6,6 +6,22 @@ Display bindings for EDT Display Technology Corp. Displays which are
compatible with the simple-panel binding, which is specified in
simple-panel.txt
3,5" QVGA TFT Panels
--------------------
+-----------------+---------------------+-------------------------------------+
| Identifier | compatbile | description |
+=================+=====================+=====================================+
| ET035012DM6 | edt,et035012dm6 | 3.5" QVGA TFT LCD panel |
+-----------------+---------------------+-------------------------------------+
4,3" WVGA TFT Panels
--------------------
+-----------------+---------------------+-------------------------------------+
| Identifier | compatbile | description |
+=================+=====================+=====================================+
| ETM0430G0DH6 | edt,etm0430g0dh6 | 480x272 TFT Display |
+-----------------+---------------------+-------------------------------------+
5,7" WVGA TFT Panels
--------------------

12
bindings/display/panel/evervision,vgg804821.txt Normal file
View file

@ -0,0 +1,12 @@
Evervision Electronics Co. Ltd. VGG804821 5.0" WVGA TFT LCD Panel
Required properties:
- compatible: should be "evervision,vgg804821"
- power-supply: See simple-panel.txt
Optional properties:
- backlight: See simple-panel.txt
- enable-gpios: See simple-panel.txt
This binding is compatible with the simple-panel binding, which is specified
in simple-panel.txt in this directory.

32
bindings/display/panel/friendlyarm,hd702e.txt Normal file
View file

@ -0,0 +1,32 @@
FriendlyELEC HD702E 800x1280 LCD panel
HD702E lcd is FriendlyELEC developed eDP LCD panel with 800x1280
resolution. It has built in Goodix, GT9271 captive touchscreen
with backlight adjustable via PWM.
Required properties:
- compatible: should be "friendlyarm,hd702e"
- power-supply: regulator to provide the supply voltage
Optional properties:
- backlight: phandle of the backlight device attached to the panel
Optional nodes:
- Video port for LCD panel input.
This binding is compatible with the simple-panel binding, which is specified
in simple-panel.txt in this directory.
Example:
panel {
compatible ="friendlyarm,hd702e", "simple-panel";
backlight = <&backlight>;
power-supply = <&vcc3v3_sys>;
port {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
};
};

42
bindings/display/panel/koe,tx14d24vm1bpa.txt Normal file
View file

@ -0,0 +1,42 @@
Kaohsiung Opto-Electronics Inc. 5.7" QVGA (320 x 240) TFT LCD panel
Required properties:
- compatible: should be "koe,tx14d24vm1bpa"
- backlight: phandle of the backlight device attached to the panel
- power-supply: single regulator to provide the supply voltage
Required nodes:
- port: Parallel port mapping to connect this display
This panel needs single power supply voltage. Its backlight is conntrolled
via PWM signal.
Example:
--------
Example device-tree definition when connected to iMX53 based board
lcd_panel: lcd-panel {
compatible = "koe,tx14d24vm1bpa";
backlight = <&backlight_lcd>;
power-supply = <&reg_3v3>;
port {
lcd_panel_in: endpoint {
remote-endpoint = <&lcd_display_out>;
};
};
};
Then one needs to extend the dispX node:
lcd_display: disp1 {
port@1 {
reg = <1>;
lcd_display_out: endpoint {
remote-endpoint = <&lcd_panel_in>;
};
};
};

11
bindings/display/panel/osddisplays,osd101t2045-53ts.txt Normal file
View file

@ -0,0 +1,11 @@
One Stop Displays OSD101T2045-53TS 10.1" 1920x1200 panel
Required properties:
- compatible: should be "osddisplays,osd101t2045-53ts"
- power-supply: as specified in the base binding
Optional properties:
- backlight: as specified in the base binding
This binding is compatible with the simple-panel binding, which is specified
in simple-panel.txt in this directory.

14
bindings/display/panel/osddisplays,osd101t2587-53ts.txt Normal file
View file

@ -0,0 +1,14 @@
One Stop Displays OSD101T2587-53TS 10.1" 1920x1200 panel
The panel is similar to OSD101T2045-53TS, but it needs additional
MIPI_DSI_TURN_ON_PERIPHERAL message from the host.
Required properties:
- compatible: should be "osddisplays,osd101t2587-53ts"
- power-supply: as specified in the base binding
Optional properties:
- backlight: as specified in the base binding
This binding is compatible with the simple-panel binding, which is specified
in simple-panel.txt in this directory.

33
bindings/display/panel/samsung,s6e63m0.txt Normal file
View file

@ -0,0 +1,33 @@
Samsung s6e63m0 AMOLED LCD panel
Required properties:
- compatible: "samsung,s6e63m0"
- reset-gpios: GPIO spec for reset pin
- vdd3-supply: VDD regulator
- vci-supply: VCI regulator
The panel must obey rules for SPI slave device specified in document [1].
The device node can contain one 'port' child node with one child
'endpoint' node, according to the bindings defined in [2]. This
node should describe panel's video bus.
[1]: Documentation/devicetree/bindings/spi/spi-bus.txt
[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
Example:
s6e63m0: display@0 {
compatible = "samsung,s6e63m0";
reg = <0>;
reset-gpio = <&mp05 5 1>;
vdd3-supply = <&ldo12_reg>;
vci-supply = <&ldo11_reg>;
spi-max-frequency = <1200000>;
port {
lcd_ep: endpoint {
remote-endpoint = <&fimd_ep>;
};
};
};

15
bindings/display/panel/tfc,s9700rtwv43tr-01b.txt Normal file
View file

@ -0,0 +1,15 @@
TFC S9700RTWV43TR-01B 7" Three Five Corp 800x480 LCD panel with
resistive touch
The panel is found on TI AM335x-evm.
Required properties:
- compatible: should be "tfc,s9700rtwv43tr-01b"
- power-supply: See panel-common.txt
Optional properties:
- enable-gpios: GPIO pin to enable or disable the panel, if there is one
- backlight: phandle of the backlight device attached to the panel
This binding is compatible with the simple-panel binding, which is specified
in simple-panel.txt in this directory.

12
bindings/display/panel/vl050_8048nt_c01.txt Normal file
View file

@ -0,0 +1,12 @@
VXT 800x480 color TFT LCD panel
Required properties:
- compatible: should be "vxt,vl050-8048nt-c01"
- power-supply: as specified in the base binding
Optional properties:
- backlight: as specified in the base binding
- enable-gpios: as specified in the base binding
This binding is compatible with the simple-panel binding, which is specified
in simple-panel.txt in this directory.

2
bindings/display/renesas,du.txt
View file

@ -7,6 +7,7 @@ Required Properties:
- "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU
- "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU
- "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU
- "renesas,du-r8a774a1" for R8A774A1 (RZ/G2M) compatible DU
- "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU
- "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
- "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
@ -58,6 +59,7 @@ corresponding to each DU output.
R8A7744 (RZ/G1N) DPAD 0 LVDS 0 - -
R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - -
R8A77470 (RZ/G1C) DPAD 0 DPAD 1 LVDS 0 -
R8A774A1 (RZ/G2M) DPAD 0 HDMI 0 LVDS 0 -
R8A774C0 (RZ/G2E) DPAD 0 LVDS 0 LVDS 1 -
R8A7779 (R-Car H1) DPAD 0 DPAD 1 - -
R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 -

8
bindings/display/rockchip/dw_hdmi-rockchip.txt
View file

@ -12,6 +12,7 @@ following device-specific properties.
Required properties:
- compatible: should be one of the following:
"rockchip,rk3228-dw-hdmi"
"rockchip,rk3288-dw-hdmi"
"rockchip,rk3328-dw-hdmi"
"rockchip,rk3399-dw-hdmi"
@ -38,6 +39,13 @@ Optional properties
- phys: from general PHY binding: the phandle for the PHY device.
- phy-names: Should be "hdmi" if phys references an external phy.
Optional pinctrl entry:
- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
will switch to the unwedge pinctrl state for 10ms if it ever gets an
i2c timeout. It's intended that this unwedge pinctrl entry will
cause the SDA line to be driven low to work around a hardware
errata.
Example:
hdmi: hdmi@ff980000 {

3
bindings/display/st,stm32-ltdc.txt
View file

@ -40,6 +40,8 @@ Mandatory nodes specific to STM32 DSI:
- panel or bridge node: A node containing the panel or bridge description as
documented in [6].
- port: panel or bridge port node, connected to the DSI output port (port@1).
Optional properties:
- phy-dsi-supply: phandle of the regulator that provides the supply voltage.
Note: You can find more documentation in the following references
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
@ -101,6 +103,7 @@ Example 2: DSI panel
clock-names = "pclk", "ref";
resets = <&rcc STM32F4_APB2_RESET(DSI)>;
reset-names = "apb";
phy-dsi-supply = <&reg18>;
ports {
#address-cells = <1>;

93
bindings/display/sunxi/sun6i-dsi.txt
View file

@ -1,93 +0,0 @@
Allwinner A31 DSI Encoder
=========================
The DSI pipeline consists of two separate blocks: the DSI controller
itself, and its associated D-PHY.
DSI Encoder
-----------
The DSI Encoder generates the DSI signal from the TCON's.
Required properties:
- compatible: value must be one of:
* allwinner,sun6i-a31-mipi-dsi
- reg: base address and size of memory-mapped region
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the DSI encoder
* bus: the DSI interface clock
* mod: the DSI module clock
- clock-names: the clock names mentioned above
- phys: phandle to the D-PHY
- phy-names: must be "dphy"
- resets: phandle to the reset controller driving the encoder
- ports: A ports node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. The
first port should be the input endpoint, usually coming from the
associated TCON.
Any MIPI-DSI device attached to this should be described according to
the bindings defined in ../mipi-dsi-bus.txt
D-PHY
-----
Required properties:
- compatible: value must be one of:
* allwinner,sun6i-a31-mipi-dphy
- reg: base address and size of memory-mapped region
- clocks: phandles to the clocks feeding the DSI encoder
* bus: the DSI interface clock
* mod: the DSI module clock
- clock-names: the clock names mentioned above
- resets: phandle to the reset controller driving the encoder
Example:
dsi0: dsi@1ca0000 {
compatible = "allwinner,sun6i-a31-mipi-dsi";
reg = <0x01ca0000 0x1000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MIPI_DSI>,
<&ccu CLK_DSI_SCLK>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_MIPI_DSI>;
phys = <&dphy0>;
phy-names = "dphy";
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
compatible = "bananapi,lhr050h41", "ilitek,ili9881c";
reg = <0>;
power-gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; /* PB07 */
reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */
backlight = <&pwm_bl>;
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
dsi0_in_tcon0: endpoint {
remote-endpoint = <&tcon0_out_dsi0>;
};
};
};
};
dphy0: d-phy@1ca1000 {
compatible = "allwinner,sun6i-a31-mipi-dphy";
reg = <0x01ca1000 0x1000>;
clocks = <&ccu CLK_BUS_MIPI_DSI>,
<&ccu CLK_DSI_DPHY>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_MIPI_DSI>;
#phy-cells = <0>;
};

33
bindings/dma/8250_mtk_dma.txt
View file

@ -1,33 +0,0 @@
* Mediatek UART APDMA Controller
Required properties:
- compatible should contain:
* "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA
* "mediatek,mt6577-uart-dma" for MT6577 and all of the above
- reg: The base address of the APDMA register bank.
- interrupts: A single interrupt specifier.
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: The APDMA clock for register accesses
Examples:
apdma: dma-controller@11000380 {
compatible = "mediatek,mt2712-uart-dma";
reg = <0 0x11000380 0 0x400>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 66 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_AP_DMA>;
clock-names = "apdma";
#dma-cells = <1>;
};

3
bindings/dma/arm-pl330.txt
View file

@ -16,6 +16,9 @@ Optional properties:
- dma-channels: contains the total number of DMA channels supported by the DMAC
- dma-requests: contains the total number of DMA requests supported by the DMAC
- arm,pl330-broken-no-flushp: quirk for avoiding to execute DMAFLUSHP
- resets: contains an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: must contain at least "dma", and optional is "dma-ocp".
Example:

44
bindings/dma/fsl-edma.txt
View file

@ -9,15 +9,16 @@ group, DMAMUX0 or DMAMUX1, but not both.
Required properties:
- compatible :
- "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC
- "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp
- reg : Specifies base physical address(s) and size of the eDMA registers.
The 1st region is eDMA control register's address and size.
The 2nd and the 3rd regions are programmable channel multiplexing
control register's address and size.
- interrupts : A list of interrupt-specifiers, one for each entry in
interrupt-names.
- interrupt-names : Should contain:
"edma-tx" - the transmission interrupt
"edma-err" - the error interrupt
interrupt-names on vf610 similar SoC. But for i.mx7ulp per channel
per transmission interrupt, total 16 channel interrupt and 1
error interrupt(located in the last), no interrupt-names list on
i.mx7ulp for clean on dts.
- #dma-cells : Must be <2>.
The 1st cell specifies the DMAMUX(0 for DMAMUX0 and 1 for DMAMUX1).
Specific request source can only be multiplexed by specific channels
@ -28,6 +29,7 @@ Required properties:
- clock-names : A list of channel group clock names. Should contain:
"dmamux0" - clock name of mux0 group
"dmamux1" - clock name of mux1 group
Note: No dmamux0 on i.mx7ulp, but another 'dma' clk added on i.mx7ulp.
- clocks : A list of phandle and clock-specifier pairs, one for each entry in
clock-names.
@ -35,6 +37,10 @@ Optional properties:
- big-endian: If present registers and hardware scatter/gather descriptors
of the eDMA are implemented in big endian mode, otherwise in little
mode.
- interrupt-names : Should contain the below on vf610 similar SoC but not used
on i.mx7ulp similar SoC:
"edma-tx" - the transmission interrupt
"edma-err" - the error interrupt
Examples:
@ -52,8 +58,36 @@ edma0: dma-controller@40018000 {
clock-names = "dmamux0", "dmamux1";
clocks = <&clks VF610_CLK_DMAMUX0>,
<&clks VF610_CLK_DMAMUX1>;
};
}; /* vf610 */
edma1: dma-controller@40080000 {
#dma-cells = <2>;
compatible = "fsl,imx7ulp-edma";
reg = <0x40080000 0x2000>,
<0x40210000 0x1000>;
dma-channels = <32>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
/* last is eDMA2-ERR interrupt */
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dma", "dmamux0";
clocks = <&pcc2 IMX7ULP_CLK_DMA1>,
<&pcc2 IMX7ULP_CLK_DMA_MUX1>;
}; /* i.mx7ulp */
* DMA clients
DMA client drivers that uses the DMA function must use the format described

1
bindings/dma/fsl-qdma.txt
View file

@ -7,6 +7,7 @@ Required properties:
- compatible: Must be one of
"fsl,ls1021a-qdma": for LS1021A Board
"fsl,ls1028a-qdma": for LS1028A Board
"fsl,ls1043a-qdma": for ls1043A Board
"fsl,ls1046a-qdma": for ls1046A Board
- reg: Should contain the register's base address and length.

54
bindings/dma/mtk-uart-apdma.txt Normal file
View file

@ -0,0 +1,54 @@
* Mediatek UART APDMA Controller
Required properties:
- compatible should contain:
* "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA
* "mediatek,mt6577-uart-dma" for MT6577 and all of the above
- reg: The base address of the APDMA register bank.
- interrupts: A single interrupt specifier.
One interrupt per dma-requests, or 8 if no dma-requests property is present
- dma-requests: The number of DMA channels
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: The APDMA clock for register accesses
- mediatek,dma-33bits: Present if the DMA requires support
Examples:
apdma: dma-controller@11000400 {
compatible = "mediatek,mt2712-uart-dma";
reg = <0 0x11000400 0 0x80>,
<0 0x11000480 0 0x80>,
<0 0x11000500 0 0x80>,
<0 0x11000580 0 0x80>,
<0 0x11000600 0 0x80>,
<0 0x11000680 0 0x80>,
<0 0x11000700 0 0x80>,
<0 0x11000780 0 0x80>,
<0 0x11000800 0 0x80>,
<0 0x11000880 0 0x80>,
<0 0x11000900 0 0x80>,
<0 0x11000980 0 0x80>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
dma-requests = <12>;
clocks = <&pericfg CLK_PERI_AP_DMA>;
clock-names = "apdma";
mediatek,dma-33bits;
#dma-cells = <1>;
};

9
bindings/dma/sun6i-dma.txt
View file

@ -28,12 +28,17 @@ Example:
};
------------------------------------------------------------------------------
For A64 DMA controller:
For A64 and H6 DMA controller:
Required properties:
- compatible: "allwinner,sun50i-a64-dma"
- compatible: Must be one of
"allwinner,sun50i-a64-dma"
"allwinner,sun50i-h6-dma"
- dma-channels: Number of DMA channels supported by the controller.
Refer to Documentation/devicetree/bindings/dma/dma.txt
- clocks: In addition to parent AHB clock, it should also contain mbus
clock (H6 only)
- clock-names: Should contain "bus" and "mbus" (H6 only)
- all properties above, i.e. reg, interrupts, clocks, resets and #dma-cells
Optional properties:

19
bindings/extcon/extcon-fsa9480.txt Normal file
View file

@ -0,0 +1,19 @@
FAIRCHILD SEMICONDUCTOR FSA9480 MICROUSB SWITCH
The FSA9480 is a USB port accessory detector and switch. The FSA9480 is fully
controlled using I2C and enables USB data, stereo and mono audio, video,
microphone, and UART data to use a common connector port.
Required properties:
- compatible : Must be "fcs,fsa9480"
- reg : Specifies i2c slave address. Must be 0x25.
- interrupts : Should contain one entry specifying interrupt signal of
interrupt parent to which interrupt pin of the chip is connected.
Example:
musb@25 {
compatible = "fcs,fsa9480";
reg = <0x25>;
interrupt-parent = <&gph2>;
interrupts = <7 0>;
};

2
bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
View file

@ -2,7 +2,7 @@
# Copyright 2019 Linaro Ltd.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/firmware/intel-ixp4xx-network-processing-engine.yaml#"
$id: "http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Intel IXP4xx Network Processing Engine

18
bindings/gpio/gpio-davinci.txt
View file

@ -5,6 +5,7 @@ Required Properties:
"ti,keystone-gpio": for Keystone 2 66AK2H/K, 66AK2L,
66AK2E SoCs
"ti,k2g-gpio", "ti,keystone-gpio": for 66AK2G
"ti,am654-gpio", "ti,keystone-gpio": for TI K3 AM654
- reg: Physical base address of the controller and the size of memory mapped
registers.
@ -145,3 +146,20 @@ gpio0: gpio@260bf00 {
ti,ngpio = <32>;
ti,davinci-gpio-unbanked = <32>;
};
Example for K3 AM654:
wkup_gpio0: wkup_gpio0@42110000 {
compatible = "ti,am654-gpio", "ti,keystone-gpio";
reg = <0x42110000 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&intr_wkup_gpio>;
interrupts = <59 128>, <59 129>, <59 130>, <59 131>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <56>;
ti,davinci-gpio-unbanked = <0>;
clocks = <&k3_clks 59 0>;
clock-names = "gpio";
};

10
bindings/gpio/pl061-gpio.txt
View file

@ -1,10 +0,0 @@
ARM PL061 GPIO controller
Required properties:
- compatible : "arm,pl061", "arm,primecell"
- #gpio-cells : Should be two. The first cell is the pin number and the
second cell is used to specify optional parameters:
- bit 0 specifies polarity (0 for normal, 1 for inverted)
- gpio-controller : Marks the device node as a GPIO controller.
- interrupts : Interrupt mapping for GPIO IRQ.
- gpio-ranges : Interaction with the PINCTRL subsystem.

69
bindings/gpio/pl061-gpio.yaml Normal file
View file

@ -0,0 +1,69 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/pl061-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM PL061 GPIO controller
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Rob Herring <robh@kernel.org>
# We need a select here so we don't match all nodes with 'arm,primecell'
select:
properties:
compatible:
contains:
const: arm,pl061
required:
- compatible
properties:
$nodename:
pattern: "^gpio@[0-9a-f]+$"
compatible:
items:
- const: arm,pl061
- const: arm,primecell
reg:
maxItems: 1
interrupts:
oneOf:
- maxItems: 1
- maxItems: 8
interrupt-controller: true
"#interrupt-cells":
const: 2
clocks:
maxItems: 1
clock-names: true
"#gpio-cells":
const: 2
gpio-controller: true
gpio-ranges:
maxItems: 8
required:
- compatible
- reg
- interrupts
- interrupt-controller
- "#interrupt-cells"
- clocks
- "#gpio-cells"
- gpio-controller
additionalProperties: false
...

20
bindings/gpu/arm,mali-midgard.txt
View file

@ -15,7 +15,9 @@ Required properties:
+ "arm,mali-t860"
+ "arm,mali-t880"
* which must be preceded by one of the following vendor specifics:
+ "allwinner,sun50i-h6-mali"
+ "amlogic,meson-gxm-mali"
+ "samsung,exynos5433-mali"
+ "rockchip,rk3288-mali"
+ "rockchip,rk3399-mali"
@ -31,21 +33,36 @@ Optional properties:
- clocks : Phandle to clock for the Mali Midgard device.
- clock-names : Specify the names of the clocks specified in clocks
when multiple clocks are present.
* core: clock driving the GPU itself (When only one clock is present,
assume it's this clock.)
* bus: bus clock for the GPU
- mali-supply : Phandle to regulator for the Mali device. Refer to
Documentation/devicetree/bindings/regulator/regulator.txt for details.
- operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt
for details.
- #cooling-cells: Refer to Documentation/devicetree/bindings/thermal/thermal.txt
for details.
- resets : Phandle of the GPU reset line.
Vendor-specific bindings
------------------------
The Mali GPU is integrated very differently from one SoC to
another. In order to accomodate those differences, you have the option
another. In order to accommodate those differences, you have the option
to specify one more vendor-specific compatible, among:
- "allwinner,sun50i-h6-mali"
Required properties:
- clocks : phandles to core and bus clocks
- clock-names : must contain "core" and "bus"
- resets: phandle to GPU reset line
- "amlogic,meson-gxm-mali"
Required properties:
- resets : Should contain phandles of :
@ -65,6 +82,7 @@ gpu@ffa30000 {
mali-supply = <&vdd_gpu>;
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&power RK3288_PD_GPU>;
#cooling-cells = <2>;
};
gpu_opp_table: opp_table0 {

1
bindings/gpu/arm,mali-utgard.txt
View file

@ -17,6 +17,7 @@ Required properties:
+ amlogic,meson8b-mali
+ amlogic,meson-gxbb-mali
+ amlogic,meson-gxl-mali
+ samsung,exynos4210-mali
+ rockchip,rk3036-mali
+ rockchip,rk3066-mali
+ rockchip,rk3188-mali

25
bindings/hwlock/omap-hwspinlock.txt
View file

@ -1,12 +1,16 @@
OMAP4+ HwSpinlock Driver
========================
TI HwSpinlock for OMAP and K3 based SoCs
=========================================
Required properties:
- compatible: Should be "ti,omap4-hwspinlock" for
OMAP44xx, OMAP54xx, AM33xx, AM43xx, DRA7xx SoCs
- compatible: Should be one of the following,
"ti,omap4-hwspinlock" for
OMAP44xx, OMAP54xx, AM33xx, AM43xx, DRA7xx SoCs
"ti,am654-hwspinlock" for
K3 AM65x and J721E SoCs
- reg: Contains the hwspinlock module register address space
(base address and length)
- ti,hwmods: Name of the hwmod associated with the hwspinlock device
(for OMAP architecture based SoCs only)
- #hwlock-cells: Should be 1. The OMAP hwspinlock users will use a
0-indexed relative hwlock number as the argument
specifier value for requesting a specific hwspinlock
@ -17,10 +21,21 @@ Please look at the generic hwlock binding for usage information for consumers,
Example:
/* OMAP4 */
1. OMAP4 SoCs
hwspinlock: spinlock@4a0f6000 {
compatible = "ti,omap4-hwspinlock";
reg = <0x4a0f6000 0x1000>;
ti,hwmods = "spinlock";
#hwlock-cells = <1>;
};
2. AM65x SoCs and J721E SoCs
&cbass_main {
cbass_main_navss: interconnect0 {
hwspinlock: spinlock@30e00000 {
compatible = "ti,am654-hwspinlock";
reg = <0x00 0x30e00000 0x00 0x1000>;
#hwlock-cells = <1>;
};
};
};

25
bindings/i2c/i2c-mt7621.txt Normal file
View file

@ -0,0 +1,25 @@
MediaTek MT7621/MT7628 I2C master controller
Required properties:
- compatible: Should be one of the following:
- "mediatek,mt7621-i2c": for MT7621/MT7628/MT7688 platforms
- #address-cells: should be 1.
- #size-cells: should be 0.
- reg: Address and length of the register set for the device
- resets: phandle to the reset controller asserting this device in
reset
See ../reset/reset.txt for details.
Optional properties :
Example:
i2c: i2c@900 {
compatible = "mediatek,mt7621-i2c";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&rstctrl 16>;
reset-names = "i2c";
};

64
bindings/i2c/i2c-mv64xxx.txt
View file

@ -1,64 +0,0 @@
* Marvell MV64XXX I2C controller
Required properties :
- reg : Offset and length of the register set for the device
- compatible : Should be either:
- "allwinner,sun4i-a10-i2c"
- "allwinner,sun6i-a31-i2c"
- "marvell,mv64xxx-i2c"
- "marvell,mv78230-i2c"
- "marvell,mv78230-a0-i2c"
* Note: Only use "marvell,mv78230-a0-i2c" for a
very rare, initial version of the SoC which
had broken offload support. Linux
auto-detects this and sets it appropriately.
- interrupts : The interrupt number
Optional properties :
- clock-frequency : Desired I2C bus clock frequency in Hz. If not set the
default frequency is 100kHz
- resets : phandle to the parent reset controller. Mandatory
whenever you're using the "allwinner,sun6i-a31-i2c"
compatible.
- clocks: : pointers to the reference clocks for this device, the
first one is the one used for the clock on the i2c bus,
the second one is the clock used to acces the registers
of the controller
- clock-names : names of used clocks, mandatory if the second clock is
used, the name must be "core", and "reg" (the latter is
only for Armada 7K/8K).
Examples:
i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11000 0x20>;
interrupts = <29>;
clock-frequency = <100000>;
};
For the Armada XP:
i2c@11000 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11000 0x100>;
interrupts = <29>;
clock-frequency = <100000>;
};
For the Armada 7040:
i2c@701000 {
compatible = "marvell,mv78230-i2c";
reg = <0x701000 0x20>;
interrupts = <29>;
clock-frequency = <100000>;
clock-names = "core", "reg";
clocks = <&core_clock>, <&reg_clock>;
};

9
bindings/i2c/i2c-ocores.txt
View file

@ -1,9 +1,13 @@
Device tree configuration for i2c-ocores
Required properties:
- compatible : "opencores,i2c-ocores" or "aeroflexgaisler,i2cmst"
- compatible : "opencores,i2c-ocores"
"aeroflexgaisler,i2cmst"
"sifive,fu540-c000-i2c", "sifive,i2c0"
For Opencore based I2C IP block reimplemented in
FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt
for additional details.
- reg : bus address start and address range size of device
- interrupts : interrupt number
- clocks : handle to the controller clock; see the note below.
Mutually exclusive with opencores,ip-clock-frequency
- opencores,ip-clock-frequency: frequency of the controller clock in Hz;
@ -12,6 +16,7 @@ Required properties:
- #size-cells : should be <0>
Optional properties:
- interrupts : interrupt number.
- clock-frequency : frequency of bus clock in Hz; see the note below.
Defaults to 100 KHz when the property is not specified
- reg-shift : device register offsets are shifted by this value

1
bindings/i2c/i2c-omap.txt
View file

@ -7,6 +7,7 @@ Required properties :
"ti,omap3-i2c" for OMAP3 SoCs
"ti,omap4-i2c" for OMAP4+ SoCs
"ti,am654-i2c", "ti,omap4-i2c" for AM654 SoCs
"ti,j721e-i2c", "ti,omap4-i2c" for J721E SoCs
- ti,hwmods : Must be "i2c<n>", n being the instance number (1-based)
- #address-cells = <1>;
- #size-cells = <0>;

2
bindings/i2c/i2c-stm32.txt
View file

@ -21,6 +21,8 @@ Optional properties:
100000 and 400000.
For STM32F7, STM32H7 and STM32MP1 SoCs, Standard-mode, Fast-mode and Fast-mode
Plus are supported, possible values are 100000, 400000 and 1000000.
- dmas: List of phandles to rx and tx DMA channels. Refer to stm32-dma.txt.
- dma-names: List of dma names. Valid names are: "rx" and "tx".
- i2c-scl-rising-time-ns: I2C SCL Rising time for the board (default: 25)
For STM32F7, STM32H7 and STM32MP1 only.
- i2c-scl-falling-time-ns: I2C SCL Falling time for the board (default: 10)

41
bindings/i2c/i2c-sun6i-p2wi.txt
View file

@ -1,41 +0,0 @@
* Allwinner P2WI (Push/Pull 2 Wire Interface) controller
Required properties :
- reg : Offset and length of the register set for the device.
- compatible : Should one of the following:
- "allwinner,sun6i-a31-p2wi"
- interrupts : The interrupt line connected to the P2WI peripheral.
- clocks : The gate clk connected to the P2WI peripheral.
- resets : The reset line connected to the P2WI peripheral.
Optional properties :
- clock-frequency : Desired P2WI bus clock frequency in Hz. If not set the
default frequency is 100kHz
A P2WI may contain one child node encoding a P2WI slave device.
Slave device properties:
Required properties:
- reg : the I2C slave address used during the initialization
process to switch from I2C to P2WI mode
Example:
p2wi@1f03400 {
compatible = "allwinner,sun6i-a31-p2wi";
reg = <0x01f03400 0x400>;
interrupts = <0 39 4>;
clocks = <&apb0_gates 3>;
clock-frequency = <6000000>;
resets = <&apb0_rst 3>;
axp221: pmic@68 {
compatible = "x-powers,axp221";
reg = <0x68>;
/* ... */
};
};

2
bindings/i3c/cdns,i3c-master.txt
View file

@ -38,6 +38,6 @@ Example:
nunchuk: nunchuk@52 {
compatible = "nintendo,nunchuk";
reg = <0x52 0x80000010 0>;
reg = <0x52 0x0 0x10>;
};
};

4
bindings/i3c/i3c.txt
View file

@ -39,7 +39,9 @@ valid here, but several new properties have been added.
New constraint on existing properties:
--------------------------------------
- reg: contains 3 cells
+ first cell : still encoding the I2C address
+ first cell : still encoding the I2C address. 10 bit addressing is not
supported. Devices with 10 bit address can't be properly passed through
DEFSLVS command.
+ second cell: shall be 0

39
bindings/iio/accel/adxl345.txt
View file

@ -1,39 +0,0 @@
Analog Devices ADXL345/ADXL375 3-Axis Digital Accelerometers
http://www.analog.com/en/products/mems/accelerometers/adxl345.html
http://www.analog.com/en/products/sensors-mems/accelerometers/adxl375.html
Required properties:
- compatible : should be one of
"adi,adxl345"
"adi,adxl375"
- reg : the I2C address or SPI chip select number of the sensor
Required properties for SPI bus usage:
- spi-max-frequency : set maximum clock frequency, must be 5000000
- spi-cpol and spi-cpha : must be defined for adxl345 to enable SPI mode 3
Optional properties:
- interrupts: interrupt mapping for IRQ as documented in
Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
Example for a I2C device node:
accelerometer@2a {
compatible = "adi,adxl345";
reg = <0x53>;
interrupt-parent = <&gpio1>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
};
Example for a SPI device node:
accelerometer@0 {
compatible = "adi,adxl345";
reg = <0>;
spi-max-frequency = <5000000>;
spi-cpol;
spi-cpha;
interrupt-parent = <&gpio1>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
};

33
bindings/iio/accel/adxl372.txt
View file

@ -1,33 +0,0 @@
Analog Devices ADXL372 3-Axis, +/-(200g) Digital Accelerometer
http://www.analog.com/media/en/technical-documentation/data-sheets/adxl372.pdf
Required properties:
- compatible : should be "adi,adxl372"
- reg: the I2C address or SPI chip select number for the device
Required properties for SPI bus usage:
- spi-max-frequency: Max SPI frequency to use
Optional properties:
- interrupts: interrupt mapping for IRQ as documented in
Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
Example for a I2C device node:
accelerometer@53 {
compatible = "adi,adxl372";
reg = <0x53>;
interrupt-parent = <&gpio>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};
Example for a SPI device node:
accelerometer@0 {
compatible = "adi,adxl372";
reg = <0>;
spi-max-frequency = <1000000>;
interrupt-parent = <&gpio>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};

75
bindings/iio/adc/adi,ad7124.txt
View file

@ -1,75 +0,0 @@
Analog Devices AD7124 ADC device driver
Required properties for the AD7124:
- compatible: Must be one of "adi,ad7124-4" or "adi,ad7124-8"
- reg: SPI chip select number for the device
- spi-max-frequency: Max SPI frequency to use
see: Documentation/devicetree/bindings/spi/spi-bus.txt
- clocks: phandle to the master clock (mclk)
see: Documentation/devicetree/bindings/clock/clock-bindings.txt
- clock-names: Must be "mclk".
- interrupts: IRQ line for the ADC
see: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
Required properties:
* #address-cells: Must be 1.
* #size-cells: Must be 0.
Subnode(s) represent the external channels which are connected to the ADC.
Each subnode represents one channel and has the following properties:
Required properties:
* reg: The channel number. It can have up to 4 channels on ad7124-4
and 8 channels on ad7124-8, numbered from 0 to 15.
* diff-channels: see: Documentation/devicetree/bindings/iio/adc/adc.txt
Optional properties:
* bipolar: see: Documentation/devicetree/bindings/iio/adc/adc.txt
* adi,reference-select: Select the reference source to use when
converting on the the specific channel. Valid values are:
0: REFIN1(+)/REFIN1(−).
1: REFIN2(+)/REFIN2(−).
3: AVDD
If this field is left empty, internal reference is selected.
Optional properties:
- refin1-supply: refin1 supply can be used as reference for conversion.
- refin2-supply: refin2 supply can be used as reference for conversion.
- avdd-supply: avdd supply can be used as reference for conversion.
Example:
adc@0 {
compatible = "adi,ad7124-4";
reg = <0>;
spi-max-frequency = <5000000>;
interrupts = <25 2>;
interrupt-parent = <&gpio>;
refin1-supply = <&adc_vref>;
clocks = <&ad7124_mclk>;
clock-names = "mclk";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
diff-channels = <0 1>;
adi,reference-select = <0>;
};
channel@1 {
reg = <1>;
bipolar;
diff-channels = <2 3>;
adi,reference-select = <0>;
};
channel@2 {
reg = <2>;
diff-channels = <4 5>;
};
channel@3 {
reg = <3>;
diff-channels = <6 7>;
};
};

160
bindings/iio/adc/adi,ad7124.yaml Normal file
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@ -0,0 +1,160 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 Analog Devices Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/iio/adc/adi,ad7124.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD7124 ADC device driver
maintainers:
- Stefan Popa <stefan.popa@analog.com>
description: |
Bindings for the Analog Devices AD7124 ADC device. Datasheet can be
found here:
https://www.analog.com/media/en/technical-documentation/data-sheets/AD7124-8.pdf
properties:
compatible:
enum:
- adi,ad7124-4
- adi,ad7124-8
reg:
description: SPI chip select number for the device
maxItems: 1
clocks:
maxItems: 1
description: phandle to the master clock (mclk)
clock-names:
items:
- const: mclk
interrupts:
description: IRQ line for the ADC
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
refin1-supply:
description: refin1 supply can be used as reference for conversion.
maxItems: 1
refin2-supply:
description: refin2 supply can be used as reference for conversion.
maxItems: 1
avdd-supply:
description: avdd supply can be used as reference for conversion.
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
patternProperties:
"^channel@([0-9]|1[0-5])$":
type: object
description: |
Represents the external channels which are connected to the ADC.
See Documentation/devicetree/bindings/iio/adc/adc.txt.
properties:
reg:
description: |
The channel number. It can have up to 8 channels on ad7124-4
and 16 channels on ad7124-8, numbered from 0 to 15.
items:
minimum: 0
maximum: 15
adi,reference-select:
description: |
Select the reference source to use when converting on
the specific channel. Valid values are:
0: REFIN1(+)/REFIN1(−).
1: REFIN2(+)/REFIN2(−).
3: AVDD
If this field is left empty, internal reference is selected.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [0, 1, 3]
diff-channels:
description: see Documentation/devicetree/bindings/iio/adc/adc.txt
items:
minimum: 0
maximum: 15
bipolar:
description: see Documentation/devicetree/bindings/iio/adc/adc.txt
type: boolean
adi,buffered-positive:
description: Enable buffered mode for positive input.
type: boolean
adi,buffered-negative:
description: Enable buffered mode for negative input.
type: boolean
required:
- reg
- diff-channels
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
adc@0 {
compatible = "adi,ad7124-4";
reg = <0>;
spi-max-frequency = <5000000>;
interrupts = <25 2>;
interrupt-parent = <&gpio>;
refin1-supply = <&adc_vref>;
clocks = <&ad7124_mclk>;
clock-names = "mclk";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
diff-channels = <0 1>;
adi,reference-select = <0>;
adi,buffered-positive;
};
channel@1 {
reg = <1>;
bipolar;
diff-channels = <2 3>;
adi,reference-select = <0>;
adi,buffered-positive;
adi,buffered-negative;
};
channel@2 {
reg = <2>;
diff-channels = <4 5>;
};
channel@3 {
reg = <3>;
diff-channels = <6 7>;
};
};
};

48
bindings/iio/adc/adi,ad7780.txt
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@ -1,48 +0,0 @@
* Analog Devices AD7170/AD7171/AD7780/AD7781
Data sheets:
- AD7170:
* https://www.analog.com/media/en/technical-documentation/data-sheets/AD7170.pdf
- AD7171:
* https://www.analog.com/media/en/technical-documentation/data-sheets/AD7171.pdf
- AD7780:
* https://www.analog.com/media/en/technical-documentation/data-sheets/ad7780.pdf
- AD7781:
* https://www.analog.com/media/en/technical-documentation/data-sheets/AD7781.pdf
Required properties:
- compatible: should be one of
* "adi,ad7170"
* "adi,ad7171"
* "adi,ad7780"
* "adi,ad7781"
- reg: spi chip select number for the device
- vref-supply: the regulator supply for the ADC reference voltage
Optional properties:
- powerdown-gpios: must be the device tree identifier of the PDRST pin. If
specified, it will be asserted during driver probe. As the
line is active high, it should be marked GPIO_ACTIVE_HIGH.
- adi,gain-gpios: must be the device tree identifier of the GAIN pin. Only for
the ad778x chips. If specified, it will be asserted during
driver probe. As the line is active low, it should be marked
GPIO_ACTIVE_LOW.
- adi,filter-gpios: must be the device tree identifier of the FILTER pin. Only
for the ad778x chips. If specified, it will be asserted
during driver probe. As the line is active low, it should be
marked GPIO_ACTIVE_LOW.
Example:
adc@0 {
compatible = "adi,ad7780";
reg = <0>;
vref-supply = <&vdd_supply>
powerdown-gpios = <&gpio 12 GPIO_ACTIVE_HIGH>;
adi,gain-gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
adi,filter-gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
};

2
bindings/iio/adc/mt6577_auxadc.txt
View file

@ -13,8 +13,10 @@ Required properties:
- compatible: Should be one of:
- "mediatek,mt2701-auxadc": For MT2701 family of SoCs
- "mediatek,mt2712-auxadc": For MT2712 family of SoCs
- "mediatek,mt6765-auxadc": For MT6765 family of SoCs
- "mediatek,mt7622-auxadc": For MT7622 family of SoCs
- "mediatek,mt8173-auxadc": For MT8173 family of SoCs
- "mediatek,mt8183-auxadc", "mediatek,mt8173-auxadc": For MT8183 family of SoCs
- reg: Address range of the AUXADC unit.
- clocks: Should contain a clock specifier for each entry in clock-names
- clock-names: Should contain "main".

1
bindings/iio/adc/st,stm32-adc.txt
View file

@ -38,6 +38,7 @@ Required properties:
It's required on stm32h7.
- clock-names: Must be "adc" and/or "bus" depending on part used.
- interrupt-controller: Identifies the controller node as interrupt-parent
- vdda-supply: Phandle to the vdda input analog voltage.
- vref-supply: Phandle to the vref input analog reference voltage.
- #interrupt-cells = <1>;
- #address-cells = <1>;

12
bindings/iio/chemical/sensirion,sps30.txt
View file

@ -1,12 +0,0 @@
* Sensirion SPS30 particulate matter sensor
Required properties:
- compatible: must be "sensirion,sps30"
- reg: the I2C address of the sensor
Example:
sps30@69 {
compatible = "sensirion,sps30";
reg = <0x69>;
};

27
bindings/iio/light/isl29018.txt
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@ -1,27 +0,0 @@
* ISL 29018/29023/29035 I2C ALS, Proximity, and Infrared sensor
Required properties:
- compatible: Should be one of
"isil,isl29018"
"isil,isl29023"
"isil,isl29035"
- reg: the I2C address of the device
Optional properties:
- interrupts: the sole interrupt generated by the device
Refer to interrupt-controller/interrupts.txt for generic interrupt client
node bindings.
- vcc-supply: phandle to the regulator that provides power to the sensor.
Example:
isl29018@44 {
compatible = "isil,isl29018";
reg = <0x44>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
};

56
bindings/iio/light/isl29018.yaml Normal file
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@ -0,0 +1,56 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/light/isl29018.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: |
Intersil 29018/29023/29035 Ambient Light, Infrared Light, and Proximity Sensor
maintainers:
- Brian Masney <masneyb@onstation.org>
description: |
Ambient and infrared light sensing with proximity detection over an i2c
interface.
https://www.renesas.com/us/en/www/doc/datasheet/isl29018.pdf
https://www.renesas.com/us/en/www/doc/datasheet/isl29023.pdf
https://www.renesas.com/us/en/www/doc/datasheet/isl29035.pdf
properties:
compatible:
enum:
- isil,isl29018
- isil,isl29023
- isil,isl29035
reg:
maxItems: 1
interrupts:
maxItems: 1
vcc-supply:
description: Regulator that provides power to the sensor
required:
- compatible
- reg
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
sensor@44 {
compatible = "isil,isl29018";
reg = <0x44>;
interrupts-extended = <&msmgpio 61 IRQ_TYPE_LEVEL_HIGH>;
};
};
...

25
bindings/iio/light/tsl2583.txt
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@ -1,25 +0,0 @@
* TAOS TSL 2580/2581/2583 ALS sensor
Required properties:
- compatible: Should be one of
"amstaos,tsl2580"
"amstaos,tsl2581"
"amstaos,tsl2583"
- reg: the I2C address of the device
Optional properties:
- interrupts: the sole interrupt generated by the device
Refer to interrupt-controller/interrupts.txt for generic interrupt client
node bindings.
- vcc-supply: phandle to the regulator that provides power to the sensor.
Example:
tsl2581@29 {
compatible = "amstaos,tsl2581";
reg = <0x29>;
};

46
bindings/iio/light/tsl2583.yaml Normal file
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@ -0,0 +1,46 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/light/tsl2583.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: AMS/TAOS Ambient Light Sensor (ALS)
maintainers:
- Brian Masney <masneyb@onstation.org>
description: |
Ambient light sensing with an i2c interface.
properties:
compatible:
enum:
- amstaos,tsl2580
- amstaos,tsl2581
- amstaos,tsl2583
reg:
maxItems: 1
interrupts:
maxItems: 1
vcc-supply:
description: Regulator that provides power to the sensor
required:
- compatible
- reg
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
light-sensor@29 {
compatible = "amstaos,tsl2581";
reg = <0x29>;
};
};
...

42
bindings/iio/light/tsl2772.txt
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@ -1,42 +0,0 @@
* AMS/TAOS ALS and proximity sensor
Required properties:
- compatible: Should be one of
"amstaos,tsl2571"
"amstaos,tsl2671"
"amstaos,tmd2671"
"amstaos,tsl2771"
"amstaos,tmd2771"
"amstaos,tsl2572"
"amstaos,tsl2672"
"amstaos,tmd2672"
"amstaos,tsl2772"
"amstaos,tmd2772"
"avago,apds9930"
- reg: the I2C address of the device
Optional properties:
- amstaos,proximity-diodes - proximity diodes to enable. <0>, <1>, or <0 1>
are the only valid values.
- led-max-microamp - current for the proximity LED. Must be 100000, 50000,
25000, or 13000.
- vdd-supply: phandle to the regulator that provides power to the sensor.
- vddio-supply: phandle to the regulator that provides power to the bus.
- interrupts: the sole interrupt generated by the device
Refer to interrupt-controller/interrupts.txt for generic interrupt client
node bindings.
Example:
tsl2772@39 {
compatible = "amstaos,tsl2772";
reg = <0x39>;
interrupts-extended = <&msmgpio 61 IRQ_TYPE_EDGE_FALLING>;
vdd-supply = <&pm8941_l17>;
vddio-supply = <&pm8941_lvs1>;
amstaos,proximity-diodes = <0>;
led-max-microamp = <100000>;
};

83
bindings/iio/light/tsl2772.yaml Normal file
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@ -0,0 +1,83 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/light/tsl2772.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: AMS/TAOS Ambient Light Sensor (ALS) and Proximity Detector
maintainers:
- Brian Masney <masneyb@onstation.org>
description: |
Ambient light sensing and proximity detection with an i2c interface.
https://ams.com/documents/20143/36005/TSL2772_DS000181_2-00.pdf
properties:
compatible:
enum:
- amstaos,tsl2571
- amstaos,tsl2671
- amstaos,tmd2671
- amstaos,tsl2771
- amstaos,tmd2771
- amstaos,tsl2572
- amstaos,tsl2672
- amstaos,tmd2672
- amstaos,tsl2772
- amstaos,tmd2772
- avago,apds9930
reg:
maxItems: 1
amstaos,proximity-diodes:
description: Proximity diodes to enable
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- minItems: 1
maxItems: 2
items:
minimum: 0
maximum: 1
interrupts:
maxItems: 1
led-max-microamp:
description: Current for the proximity LED
enum:
- 13000
- 25000
- 50000
- 100000
vdd-supply:
description: Regulator that provides power to the sensor
vddio-supply:
description: Regulator that provides power to the bus
required:
- compatible
- reg
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
sensor@39 {
compatible = "amstaos,tsl2772";
reg = <0x39>;
interrupts-extended = <&msmgpio 61 IRQ_TYPE_EDGE_FALLING>;
vdd-supply = <&pm8941_l17>;
vddio-supply = <&pm8941_lvs1>;
amstaos,proximity-diodes = <0>;
led-max-microamp = <100000>;
};
};
...

11
bindings/input/elan_i2c.txt
View file

@ -13,9 +13,20 @@ Optional properties:
pinctrl binding [1]).
- vcc-supply: a phandle for the regulator supplying 3.3V power.
- elan,trackpoint: touchpad can support a trackpoint (boolean)
- elan,clickpad: touchpad is a clickpad (the entire surface is a button)
- elan,middle-button: touchpad has a physical middle button
- elan,x_traces: number of antennas on the x axis
- elan,y_traces: number of antennas on the y axis
- some generic touchscreen properties [2]:
* touchscreen-size-x
* touchscreen-size-y
* touchscreen-x-mm
* touchscreen-y-mm
[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
[1]: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
[2]: Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt
Example:
&i2c1 {

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