From 43ea79256774eafc441aeafe3e59da8cdd0f891f Mon Sep 17 00:00:00 2001
From: Venkata Prahlad Valluru <vvalluru@qti.qualcomm.com>
Date: Sat, 28 Aug 2021 01:13:18 +0530
Subject: [PATCH] ARM: dts: msm: update max clk rate for display clocks

Update max clk rates for mdp clks.

Change-Id: I1732f73d1646d8aa08ffbaebfd6afacda07baaaf
---
 display/monaco-sde.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/display/monaco-sde.dtsi b/display/monaco-sde.dtsi
index 1518a5165ba5..aee56512a059 100644
--- a/display/monaco-sde.dtsi
+++ b/display/monaco-sde.dtsi
@@ -40,8 +40,8 @@
 		clock-names = "gcc_bus", "throttle_clk",
 				"iface_clk", "core_clk", "vsync_clk",
 				"lut_clk";
-		clock-rate = <0 0 0 0 0 256000000 19200000 192000000>;
-		clock-max-rate = <0 0 0 0 0 384000000 19200000 384000000>;
+		clock-rate = <0 0 0 300000000 19200000 192000000>;
+		clock-max-rate = <0 0 0 400000000 19200000 400000000>;
 
 		sde-vdd-supply = <&mdss_core_gdsc>;