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guam: input add touch chipone fw

Browse source 
input add touch chipone
fw
NO_PROP_NEEDED: only for guam/guamp

Change-Id: I8f31a802f0cc1b83c8afc30f7709d194c1d120c2
Signed-off-by: dengwei1 <dengwei1@motorola.com>
Reviewed-on: https://gerrit.mot.com/1530903
SME-Granted: SME Approvals Granted
SLTApproved: Slta Waiver
Tested-by: Jira Key
Reviewed-by: Xiangpo Zhao <zhaoxp3@motorola.com>
Submit-Approved: Jira Key
This commit is contained in:
dengwei1 2020-04-09 09:39:48 +08:00 • committed by Wei Deng
commit 44eaba9e38
22 changed files with 11772 additions and 12336 deletions
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1
drivers/input/touchscreen/chipone_tddi_mmi/Kbuild
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@ -14,3 +14,4 @@ chipone_tddi_mmi-objs += cts_firmware.o
chipone_tddi_mmi-objs += cts_tool.o
chipone_tddi_mmi-objs += cts_sysfs.o
chipone_tddi_mmi-objs += cts_test.o
chipone_tddi_mmi-objs += cts_charger_detect.o

3858
drivers/input/touchscreen/chipone_tddi_mmi/cts_builtin_firmware.h Executable file → Normal file
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1047
drivers/input/touchscreen/chipone_tddi_mmi/cts_charger_detect.c Normal file
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40
drivers/input/touchscreen/chipone_tddi_mmi/cts_charger_detect.h Normal file
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@ -0,0 +1,40 @@
#ifndef CTS_CHARGER_DETECT_H
#define CTS_CHARGER_DETECT_H
#include "cts_config.h"
struct chipone_ts_data;
#ifdef CONFIG_CTS_CHARGER_DETECT
extern int cts_charger_detect_init(struct chipone_ts_data *cts_data);
extern int cts_charger_detect_deinit(struct chipone_ts_data *cts_data);
extern int cts_start_charger_detect(struct chipone_ts_data *cts_data);
extern int cts_stop_charger_detect(struct chipone_ts_data *cts_data);
extern int cts_is_charger_attached(struct chipone_ts_data *cts_data,
bool *attached);
#else /* CONFIG_CTS_CHARGER_DETECT */
static inline int cts_charger_detect_init(struct chipone_ts_data *cts_data)
{
return -ENOTSUPP;
}
static inline int cts_charger_detect_deinit(struct chipone_ts_data *cts_data)
{
return -ENOTSUPP;
}
static inline int cts_start_charger_detect(struct chipone_ts_data *cts_data)
{
return -ENODEV;
}
static inline int cts_stop_charger_detect(struct chipone_ts_data *cts_data)
{
return -ENODEV;
}
static inline int cts_is_charger_attached(struct chipone_ts_data *cts_data,
bool *attached)
{
return -ENODEV;
}
#endif /*CONFIG_CTS_CHARGER_DETECT */
#endif /* CTS_CHARGER_DETECT_H */

85
drivers/input/touchscreen/chipone_tddi_mmi/cts_config.h Executable file → Normal file
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@ -4,9 +4,9 @@
/** Driver version */
#define CFG_CTS_DRIVER_MAJOR_VERSION 1
#define CFG_CTS_DRIVER_MINOR_VERSION 2
#define CFG_CTS_DRIVER_PATCH_VERSION 5
#define CFG_CTS_DRIVER_PATCH_VERSION 7
#define CFG_CTS_DRIVER_VERSION "v1.2.5"
#define CFG_CTS_DRIVER_VERSION "v1.2.7"
/** Whether reset pin is used */
#define CFG_CTS_HAS_RESET_PIN
@ -18,44 +18,54 @@
#define CFG_CTS_HAS_RESET_PIN
#endif
#define CFG_CTS_SPI_SPEED_KHZ 4000
#define CFG_CTS_SPI_SPEED_KHZ 6000
#endif
//#define CFG_CTS_FORCE_UP
#define CFG_CTS_FORCE_UP
#define CONFIG_GENERIC_HARDIRQS
//#define CFG_CTS_FW_LOG_REDIRECT
/** Whether force download firmware to chip */
//#define CFG_CTS_FIRMWARE_FORCE_UPDATE
/** Use build in firmware or firmware file in fs*/
#define CFG_CTS_DRIVER_BUILTIN_FIRMWARE
#define CFG_CTS_KERNEL_BUILTIN_FIRMWARE
//#define CFG_CTS_DRIVER_BUILTIN_FIRMWARE
#define CFG_CTS_FIRMWARE_IN_FS
#ifdef CFG_CTS_FIRMWARE_IN_FS
#define CFG_CTS_FIRMWARE_FILENAME "ICNL9911.bin"
#define CFG_CTS_FIRMWARE_FILEPATH "/vendor/firmware/ICNL9911.bin"
//#define CFG_CTS_FW_UPDATE_SYS // Add FW custom process.
//#define CFG_CTS_FW_UPDATE_FILE_LOAD // Load config fw bin as default.
#ifdef CFG_CTS_FW_UPDATE_FILE_LOAD
#define CFG_CTS_FW_FILE_NAME_MAX_LEN 128
#define CFG_CTS_FW_FILE_PATH "/vendor/firmware/"
#define CFG_CTS_FW_FILE_NAME_VENDOR "chipone"
#endif /*CFG_CTS_FW_UPDATE_FILE_LOAD*/
#define CFG_CTS_FIRMWARE_FILENAME "ICNL9911.bin"
#define CFG_CTS_FIRMWARE_FILEPATH "/vendor/firmware/ICNL9911.bin"
#endif /* CFG_CTS_FIRMWARE_IN_FS */
/* IC type support */
#define CFG_CTS_CHIP_NAME "ICNL9911S"
#ifdef CONFIG_PROC_FS
/* Proc FS for backward compatibility for APK tool com.ICN85xx */
#define CONFIG_CTS_LEGACY_TOOL
#define CONFIG_CTS_LEGACY_TOOL
#endif /* CONFIG_PROC_FS */
#ifdef CONFIG_SYSFS
/* Sys FS for gesture report, debug feature etc. */
// #define CONFIG_CTS_SYSFS
#define CONFIG_CTS_SYSFS
#endif /* CONFIG_SYSFS */
#define CFG_CTS_MAX_TOUCH_NUM (5)
#define CFG_CTS_MAX_TOUCH_NUM (10) // 5
/* Virtual key support */
//#define CONFIG_CTS_VIRTUALKEY
#ifdef CONFIG_CTS_VIRTUALKEY
#define CFG_CTS_MAX_VKEY_NUM (4)
#define CFG_CTS_NUM_VKEY (3)
#define CFG_CTS_VKEY_KEYCODES {KEY_BACK, KEY_HOME, KEY_MENU}
#define CFG_CTS_MAX_VKEY_NUM (4)
#define CFG_CTS_NUM_VKEY (3)
#define CFG_CTS_VKEY_KEYCODES {KEY_BACK, KEY_HOME, KEY_MENU}
#endif /* CONFIG_CTS_VIRTUALKEY */
/* Gesture wakeup */
@ -75,42 +85,42 @@
#define GESTURE_LEFT 0x23
#define GESTURE_RIGHT 0x24
#define CFG_CTS_NUM_GESTURE (13u)
#define CFG_CTS_GESTURE_REPORT_KEY
#define CFG_CTS_GESTURE_KEYMAP \
{{GESTURE_C, KEY_C,}, \
{GESTURE_W, KEY_W,}, \
{GESTURE_V, KEY_V,}, \
{GESTURE_D_TAP, KEY_F1,}, \
{GESTURE_Z, KEY_Z,}, \
{GESTURE_M, KEY_M,}, \
{GESTURE_O, KEY_O,}, \
{GESTURE_E, KEY_E,}, \
{GESTURE_S, KEY_S,}, \
{GESTURE_UP, KEY_UP,}, \
{GESTURE_DOWN, KEY_DOWN,}, \
{GESTURE_LEFT, KEY_LEFT,}, \
{GESTURE_RIGHT, KEY_RIGHT,}, \
}
#define CFG_CTS_GESTURE_REPORT_TRACE 0
#define CFG_CTS_NUM_GESTURE (13u)
#define CFG_CTS_GESTURE_REPORT_KEY
#define CFG_CTS_GESTURE_KEYMAP \
{{GESTURE_C, KEY_C,}, \
{GESTURE_W, KEY_W,}, \
{GESTURE_V, KEY_V,}, \
{GESTURE_D_TAP, KEY_F1,}, \
{GESTURE_Z, KEY_Z,}, \
{GESTURE_M, KEY_M,}, \
{GESTURE_O, KEY_O,}, \
{GESTURE_E, KEY_E,}, \
{GESTURE_S, KEY_S,}, \
{GESTURE_UP, KEY_UP,}, \
{GESTURE_DOWN, KEY_DOWN,}, \
{GESTURE_LEFT, KEY_LEFT,}, \
{GESTURE_RIGHT, KEY_RIGHT,}, \
}
#define CFG_CTS_GESTURE_REPORT_TRACE 0
#endif /* CFG_CTS_GESTURE */
//#define CONFIG_CTS_GLOVE
//#define CONFIG_CTS_CHARGER_DETECT
#define CONFIG_CTS_CHARGER_DETECT
/* ESD protection */
//#define CONFIG_CTS_ESD_PROTECTION
#ifdef CONFIG_CTS_ESD_PROTECTION
#define CFG_CTS_ESD_PROTECTION_CHECK_PERIOD (2 * HZ)
#define CFG_CTS_ESD_FAILED_CONFIRM_CNT 3
#define CFG_CTS_ESD_PROTECTION_CHECK_PERIOD (2 * HZ)
#define CFG_CTS_ESD_FAILED_CONFIRM_CNT 3
#endif /* CONFIG_CTS_ESD_PROTECTION */
/* Use slot protocol (protocol B), comment it if use protocol A. */
#define CONFIG_CTS_SLOTPROTOCOL
#ifdef CONFIG_CTS_LEGACY_TOOL
#define CFG_CTS_TOOL_PROC_FILENAME "icn85xx_tool"
#define CFG_CTS_TOOL_PROC_FILENAME "icn85xx_tool"
#endif /* CONFIG_CTS_LEGACY_TOOL */
#define CFG_CTS_UPDATE_CRCCHECK
@ -121,4 +131,3 @@
#include "cts_plat_qcom_config.h"
#endif /* CTS_CONFIG_H */

3467
drivers/input/touchscreen/chipone_tddi_mmi/cts_core.c Executable file → Normal file
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584
drivers/input/touchscreen/chipone_tddi_mmi/cts_core.h Executable file → Normal file
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@ -3,21 +3,20 @@
#include "cts_config.h"
enum cts_dev_hw_reg {
CTS_DEV_HW_REG_HARDWARE_ID = 0x30000u,
CTS_DEV_HW_REG_CLOCK_GATING = 0x30004u,
CTS_DEV_HW_REG_RESET_CONFIG = 0x30008u,
CTS_DEV_HW_REG_BOOT_MODE = 0x30010u,
CTS_DEV_HW_REG_HARDWARE_ID = 0x30000u,
CTS_DEV_HW_REG_CLOCK_GATING = 0x30004u,
CTS_DEV_HW_REG_RESET_CONFIG = 0x30008u,
CTS_DEV_HW_REG_BOOT_MODE = 0x30010u,
CTS_DEV_HW_REG_CURRENT_MODE = 0x30011u,
};
enum cts_dev_boot_mode {
CTS_DEV_BOOT_MODE_FLASH = 1,
CTS_DEV_BOOT_MODE_I2C_PROGRAM = 2,
CTS_DEV_BOOT_MODE_SRAM = 3,
CTS_DEV_BOOT_MODE_SPI_PROGRAM = 5,
CTS_DEV_BOOT_MODE_MASK = 7,
CTS_DEV_BOOT_MODE_FLASH = 1,
CTS_DEV_BOOT_MODE_I2C_PROGRAM = 2,
CTS_DEV_BOOT_MODE_SRAM = 3,
CTS_DEV_BOOT_MODE_SPI_PROGRAM = 5,
CTS_DEV_BOOT_MODE_MASK = 7,
};
/** I2C addresses(7bits), transfer size and bitrate */
@ -30,86 +29,88 @@ enum cts_dev_boot_mode {
/** Chipone firmware register addresses under normal mode */
enum cts_device_fw_reg {
CTS_DEVICE_FW_REG_WORK_MODE = 0x0000,
CTS_DEVICE_FW_REG_DATA_READY = 0x0002,
CTS_DEVICE_FW_REG_CMD = 0x0004,
CTS_DEVICE_FW_REG_CHIP_TYPE = 0x000A,
CTS_DEVICE_FW_REG_VERSION = 0x000C,
CTS_DEVICE_FW_REG_FW_LIB_MAIN_VERSION = 0x09,
CTS_DEVICE_FW_REG_DDI_VERSION = 0x0010,
CTS_DEVICE_FW_REG_FW_LIB_SUB_VERSION = 0x47,
CTS_DEVICE_FW_REG_WORK_MODE = 0x0000,
CTS_DEVICE_FW_REG_DATA_READY = 0x0002,
CTS_DEVICE_FW_REG_CMD = 0x0004,
CTS_DEVICE_FW_REG_CHIP_TYPE = 0x000A,
CTS_DEVICE_FW_REG_VERSION = 0x000C,
CTS_DEVICE_FW_REG_FW_LIB_MAIN_VERSION = 0x09,
CTS_DEVICE_FW_REG_DDI_VERSION = 0x0010,
CTS_DEVICE_FW_REG_GET_WORK_MODE = 0x003F,
CTS_DEVICE_FW_REG_FW_LIB_SUB_VERSION = 0x0047,
CTS_DEVICE_FW_REG_TOUCH_INFO = 0x1000,
CTS_DEVICE_FW_REG_RAW_DATA = 0x2000,
CTS_DEVICE_FW_REG_DIFF_DATA = 0x3000,
CTS_DEVICE_FW_REG_GESTURE_INFO = 0x7000,
CTS_DEVICE_FW_REG_TOUCH_INFO = 0x1000,
CTS_DEVICE_FW_REG_RAW_DATA = 0x2000,
CTS_DEVICE_FW_REG_DIFF_DATA = 0x3000,
CTS_DEVICE_FW_REG_GESTURE_INFO = 0x7000,
CTS_DEVICE_FW_REG_PANEL_PARAM = 0x8000,
CTS_DEVICE_FW_REG_X_RESOLUTION = 0x8090,
CTS_DEVICE_FW_REG_Y_RESOLUTION = 0x8092,
CTS_DEVICE_FW_REG_NUM_TX = 0x8007,
CTS_DEVICE_FW_REG_NUM_RX = 0x8008,
CTS_DEVICE_FW_REG_PANEL_PARAM = 0x8000,
CTS_DEVICE_FW_REG_X_RESOLUTION = 0x8090,
CTS_DEVICE_FW_REG_Y_RESOLUTION = 0x8092,
CTS_DEVICE_FW_REG_NUM_TX = 0x8007,
CTS_DEVICE_FW_REG_NUM_RX = 0x8008,
CTS_DEVICE_FW_REG_COMPENSATE_CAP = 0xA000,
CTS_DEVICE_FW_REG_DEBUG_INTF = 0xF000,
CTS_DEVICE_FW_REG_COMPENSATE_CAP = 0xA000,
CTS_DEVICE_FW_REG_DEBUG_INTF = 0xF000,
};
/** Hardware IDs, read from hardware id register */
enum cts_dev_hwid {
CTS_DEV_HWID_ICNL9911 = 0x990100u,
CTS_DEV_HWID_ICNL9911S = 0x990110u,
CTS_DEV_HWID_ICNL9911 = 0x990100u,
CTS_DEV_HWID_ICNL9911S = 0x990110u,
CTS_DEV_HWID_ANY = 0,
CTS_DEV_HWID_INVALID = 0xFFFFFFFFu,
CTS_DEV_HWID_ANY = 0,
CTS_DEV_HWID_INVALID = 0xFFFFFFFFu,
};
/* Firmware IDs, read from firmware register @ref CTS_DEV_FW_REG_CHIP_TYPE
under normal mode */
enum cts_dev_fwid {
CTS_DEV_FWID_ICNL9911 = 0x9911u,
CTS_DEV_FWID_ICNL9911S = 0x9964u,
CTS_DEV_FWID_ICNL9911 = 0x9911u,
CTS_DEV_FWID_ICNL9911S = 0x9964u,
CTS_DEV_FWID_ANY = 0u,
CTS_DEV_FWID_INVALID = 0xFFFFu
CTS_DEV_FWID_ANY = 0u,
CTS_DEV_FWID_INVALID = 0xFFFFu
};
/** Commands written to firmware register @ref CTS_DEVICE_FW_REG_CMD under normal mode */
enum cts_firmware_cmd {
CTS_CMD_RESET = 1,
CTS_CMD_SUSPEND = 2,
CTS_CMD_ENTER_WRITE_PARA_TO_FLASH_MODE = 3,
CTS_CMD_WRITE_PARA_TO_FLASH = 4,
CTS_CMD_WRTITE_INT_HIGH = 5,
CTS_CMD_WRTITE_INT_LOW = 6,
CTS_CMD_RELASE_INT_TEST = 7,
CTS_CMD_RECOVERY_TX_VOL = 0x10,
CTS_CMD_DEC_TX_VOL_1 = 0x11,
CTS_CMD_DEC_TX_VOL_2 = 0x12,
CTS_CMD_DEC_TX_VOL_3 = 0x13,
CTS_CMD_DEC_TX_VOL_4 = 0x14,
CTS_CMD_DEC_TX_VOL_5 = 0x15,
CTS_CMD_DEC_TX_VOL_6 = 0x16,
CTS_CMD_ENABLE_READ_RAWDATA = 0x20,
CTS_CMD_DISABLE_READ_RAWDATA = 0x21,
CTS_CMD_SUSPEND_WITH_GESTURE = 0x40,
CTS_CMD_QUIT_GESTURE_MONITOR = 0x41,
CTS_CMD_CHARGER_PLUG_IN = 0x55,
CTS_CMD_CHARGER_PLUG_OUT = 0x66,
CTS_CMD_ENABLE_FW_LOG_REDIRECT = 0x86,
CTS_CMD_DISABLE_FW_LOG_REDIRECT = 0x87,
CTS_CMD_ENABLE_READ_CNEG = 0x88,
CTS_CMD_DISABLE_READ_CNEG = 0x89,
CTS_CMD_FW_LOG_SHOW_FINISH = 0xE0,
CTS_CMD_RESET = 1,
CTS_CMD_SUSPEND = 2,
CTS_CMD_ENTER_WRITE_PARA_TO_FLASH_MODE = 3,
CTS_CMD_WRITE_PARA_TO_FLASH = 4,
CTS_CMD_WRTITE_INT_HIGH = 5,
CTS_CMD_WRTITE_INT_LOW = 6,
CTS_CMD_RELASE_INT_TEST = 7,
CTS_CMD_RECOVERY_TX_VOL = 0x10,
CTS_CMD_DEC_TX_VOL_1 = 0x11,
CTS_CMD_DEC_TX_VOL_2 = 0x12,
CTS_CMD_DEC_TX_VOL_3 = 0x13,
CTS_CMD_DEC_TX_VOL_4 = 0x14,
CTS_CMD_DEC_TX_VOL_5 = 0x15,
CTS_CMD_DEC_TX_VOL_6 = 0x16,
CTS_CMD_ENABLE_READ_RAWDATA = 0x20,
CTS_CMD_DISABLE_READ_RAWDATA = 0x21,
CTS_CMD_SUSPEND_WITH_GESTURE = 0x40,
CTS_CMD_QUIT_GESTURE_MONITOR = 0x41,
CTS_CMD_CHARGER_PLUG_IN = 0x55,
CTS_CMD_CHARGER_PLUG_OUT = 0x66,
CTS_CMD_ENABLE_FW_LOG_REDIRECT = 0x86,
CTS_CMD_DISABLE_FW_LOG_REDIRECT = 0x87,
CTS_CMD_ENABLE_READ_CNEG = 0x88,
CTS_CMD_DISABLE_READ_CNEG = 0x89,
CTS_CMD_FW_LOG_SHOW_FINISH = 0xE0,
};
#pragma pack(1)
/** Touch message read back from chip */
struct cts_device_touch_msg {
u8 id;
__le16 x;
__le16 y;
u8 pressure;
u8 event;
u8 id;
__le16 x;
__le16 y;
u8 pressure;
u8 event;
#define CTS_DEVICE_TOUCH_EVENT_NONE (0)
#define CTS_DEVICE_TOUCH_EVENT_DOWN (1)
@ -121,23 +122,23 @@ struct cts_device_touch_msg {
/** Touch information read back from chip */
struct cts_device_touch_info {
u8 vkey_state;
u8 num_msg;
u8 vkey_state;
u8 num_msg;
struct cts_device_touch_msg msgs[CFG_CTS_MAX_TOUCH_NUM];
struct cts_device_touch_msg msgs[CFG_CTS_MAX_TOUCH_NUM];
};
/** Gesture trace point read back from chip */
struct cts_device_gesture_point {
__le16 x;
__le16 y;
u8 pressure;
u8 event;
__le16 x;
__le16 y;
u8 pressure;
u8 event;
};
/** Gesture information read back from chip */
struct cts_device_gesture_info {
u8 gesture_id;
u8 gesture_id;
#define CTS_GESTURE_UP (0x11)
#define CTS_GESTURE_C (0x12)
#define CTS_GESTURE_O (0x13)
@ -154,48 +155,48 @@ struct cts_device_gesture_info {
#define CTS_GESTURE_V (0x1E)
#define CTS_GESTURE_D_TAP (0x50)
u8 num_points;
u8 num_points;
#define CTS_CHIP_MAX_GESTURE_TRACE_POINT (64u)
struct cts_device_gesture_point points[CTS_CHIP_MAX_GESTURE_TRACE_POINT];
struct cts_device_gesture_point
points[CTS_CHIP_MAX_GESTURE_TRACE_POINT];
};
#pragma pack()
struct cts_device;
enum cts_crc_type {
CTS_CRC16 = 1,
CTS_CRC32 = 2,
CTS_CRC16 = 1,
CTS_CRC32 = 2,
};
/** Chip hardware data, will never change */
struct cts_device_hwdata {
const char *name;
u32 hwid;
u16 fwid;
u8 num_row;
u8 num_col;
u32 sram_size;
const char *name;
u32 hwid;
u16 fwid;
u8 num_row;
u8 num_col;
u32 sram_size;
/* Address width under program mode */
u8 program_addr_width;
/* Address width under program mode */
u8 program_addr_width;
const struct cts_sfctrl *sfctrl;
const struct cts_sfctrl *sfctrl;
};
/** Chip firmware data */
struct cts_device_fwdata {
u16 version;
u16 res_x;
u16 res_y;
u8 rows;
u8 cols;
u8 ddi_version;
u8 int_mode;
u8 esd_method;
u16 version;
u16 res_x;
u16 res_y;
u8 rows;
u8 cols;
u8 ddi_version;
u8 int_mode;
u8 esd_method;
u16 lib_version;
u16 int_keep_time;
u16 rawdata_target;
@ -203,307 +204,344 @@ struct cts_device_fwdata {
/** Chip runtime data */
struct cts_device_rtdata {
u8 slave_addr;
int addr_width;
bool program_mode;
bool has_flash;
u8 slave_addr;
int addr_width;
bool program_mode;
bool has_flash;
bool suspended;
bool updating;
bool testing;
bool suspended;
bool updating;
bool testing;
bool gesture_wakeup_enabled;
bool charger_exist;
bool fw_log_redirect_enabled;
bool glove_mode_enabled;
bool gesture_wakeup_enabled;
bool charger_exist;
bool fw_log_redirect_enabled;
bool glove_mode_enabled;
};
struct cts_device {
struct cts_platform_data *pdata;
const struct cts_device_hwdata *hwdata;
struct cts_device_fwdata fwdata;
struct cts_device_rtdata rtdata;
const struct cts_flash *flash;
bool enabled;
struct cts_platform_data *pdata;
const struct cts_device_hwdata *hwdata;
struct cts_device_fwdata fwdata;
struct cts_device_rtdata rtdata;
const struct cts_flash *flash;
bool enabled;
#ifdef CFG_CTS_FW_UPDATE_FILE_LOAD
char config_fw_name[CFG_CTS_FW_FILE_NAME_MAX_LEN + 1];
#endif /* CFG_CTS_FW_UPDATE_FILE_LOAD */
};
struct cts_platform_data;
struct chipone_ts_data {
#ifdef CONFIG_CTS_I2C_HOST
struct i2c_client *i2c_client;
struct i2c_client *i2c_client;
#else
struct spi_device *spi_client;
#endif /* CONFIG_CTS_I2C_HOST */
struct cts_device cts_dev;
struct cts_platform_data *pdata;
struct workqueue_struct *workqueue;
#endif /* CONFIG_CTS_I2C_HOST */
struct device *device;
struct cts_device cts_dev;
struct cts_platform_data *pdata;
struct workqueue_struct *workqueue;
struct delayed_work fw_upgrade_work;
struct work_struct ts_resume_work;
#ifdef CONFIG_CTS_CHARGER_DETECT
void *cd_data;
#endif /* CONFIG_CTS_CHARGER_DETECT */
#ifdef CONFIG_CTS_ESD_PROTECTION
struct workqueue_struct *esd_workqueue;
struct delayed_work esd_work;
bool esd_enabled;
int esd_check_fail_cnt;
#endif /* CONFIG_CTS_ESD_PROTECTION */
struct workqueue_struct *esd_workqueue;
struct delayed_work esd_work;
bool esd_enabled;
int esd_check_fail_cnt;
#endif /* CONFIG_CTS_ESD_PROTECTION */
#ifdef CONFIG_CTS_LEGACY_TOOL
struct proc_dir_entry *procfs_entry;
#endif /* CONFIG_CTS_LEGACY_TOOL */
struct proc_dir_entry *procfs_entry;
#endif /* CONFIG_CTS_LEGACY_TOOL */
bool force_reflash;
};
static inline u32 get_unaligned_le24(const void *p)
{
const u8 *puc = (const u8 *)p;
return (puc[0] | (puc[1] << 8) | (puc[2] << 16));
const u8 *puc = (const u8 *)p;
return (puc[0] | (puc[1] << 8) | (puc[2] << 16));
}
static inline u32 get_unaligned_be24(const void *p)
{
const u8 *puc = (const u8 *)p;
return (puc[2] | (puc[1] << 8) | (puc[0] << 16));
const u8 *puc = (const u8 *)p;
return (puc[2] | (puc[1] << 8) | (puc[0] << 16));
}
static inline void put_unaligned_be24(u32 v, void *p)
{
u8 *puc = (u8 *)p;
u8 *puc = (u8 *) p;
puc[0] = (v >> 16) & 0xFF;
puc[1] = (v >> 8 ) & 0xFF;
puc[2] = (v >> 0 ) & 0xFF;
puc[0] = (v >> 16) & 0xFF;
puc[1] = (v >> 8) & 0xFF;
puc[2] = (v >> 0) & 0xFF;
}
#define wrap(max,x) ((max) - 1 - (x))
#define wrap(max, x) ((max) - 1 - (x))
extern void cts_lock_device(const struct cts_device *cts_dev);
extern void cts_unlock_device(const struct cts_device *cts_dev);
extern int cts_sram_writeb_retry(const struct cts_device *cts_dev,
u32 addr, u8 b, int retry, int delay);
u32 addr, u8 b, int retry, int delay);
extern int cts_sram_writew_retry(const struct cts_device *cts_dev,
u32 addr, u16 w, int retry, int delay);
u32 addr, u16 w, int retry, int delay);
extern int cts_sram_writel_retry(const struct cts_device *cts_dev,
u32 addr, u32 l, int retry, int delay);
u32 addr, u32 l, int retry, int delay);
extern int cts_sram_writesb_retry(const struct cts_device *cts_dev,
u32 addr, const void *src, size_t len, int retry, int delay);
u32 addr, const void *src, size_t len,
int retry, int delay);
extern int cts_sram_writesb_check_crc_retry(const struct cts_device *cts_dev,
u32 addr, const void *src, size_t len, u32 crc, int retry);
u32 addr, const void *src,
size_t len, u32 crc, int retry);
extern int cts_sram_readb_retry(const struct cts_device *cts_dev,
u32 addr, u8 *b, int retry, int delay);
u32 addr, u8 *b, int retry, int delay);
extern int cts_sram_readw_retry(const struct cts_device *cts_dev,
u32 addr, u16 *w, int retry, int delay);
u32 addr, u16 *w, int retry, int delay);
extern int cts_sram_readl_retry(const struct cts_device *cts_dev,
u32 addr, u32 *l, int retry, int delay);
u32 addr, u32 *l, int retry, int delay);
extern int cts_sram_readsb_retry(const struct cts_device *cts_dev,
u32 addr, void *dst, size_t len, int retry, int delay);
u32 addr, void *dst, size_t len, int retry,
int delay);
extern int cts_fw_reg_writeb_retry(const struct cts_device *cts_dev,
u32 reg_addr, u8 b, int retry, int delay);
u32 reg_addr, u8 b, int retry, int delay);
extern int cts_fw_reg_writew_retry(const struct cts_device *cts_dev,
u32 reg_addr, u16 w, int retry, int delay);
u32 reg_addr, u16 w, int retry, int delay);
extern int cts_fw_reg_writel_retry(const struct cts_device *cts_dev,
u32 reg_addr, u32 l, int retry, int delay);
u32 reg_addr, u32 l, int retry, int delay);
extern int cts_fw_reg_writesb_retry(const struct cts_device *cts_dev,
u32 reg_addr, const void *src, size_t len, int retry, int delay);
u32 reg_addr, const void *src, size_t len,
int retry, int delay);
extern int cts_fw_reg_readb_retry(const struct cts_device *cts_dev,
u32 reg_addr, u8 *b, int retry, int delay);
u32 reg_addr, u8 *b, int retry, int delay);
extern int cts_fw_reg_readw_retry(const struct cts_device *cts_dev,
u32 reg_addr, u16 *w, int retry, int delay);
u32 reg_addr, u16 *w, int retry, int delay);
extern int cts_fw_reg_readl_retry(const struct cts_device *cts_dev,
u32 reg_addr, u32 *l, int retry, int delay);
u32 reg_addr, u32 *l, int retry, int delay);
extern int cts_fw_reg_readsb_retry(const struct cts_device *cts_dev,
u32 reg_addr, void *dst, size_t len, int retry, int delay);
u32 reg_addr, void *dst, size_t len,
int retry, int delay);
extern int cts_fw_reg_readsb_retry_delay_idle(const struct cts_device *cts_dev,
u32 reg_addr, void *dst, size_t len, int retry, int delay, int idle);
u32 reg_addr, void *dst,
size_t len, int retry, int delay,
int idle);
extern int cts_hw_reg_writeb_retry(const struct cts_device *cts_dev,
u32 reg_addr, u8 b, int retry, int delay);
u32 reg_addr, u8 b, int retry, int delay);
extern int cts_hw_reg_writew_retry(const struct cts_device *cts_dev,
u32 reg_addr, u16 w, int retry, int delay);
u32 reg_addr, u16 w, int retry, int delay);
extern int cts_hw_reg_writel_retry(const struct cts_device *cts_dev,
u32 reg_addr, u32 l, int retry, int delay);
u32 reg_addr, u32 l, int retry, int delay);
extern int cts_hw_reg_writesb_retry(const struct cts_device *cts_dev,
u32 reg_addr, const void *src, size_t len, int retry, int delay);
u32 reg_addr, const void *src, size_t len,
int retry, int delay);
extern int cts_hw_reg_readb_retry(const struct cts_device *cts_dev,
u32 reg_addr, u8 *b, int retry, int delay);
u32 reg_addr, u8 *b, int retry, int delay);
extern int cts_hw_reg_readw_retry(const struct cts_device *cts_dev,
u32 reg_addr, u16 *w, int retry, int delay);
u32 reg_addr, u16 *w, int retry, int delay);
extern int cts_hw_reg_readl_retry(const struct cts_device *cts_dev,
u32 reg_addr, u32 *l, int retry, int delay);
u32 reg_addr, u32 *l, int retry, int delay);
extern int cts_hw_reg_readsb_retry(const struct cts_device *cts_dev,
u32 reg_addr, void *dst, size_t len, int retry, int delay);
u32 reg_addr, void *dst, size_t len,
int retry, int delay);
static inline int cts_fw_reg_writeb(const struct cts_device *cts_dev, u32 reg_addr, u8 b)
static inline int cts_fw_reg_writeb(const struct cts_device *cts_dev,
u32 reg_addr, u8 b)
{
return cts_fw_reg_writeb_retry(cts_dev, reg_addr, b, 1, 0);
return cts_fw_reg_writeb_retry(cts_dev, reg_addr, b, 1, 0);
}
static inline int cts_fw_reg_writew(const struct cts_device *cts_dev, u32 reg_addr, u16 w)
static inline int cts_fw_reg_writew(const struct cts_device *cts_dev,
u32 reg_addr, u16 w)
{
return cts_fw_reg_writew_retry(cts_dev, reg_addr, w, 1, 0);
return cts_fw_reg_writew_retry(cts_dev, reg_addr, w, 1, 0);
}
static inline int cts_fw_reg_writel(const struct cts_device *cts_dev, u32 reg_addr, u32 l)
static inline int cts_fw_reg_writel(const struct cts_device *cts_dev,
u32 reg_addr, u32 l)
{
return cts_fw_reg_writel_retry(cts_dev, reg_addr, l, 1, 0);
return cts_fw_reg_writel_retry(cts_dev, reg_addr, l, 1, 0);
}
static inline int cts_fw_reg_writesb(const struct cts_device *cts_dev, u32 reg_addr,
const void *src, size_t len)
static inline int cts_fw_reg_writesb(const struct cts_device *cts_dev,
u32 reg_addr, const void *src, size_t len)
{
return cts_fw_reg_writesb_retry(cts_dev, reg_addr, src, len, 1, 0);
return cts_fw_reg_writesb_retry(cts_dev, reg_addr, src, len, 1, 0);
}
static inline int cts_fw_reg_readb(const struct cts_device *cts_dev, u32 reg_addr, u8 *b)
static inline int cts_fw_reg_readb(const struct cts_device *cts_dev,
u32 reg_addr, u8 *b)
{
return cts_fw_reg_readb_retry(cts_dev, reg_addr, b, 1, 0);
return cts_fw_reg_readb_retry(cts_dev, reg_addr, b, 1, 0);
}
static inline int cts_fw_reg_readw(const struct cts_device *cts_dev, u32 reg_addr, u16 *w)
static inline int cts_fw_reg_readw(const struct cts_device *cts_dev,
u32 reg_addr, u16 *w)
{
return cts_fw_reg_readw_retry(cts_dev, reg_addr, w, 1, 0);
return cts_fw_reg_readw_retry(cts_dev, reg_addr, w, 1, 0);
}
static inline int cts_fw_reg_readl(const struct cts_device *cts_dev, u32 reg_addr, u32 *l)
static inline int cts_fw_reg_readl(const struct cts_device *cts_dev,
u32 reg_addr, u32 *l)
{
return cts_fw_reg_readl_retry(cts_dev, reg_addr, l, 1, 0);
return cts_fw_reg_readl_retry(cts_dev, reg_addr, l, 1, 0);
}
static inline int cts_fw_reg_readsb(const struct cts_device *cts_dev,
u32 reg_addr, void *dst, size_t len)
u32 reg_addr, void *dst, size_t len)
{
return cts_fw_reg_readsb_retry(cts_dev, reg_addr, dst, len, 1, 0);
return cts_fw_reg_readsb_retry(cts_dev, reg_addr, dst, len, 1, 0);
}
static inline int cts_fw_reg_readsb_delay_idle(const struct cts_device *cts_dev,
u32 reg_addr, void *dst, size_t len, int idle)
u32 reg_addr, void *dst,
size_t len, int idle)
{
return cts_fw_reg_readsb_retry_delay_idle(cts_dev, reg_addr, dst, len, 1, 0, idle);
return cts_fw_reg_readsb_retry_delay_idle(cts_dev, reg_addr, dst, len,
1, 0, idle);
}
static inline int cts_hw_reg_writeb(const struct cts_device *cts_dev, u32 reg_addr, u8 b)
static inline int cts_hw_reg_writeb_relaxed(const struct cts_device *cts_dev,
u32 reg_addr, u8 b)
{
return cts_hw_reg_writeb_retry(cts_dev, reg_addr, b, 1, 0);
return cts_hw_reg_writeb_retry(cts_dev, reg_addr, b, 1, 0);
}
static inline int cts_hw_reg_writew(const struct cts_device *cts_dev, u32 reg_addr, u16 w)
static inline int cts_hw_reg_writew_relaxed(const struct cts_device *cts_dev,
u32 reg_addr, u16 w)
{
return cts_hw_reg_writew_retry(cts_dev, reg_addr, w, 1, 0);
return cts_hw_reg_writew_retry(cts_dev, reg_addr, w, 1, 0);
}
static inline int cts_hw_reg_writel(const struct cts_device *cts_dev, u32 reg_addr, u32 l)
static inline int cts_hw_reg_writel_relaxed(const struct cts_device *cts_dev,
u32 reg_addr, u32 l)
{
return cts_hw_reg_writel_retry(cts_dev, reg_addr, l, 1, 0);
return cts_hw_reg_writel_retry(cts_dev, reg_addr, l, 1, 0);
}
static inline int cts_hw_reg_writesb(const struct cts_device *cts_dev, u32 reg_addr,
const void *src, size_t len)
static inline int cts_hw_reg_writesb(const struct cts_device *cts_dev,
u32 reg_addr, const void *src, size_t len)
{
return cts_hw_reg_writesb_retry(cts_dev, reg_addr, src, len, 1, 0);
return cts_hw_reg_writesb_retry(cts_dev, reg_addr, src, len, 1, 0);
}
static inline int cts_hw_reg_readb(const struct cts_device *cts_dev, u32 reg_addr, u8 *b)
static inline int cts_hw_reg_readb_relaxed(const struct cts_device *cts_dev,
u32 reg_addr, u8 *b)
{
return cts_hw_reg_readb_retry(cts_dev, reg_addr, b, 1, 0);
return cts_hw_reg_readb_retry(cts_dev, reg_addr, b, 1, 0);
}
static inline int cts_hw_reg_readw(const struct cts_device *cts_dev, u32 reg_addr, u16 *w)
static inline int cts_hw_reg_readw_relaxed(const struct cts_device *cts_dev,
u32 reg_addr, u16 *w)
{
return cts_hw_reg_readw_retry(cts_dev, reg_addr, w, 1, 0);
return cts_hw_reg_readw_retry(cts_dev, reg_addr, w, 1, 0);
}
static inline int cts_hw_reg_readl(const struct cts_device *cts_dev, u32 reg_addr, u32 *l)
static inline int cts_hw_reg_readl_relaxed(const struct cts_device *cts_dev,
u32 reg_addr, u32 *l)
{
return cts_hw_reg_readl_retry(cts_dev, reg_addr, l, 1, 0);
return cts_hw_reg_readl_retry(cts_dev, reg_addr, l, 1, 0);
}
static inline int cts_hw_reg_readsb(const struct cts_device *cts_dev,
u32 reg_addr, void *dst, size_t len)
u32 reg_addr, void *dst, size_t len)
{
return cts_hw_reg_readsb_retry(cts_dev, reg_addr, dst, len, 1, 0);
return cts_hw_reg_readsb_retry(cts_dev, reg_addr, dst, len, 1, 0);
}
static inline int cts_sram_writeb(const struct cts_device *cts_dev, u32 addr, u8 b)
static inline int cts_sram_writeb(const struct cts_device *cts_dev, u32 addr,
u8 b)
{
return cts_sram_writeb_retry(cts_dev, addr, b, 1, 0);
return cts_sram_writeb_retry(cts_dev, addr, b, 1, 0);
}
static inline int cts_sram_writew(const struct cts_device *cts_dev, u32 addr, u16 w)
static inline int cts_sram_writew(const struct cts_device *cts_dev, u32 addr,
u16 w)
{
return cts_sram_writew_retry(cts_dev, addr, w, 1, 0);
return cts_sram_writew_retry(cts_dev, addr, w, 1, 0);
}
static inline int cts_sram_writel(const struct cts_device *cts_dev, u32 addr, u32 l)
static inline int cts_sram_writel(const struct cts_device *cts_dev, u32 addr,
u32 l)
{
return cts_sram_writel_retry(cts_dev, addr, l, 1, 0);
return cts_sram_writel_retry(cts_dev, addr, l, 1, 0);
}
static inline int cts_sram_writesb(const struct cts_device *cts_dev, u32 addr,
const void *src, size_t len)
const void *src, size_t len)
{
return cts_sram_writesb_retry(cts_dev, addr, src, len, 1, 0);
return cts_sram_writesb_retry(cts_dev, addr, src, len, 1, 0);
}
static inline int cts_sram_readb(const struct cts_device *cts_dev, u32 addr, u8 *b)
static inline int cts_sram_readb(const struct cts_device *cts_dev, u32 addr,
u8 *b)
{
return cts_sram_readb_retry(cts_dev, addr, b, 1, 0);
return cts_sram_readb_retry(cts_dev, addr, b, 1, 0);
}
static inline int cts_sram_readw(const struct cts_device *cts_dev, u32 addr, u16 *w)
static inline int cts_sram_readw(const struct cts_device *cts_dev, u32 addr,
u16 *w)
{
return cts_sram_readw_retry(cts_dev, addr, w, 1, 0);
return cts_sram_readw_retry(cts_dev, addr, w, 1, 0);
}
static inline int cts_sram_readl(const struct cts_device *cts_dev, u32 addr, u32 *l)
static inline int cts_sram_readl(const struct cts_device *cts_dev, u32 addr,
u32 *l)
{
return cts_sram_readl_retry(cts_dev, addr, l, 1, 0);
return cts_sram_readl_retry(cts_dev, addr, l, 1, 0);
}
static inline int cts_sram_readsb(const struct cts_device *cts_dev,
u32 addr, void *dst, size_t len)
u32 addr, void *dst, size_t len)
{
return cts_sram_readsb_retry(cts_dev, addr, dst, len, 1, 0);
return cts_sram_readsb_retry(cts_dev, addr, dst, len, 1, 0);
}
#ifdef CONFIG_CTS_I2C_HOST
static inline void cts_set_program_addr(struct cts_device *cts_dev)
{
cts_dev->rtdata.slave_addr = CTS_DEV_PROGRAM_MODE_I2CADDR;
cts_dev->rtdata.program_mode = true;
cts_dev->rtdata.addr_width = CTS_DEV_PROGRAM_MODE_ADDR_WIDTH;
cts_dev->rtdata.slave_addr = CTS_DEV_PROGRAM_MODE_I2CADDR;
cts_dev->rtdata.program_mode = true;
cts_dev->rtdata.addr_width = CTS_DEV_PROGRAM_MODE_ADDR_WIDTH;
}
static inline void cts_set_normal_addr(struct cts_device *cts_dev)
{
cts_dev->rtdata.slave_addr = CTS_DEV_NORMAL_MODE_I2CADDR;
cts_dev->rtdata.program_mode = false;
cts_dev->rtdata.addr_width = CTS_DEV_NORMAL_MODE_ADDR_WIDTH;
cts_dev->rtdata.slave_addr = CTS_DEV_NORMAL_MODE_I2CADDR;
cts_dev->rtdata.program_mode = false;
cts_dev->rtdata.addr_width = CTS_DEV_NORMAL_MODE_ADDR_WIDTH;
}
#else
static inline void cts_set_program_addr(struct cts_device *cts_dev)
{
cts_dev->rtdata.slave_addr = CTS_DEV_PROGRAM_MODE_SPIADDR;
cts_dev->rtdata.program_mode = true;
cts_dev->rtdata.addr_width = CTS_DEV_PROGRAM_MODE_ADDR_WIDTH;
cts_dev->rtdata.slave_addr = CTS_DEV_PROGRAM_MODE_SPIADDR;
cts_dev->rtdata.program_mode = true;
cts_dev->rtdata.addr_width = CTS_DEV_PROGRAM_MODE_ADDR_WIDTH;
}
static inline void cts_set_normal_addr(struct cts_device *cts_dev)
{
cts_dev->rtdata.slave_addr = CTS_DEV_NORMAL_MODE_SPIADDR;
cts_dev->rtdata.program_mode = false;
cts_dev->rtdata.addr_width = CTS_DEV_NORMAL_MODE_ADDR_WIDTH;
cts_dev->rtdata.slave_addr = CTS_DEV_NORMAL_MODE_SPIADDR;
cts_dev->rtdata.program_mode = false;
cts_dev->rtdata.addr_width = CTS_DEV_NORMAL_MODE_ADDR_WIDTH;
}
#endif
extern int cts_irq_handler(struct cts_device *cts_dev);
extern void cts_firmware_upgrade_work(struct work_struct *work);
extern bool cts_is_device_suspended(const struct cts_device *cts_dev);
extern int cts_suspend_device(struct cts_device *cts_dev);
@ -516,18 +554,22 @@ extern int cts_enter_normal_mode(struct cts_device *cts_dev);
extern int cts_probe_device(struct cts_device *cts_dev);
extern int cts_set_work_mode(const struct cts_device *cts_dev, u8 mode);
extern int cts_get_work_mode(const struct cts_device *cts_dev, u8 *mode);
extern int cts_get_firmware_version(const struct cts_device *cts_dev, u16 *version);
extern int cts_get_firmware_version(const struct cts_device *cts_dev,
u16 *version);
extern int cts_get_ddi_version(const struct cts_device *cts_dev, u8 *version);
extern int cts_get_lib_version(const struct cts_device *cts_dev, u16 *lib_version);
extern int cts_get_lib_version(const struct cts_device *cts_dev,
u16 *lib_version);
extern int cts_get_data_ready_flag(const struct cts_device *cts_dev, u8 *flag);
extern int cts_clr_data_ready_flag(const struct cts_device *cts_dev);
extern int cts_send_command(const struct cts_device *cts_dev, u8 cmd);
extern int cts_get_panel_param(const struct cts_device *cts_dev,
void *param, size_t size);
void *param, size_t size);
extern int cts_set_panel_param(const struct cts_device *cts_dev,
const void *param, size_t size);
extern int cts_get_x_resolution(const struct cts_device *cts_dev, u16 *resolution);
extern int cts_get_y_resolution(const struct cts_device *cts_dev, u16 *resolution);
const void *param, size_t size);
extern int cts_get_x_resolution(const struct cts_device *cts_dev,
u16 *resolution);
extern int cts_get_y_resolution(const struct cts_device *cts_dev,
u16 *resolution);
extern int cts_get_num_rows(const struct cts_device *cts_dev, u8 *num_rows);
extern int cts_get_num_cols(const struct cts_device *cts_dev, u8 *num_cols);
extern int cts_enable_get_rawdata(const struct cts_device *cts_dev);
@ -544,8 +586,8 @@ extern int cts_get_hwid(struct cts_device *cts_dev, u32 *hwid);
extern void cts_enable_gesture_wakeup(struct cts_device *cts_dev);
extern void cts_disable_gesture_wakeup(struct cts_device *cts_dev);
extern bool cts_is_gesture_wakeup_enabled(const struct cts_device *cts_dev);
extern int cts_get_gesture_info(const struct cts_device *cts_dev,
void *gesture_info, bool trace_point);
extern int cts_get_gesture_info(const struct cts_device *cts_dev,
void *gesture_info, bool trace_point);
#endif /* CFG_CTS_GESTURE */
#ifdef CONFIG_CTS_ESD_PROTECTION
@ -554,10 +596,21 @@ extern void cts_enable_esd_protection(struct chipone_ts_data *cts_data);
extern void cts_disable_esd_protection(struct chipone_ts_data *cts_data);
extern void cts_deinit_esd_protection(struct chipone_ts_data *cts_data);
#else /* CONFIG_CTS_ESD_PROTECTION */
static inline void cts_init_esd_protection(struct chipone_ts_data *cts_data) {}
static inline void cts_enable_esd_protection(struct chipone_ts_data *cts_data) {}
static inline void cts_disable_esd_protection(struct chipone_ts_data *cts_data) {}
static inline void cts_deinit_esd_protection(struct chipone_ts_data *cts_data) {}
static inline void cts_init_esd_protection(struct chipone_ts_data *cts_data)
{
}
static inline void cts_enable_esd_protection(struct chipone_ts_data *cts_data)
{
}
static inline void cts_disable_esd_protection(struct chipone_ts_data *cts_data)
{
}
static inline void cts_deinit_esd_protection(struct chipone_ts_data *cts_data)
{
}
#endif /* CONFIG_CTS_ESD_PROTECTION */
#ifdef CONFIG_CTS_GLOVE
@ -565,9 +618,20 @@ extern int cts_enter_glove_mode(struct cts_device *cts_dev);
extern int cts_exit_glove_mode(struct cts_device *cts_dev);
int cts_is_glove_enabled(const struct cts_device *cts_dev);
#else
static inline int cts_enter_glove_mode(struct cts_device *cts_dev) {return 0;}
static inline int cts_exit_glove_mode(struct cts_device *cts_dev) {return 0;}
static inline int cts_is_glove_enabled(const struct cts_device *cts_dev) {return 0;}
static inline int cts_enter_glove_mode(struct cts_device *cts_dev)
{
return 0;
}
static inline int cts_exit_glove_mode(struct cts_device *cts_dev)
{
return 0;
}
static inline int cts_is_glove_enabled(const struct cts_device *cts_dev)
{
return 0;
}
#endif
#ifdef CONFIG_CTS_CHARGER_DETECT
@ -575,17 +639,34 @@ extern bool cts_is_charger_exist(struct cts_device *cts_dev);
extern int cts_charger_plugin(struct cts_device *cts_dev);
extern int cts_charger_plugout(struct cts_device *cts_dev);
#else /* CONFIG_CTS_CHARGER_DETECT */
static inline bool cts_is_charger_exist(struct cts_device *cts_dev) {return false;}
static inline int cts_charger_plugin(struct cts_device *cts_dev) {return 0;}
static inline int cts_charger_plugout(struct cts_device *cts_dev) {return 0;}
static inline bool cts_is_charger_exist(struct cts_device *cts_dev)
{
return false;
}
static inline int cts_charger_plugin(struct cts_device *cts_dev)
{
return 0;
}
static inline int cts_charger_plugout(struct cts_device *cts_dev)
{
return 0;
}
#endif /* CONFIG_CTS_CHARGER_DETECT */
#ifdef CONFIG_CTS_LEGACY_TOOL
extern int cts_tool_init(struct chipone_ts_data *cts_data);
extern int cts_tool_init(struct chipone_ts_data *cts_data);
extern void cts_tool_deinit(struct chipone_ts_data *data);
#else /* CONFIG_CTS_LEGACY_TOOL */
static inline int cts_tool_init(struct chipone_ts_data *cts_data) {return 0;}
static inline void cts_tool_deinit(struct chipone_ts_data *data) {}
static inline int cts_tool_init(struct chipone_ts_data *cts_data)
{
return 0;
}
static inline void cts_tool_deinit(struct chipone_ts_data *data)
{
}
#endif /* CONFIG_CTS_LEGACY_TOOL */
extern bool cts_is_device_enabled(const struct cts_device *cts_dev);
@ -601,11 +682,10 @@ extern int cts_fw_log_show_finish(struct cts_device *cts_dev);
#ifdef CFG_CTS_UPDATE_CRCCHECK
extern int cts_sram_writesb_boot_crc_retry(const struct cts_device *cts_dev,
size_t len, u32 crc, int retry);
size_t len, u32 crc, int retry);
#endif
extern const char *cts_dev_boot_mode2str(u8 boot_mode);
extern bool cts_is_fwid_valid(u16 fwid);
#endif /* CTS_CORE_H */

1984
drivers/input/touchscreen/chipone_tddi_mmi/cts_firmware.c Executable file → Normal file
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117
drivers/input/touchscreen/chipone_tddi_mmi/cts_firmware.h Executable file → Normal file
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@ -1,49 +1,68 @@
#ifndef CTS_FIRMWARE_H
#define CTS_FIRMWARE_H
#include "cts_config.h"
struct cts_firmware {
const char *name; /* MUST set to non-NULL if driver builtin firmware */
u32 hwid;
u16 fwid;
u8 *data;
size_t size;
};
#define FIRMWARE_VERSION_OFFSET 0x100
#define FIRMWARE_VERSION(firmware) \
get_unaligned_le16((firmware)->data + FIRMWARE_VERSION_OFFSET)
struct cts_device;
extern const struct cts_firmware *cts_request_firmware(
u32 hwid, u16 fwid, u16 device_fw_ver);
extern void cts_release_firmware(const struct cts_firmware *firmware);
#ifdef CFG_CTS_DRIVER_BUILTIN_FIRMWARE
extern int cts_get_num_driver_builtin_firmware(void);
extern const struct cts_firmware *cts_request_driver_builtin_firmware_by_name(const char *name);
extern const struct cts_firmware *cts_request_driver_builtin_firmware_by_index(u32 index);
#else /* CFG_CTS_DRIVER_BUILTIN_FIRMWARE */
static inline int cts_get_num_driver_builtin_firmware(void) {return 0;}
static inline const struct cts_firmware *cts_request_driver_builtin_firmware_by_name(const char *name) {return NULL;}
static inline const struct cts_firmware *cts_request_driver_builtin_firmware_by_index(u32 index) {return NULL;}
#endif /* CFG_CTS_DRIVER_BUILTIN_FIRMWARE */
extern bool cts_is_firmware_updating(const struct cts_device *cts_dev);
extern int cts_update_firmware(struct cts_device *cts_dev,
const struct cts_firmware *firmware, bool to_flash);
#ifdef CFG_CTS_FIRMWARE_IN_FS
extern const struct cts_firmware *cts_request_firmware_from_fs(const char *filepath);
extern int cts_update_firmware_from_file(
struct cts_device *cts_dev, const char *filepath, bool to_flash);
#endif /* CFG_CTS_FIRMWARE_IN_FS */
extern u32 crc32(const u8 *data, size_t len);
#endif /* CTS_FIRMWARE_H */
#ifndef CTS_FIRMWARE_H
#define CTS_FIRMWARE_H
#include "cts_config.h"
#include <linux/firmware.h>
struct cts_firmware {
const char *name; /* MUST set to non-NULL if driver builtin firmware */
u32 hwid;
u16 fwid;
u8 *data;
size_t size;
const struct firmware *fw;
};
#define FIRMWARE_VERSION_OFFSET 0x100
#define FIRMWARE_VERSION(firmware) \
get_unaligned_le16((firmware)->data + FIRMWARE_VERSION_OFFSET)
struct cts_device;
extern const struct cts_firmware *cts_request_firmware(
const struct cts_device *cts_dev,
u32 hwid, u16 fwid, u16 device_fw_ver);
extern void cts_release_firmware(const struct cts_firmware *firmware);
#ifdef CFG_CTS_DRIVER_BUILTIN_FIRMWARE
extern int cts_get_num_driver_builtin_firmware(void);
extern const struct cts_firmware
*cts_request_driver_builtin_firmware_by_name(const char *name);
extern const struct cts_firmware
*cts_request_driver_builtin_firmware_by_index(u32 index);
#else /* CFG_CTS_DRIVER_BUILTIN_FIRMWARE */
static inline int cts_get_num_driver_builtin_firmware(void)
{
return 0;
}
static inline const struct cts_firmware
*cts_request_driver_builtin_firmware_by_name(const char *name)
{
return NULL;
}
static inline const struct cts_firmware
*cts_request_driver_builtin_firmware_by_index(u32 index)
{
return NULL;
}
#endif /* CFG_CTS_DRIVER_BUILTIN_FIRMWARE */
extern bool cts_is_firmware_updating(const struct cts_device *cts_dev);
extern int cts_update_firmware(struct cts_device *cts_dev,
const struct cts_firmware *firmware,
bool to_flash);
#ifdef CFG_CTS_FIRMWARE_IN_FS
extern const struct cts_firmware *cts_request_firmware_from_fs(
const struct cts_device *cts_dev, const char *filepath);
extern int cts_update_firmware_from_file(struct cts_device *cts_dev,
const char *filepath, bool to_flash);
#endif /* CFG_CTS_FIRMWARE_IN_FS */
extern u32 crc32(const u8 *data, size_t len);
#endif /* CTS_FIRMWARE_H */

753
drivers/input/touchscreen/chipone_tddi_mmi/cts_i2c_driver.c Executable file → Normal file
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103
drivers/input/touchscreen/chipone_tddi_mmi/cts_plat_qcom_config.h Executable file → Normal file
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@ -1,50 +1,53 @@
#ifndef CTS_PLAT_QCOM_CONFIG_H
#define CTS_PLAT_QCOM_CONFIG_H
#define CONFIG_CTS_PM_FB_NOTIFIER
#ifdef CONFIG_CTS_PM_FB_NOTIFIER
#ifdef CONFIG_DRM
#define CFG_CTS_DRM_NOTIFIER
#endif/*CONFIG_DRM_MSM*/
#else/*CONFIG_CTS_PM_FB_NOTIFIER*/
#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_PM_SUSPEND)
//#define CONFIG_CTS_PM_GENERIC
#endif /* CONFIG_PM_SLEEP */
#if !defined(CONFIG_CTS_PM_GENERIC)
#define CONFIG_CTS_PM_LEGACY
#endif/*CONFIG_CTS_PM_GENERIC*/
#endif/*CONFIG_CTS_PM_FB_NOTIFIER*/
#define CFG_CTS_MAX_I2C_XFER_SIZE (48u)
#define CFG_CTS_MAX_SPI_XFER_SIZE (1400u)
#define CTS_FW_LOG_REDIRECT_SIGN 0x60
#define CTS_FW_LOG_BUF_LEN 128
//#define CFG_CTS_SWAP_XY
//#define CFG_CTS_WRAP_X
//#define CFG_CTS_WRAP_Y
#define CFG_CTS_DEVICE_NAME "chipone-tddi"
#define CFG_CTS_DRIVER_NAME "chipone-tddi"
#if CFG_CTS_MAX_I2C_XFER_SIZE < 8
#error "I2C transfer size should large than 8"
#endif
#ifdef CONFIG_OF
#define CONFIG_CTS_OF
#endif
#ifdef CONFIG_CTS_OF
#define CFG_CTS_OF_DEVICE_ID_NAME "chipone-tddi"
#define CFG_CTS_OF_INT_GPIO_NAME "chipone,irq-gpio"
#define CFG_CTS_OF_RST_GPIO_NAME "chipone,rst-gpio"
#define CFG_CTS_OF_X_RESOLUTION_NAME "chipone,x-res"
#define CFG_CTS_OF_Y_RESOLUTION_NAME "chipone,y-res"
#endif /* CONFIG_CTS_OF */
#endif /* CTS_PLAT_QCOM_CONFIG_H */
#ifndef CTS_PLAT_QCOM_CONFIG_H
#define CTS_PLAT_QCOM_CONFIG_H
#define CONFIG_CTS_PM_FB_NOTIFIER
#ifdef CONFIG_CTS_PM_FB_NOTIFIER
#ifdef CONFIG_DRM
#define CFG_CTS_DRM_NOTIFIER
#endif /*CONFIG_DRM_MSM */
#else /*CONFIG_CTS_PM_FB_NOTIFIER */
#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_PM_SUSPEND)
//#define CONFIG_CTS_PM_GENERIC
#endif /* CONFIG_PM_SLEEP */
#if !defined(CONFIG_CTS_PM_GENERIC)
#define CONFIG_CTS_PM_LEGACY
#endif /*CONFIG_CTS_PM_GENERIC */
#endif /*CONFIG_CTS_PM_FB_NOTIFIER */
#define CFG_CTS_MAX_I2C_XFER_SIZE (48u)
#define CFG_CTS_MAX_SPI_XFER_SIZE (1400u)
#define CTS_FW_LOG_REDIRECT_SIGN 0x60
#define CTS_FW_LOG_BUF_LEN 128
//#define CFG_CTS_SWAP_XY
//#define CFG_CTS_WRAP_X
//#define CFG_CTS_WRAP_Y
#define CFG_CTS_DEVICE_NAME "chipone-tddi"
#define CFG_CTS_DRIVER_NAME "chipone-tddi"
#if CFG_CTS_MAX_I2C_XFER_SIZE < 8
#error "I2C transfer size should large than 8"
#endif
#ifdef CONFIG_OF
#define CONFIG_CTS_OF
#endif
#ifdef CONFIG_CTS_OF
#define CFG_CTS_OF_DEVICE_ID_NAME "chipone-tddi"
#define CFG_CTS_OF_INT_GPIO_NAME "chipone,irq-gpio"
#define CFG_CTS_OF_RST_GPIO_NAME "chipone,rst-gpio"
#define CFG_CTS_OF_X_RESOLUTION_NAME "chipone,x-res"
#define CFG_CTS_OF_Y_RESOLUTION_NAME "chipone,y-res"
#ifdef CFG_CTS_FW_UPDATE_SYS
#define CFG_CTS_OF_PANEL_SUPPLIER "chipone,panel-supplier"
#endif
#endif /* CONFIG_CTS_OF */
#endif /* CTS_PLAT_QCOM_CONFIG_H */

1302
drivers/input/touchscreen/chipone_tddi_mmi/cts_platform.c Executable file → Normal file
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165
drivers/input/touchscreen/chipone_tddi_mmi/cts_platform.h Executable file → Normal file
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@ -60,105 +60,114 @@ extern bool cts_show_debug_log;
printk("<I>CTS-" LOG_TAG " " fmt"\n", ##__VA_ARGS__)
#define cts_dbg(fmt, ...) \
do { \
if (cts_show_debug_log) \
printk("<D>CTS-" LOG_TAG " "fmt"\n", ##__VA_ARGS__); \
} while(0)
if (cts_show_debug_log) \
printk("<D>CTS-" LOG_TAG " "fmt"\n", ##__VA_ARGS__); \
} while (0)
struct cts_device;
struct cts_device_touch_msg;
struct cts_device_gesture_info;
struct cts_platform_data {
int irq;
int int_gpio;
int irq;
int int_gpio;
#ifdef CFG_CTS_HAS_RESET_PIN
int rst_gpio;
#endif /* CFG_CTS_HAS_RESET_PIN */
int rst_gpio;
#endif /* CFG_CTS_HAS_RESET_PIN */
u32 res_x;
u32 res_y;
u32 res_x;
u32 res_y;
#ifdef CONFIG_CTS_VIRTUALKEY
u8 vkey_num;
u8 vkey_state;
u8 vkey_keycodes[CFG_CTS_MAX_VKEY_NUM];
#endif /* CONFIG_CTS_VIRTUALKEY */
u8 vkey_num;
u8 vkey_state;
u8 vkey_keycodes[CFG_CTS_MAX_VKEY_NUM];
#endif /* CONFIG_CTS_VIRTUALKEY */
struct cts_device *cts_dev;
#ifdef CFG_CTS_FW_UPDATE_SYS
const char *panel_supplier;
#endif
struct input_dev *ts_input_dev;
struct cts_device *cts_dev;
struct input_dev *ts_input_dev;
#ifndef CONFIG_GENERIC_HARDIRQS
struct work_struct ts_irq_work;
#endif /* CONFIG_GENERIC_HARDIRQS */
struct work_struct ts_irq_work;
#endif /* CONFIG_GENERIC_HARDIRQS */
struct rt_mutex dev_lock;
struct spinlock irq_lock;
bool irq_is_disable;
struct rt_mutex dev_lock;
struct spinlock irq_lock;
bool irq_is_disable;
#ifdef CFG_CTS_GESTURE
u8 gesture_num;
u8 gesture_keymap[CFG_CTS_NUM_GESTURE][2];
bool irq_wake_enabled;
#endif /* CFG_CTS_GESTURE */
u8 gesture_num;
u8 gesture_keymap[CFG_CTS_NUM_GESTURE][2];
bool irq_wake_enabled;
#endif /* CFG_CTS_GESTURE */
#ifdef CONFIG_CTS_PM_FB_NOTIFIER
struct notifier_block fb_notifier;
#endif /* CONFIG_CTS_PM_FB_NOTIFIER */
struct notifier_block fb_notifier;
#endif /* CONFIG_CTS_PM_FB_NOTIFIER */
#ifdef CFG_CTS_FORCE_UP
struct timer_list touch_event_timeout_timer;
struct delayed_work touch_event_timeout_work;
#endif
#ifdef CFG_CTS_FW_LOG_REDIRECT
u8 fw_log_buf[CTS_FW_LOG_BUF_LEN];
u8 fw_log_buf[CTS_FW_LOG_BUF_LEN];
#endif
#ifdef CONFIG_CTS_I2C_HOST
struct i2c_client *i2c_client;
u8 i2c_fifo_buf[CFG_CTS_MAX_I2C_XFER_SIZE];
struct i2c_client *i2c_client;
u8 i2c_fifo_buf[CFG_CTS_MAX_I2C_XFER_SIZE];
#else
struct spi_device *spi_client;
u8 spi_cache_buf[ALIGN(CFG_CTS_MAX_SPI_XFER_SIZE+10,4)];
u8 spi_rx_buf[ALIGN(CFG_CTS_MAX_SPI_XFER_SIZE+10,4)];
u8 spi_tx_buf[ALIGN(CFG_CTS_MAX_SPI_XFER_SIZE+10,4)];
u8 spi_cache_buf[ALIGN(CFG_CTS_MAX_SPI_XFER_SIZE + 10, 4)];
u8 spi_rx_buf[ALIGN(CFG_CTS_MAX_SPI_XFER_SIZE + 10, 4)];
u8 spi_tx_buf[ALIGN(CFG_CTS_MAX_SPI_XFER_SIZE + 10, 4)];
u32 spi_speed;
#endif /* CONFIG_CTS_I2C_HOST */
#endif /* CONFIG_CTS_I2C_HOST */
struct cts_device_touch_info touch_info;
struct cts_device_touch_info touch_info;
};
#ifdef CONFIG_CTS_I2C_HOST
extern size_t cts_plat_get_max_i2c_xfer_size(struct cts_platform_data *pdata);
extern u8 *cts_plat_get_i2c_xfer_buf(struct cts_platform_data *pdata,
size_t xfer_size);
size_t xfer_size);
extern int cts_plat_i2c_write(struct cts_platform_data *pdata, u8 i2c_addr,
const void *src, size_t len, int retry, int delay);
const void *src, size_t len, int retry,
int delay);
extern int cts_plat_i2c_read(struct cts_platform_data *pdata, u8 i2c_addr,
const u8 *wbuf, size_t wlen, void *rbuf, size_t rlen,
int retry, int delay);
const u8 *wbuf, size_t wlen, void *rbuf,
size_t rlen, int retry, int delay);
extern int cts_plat_is_i2c_online(struct cts_platform_data *pdata, u8 i2c_addr);
#else /* CONFIG_CTS_I2C_HOST */
extern size_t cts_plat_get_max_spi_xfer_size(struct cts_platform_data *pdata);
extern u8 *cts_plat_get_spi_xfer_buf(struct cts_platform_data *pdata, size_t xfer_size);
extern int cts_plat_spi_write(struct cts_platform_data *pdata, u8 i2c_addr, const void *src,
size_t len, int retry, int delay);
extern u8 *cts_plat_get_spi_xfer_buf(struct cts_platform_data *pdata,
size_t xfer_size);
extern int cts_plat_spi_write(struct cts_platform_data *pdata, u8 i2c_addr,
const void *src, size_t len, int retry,
int delay);
extern int cts_plat_spi_read(struct cts_platform_data *pdata, u8 i2c_addr,
const u8 *wbuf, size_t wlen, void *rbuf, size_t rlen,
int retry, int delay);
extern int cts_plat_spi_read_delay_idle(struct cts_platform_data *pdata, u8 dev_addr,
const u8 *wbuf, size_t wlen, void *rbuf, size_t rlen,
int retry, int delay, int idle);
extern int cts_spi_send_recv(struct cts_platform_data *pdata, size_t len , u8 *tx_buffer, u8 *rx_buffer);
const u8 *wbuf, size_t wlen, void *rbuf,
size_t rlen, int retry, int delay);
extern int cts_plat_spi_read_delay_idle(struct cts_platform_data *pdata,
u8 dev_addr, const u8 *wbuf,
size_t wlen, void *rbuf, size_t rlen,
int retry, int delay, int idle);
extern int cts_spi_send_recv(struct cts_platform_data *pdata, size_t len,
u8 *tx_buffer, u8 *rx_buffer);
#endif /* CONFIG_CTS_I2C_HOST */
#ifdef CONFIG_CTS_I2C_HOST
extern int cts_init_platform_data(struct cts_platform_data *pdata,
struct i2c_client *i2c_client);
struct i2c_client *i2c_client);
#else
extern int cts_plat_is_normal_mode(struct cts_platform_data *pdata);
extern int cts_init_platform_data(struct cts_platform_data *pdata,
struct spi_device *spi);
struct spi_device *spi);
#endif
extern int cts_deinit_platform_data(struct cts_platform_data *pdata);
@ -173,25 +182,45 @@ extern int cts_plat_disable_irq(struct cts_platform_data *pdata);
#ifdef CFG_CTS_HAS_RESET_PIN
extern int cts_plat_reset_device(struct cts_platform_data *pdata);
#else /* CFG_CTS_HAS_RESET_PIN */
static inline int cts_plat_reset_device(struct cts_platform_data *pdata) {return 0;}
static inline int cts_plat_reset_device(struct cts_platform_data *pdata)
{
return 0;
}
#endif /* CFG_CTS_HAS_RESET_PIN */
extern int cts_plat_init_touch_device(struct cts_platform_data *pdata);
extern void cts_plat_deinit_touch_device(struct cts_platform_data *pdata);
extern int cts_plat_process_touch_msg(struct cts_platform_data *pdata,
struct cts_device_touch_msg *msgs, int num);
struct cts_device_touch_msg *msgs,
int num);
extern int cts_plat_release_all_touch(struct cts_platform_data *pdata);
#ifdef CONFIG_CTS_VIRTUALKEY
extern int cts_plat_init_vkey_device(struct cts_platform_data *pdata);
extern void cts_plat_deinit_vkey_device(struct cts_platform_data *pdata);
extern int cts_plat_process_vkey(struct cts_platform_data *pdata, u8 vkey_state);
extern int cts_plat_process_vkey(struct cts_platform_data *pdata,
u8 vkey_state);
extern int cts_plat_release_all_vkey(struct cts_platform_data *pdata);
#else /* CONFIG_CTS_VIRTUALKEY */
static inline int cts_plat_init_vkey_device(struct cts_platform_data *pdata) {return 0;}
static inline void cts_plat_deinit_vkey_device(struct cts_platform_data *pdata) {}
static inline int cts_plat_process_vkey(struct cts_platform_data *pdata, u8 vkey_state) {return 0;}
static inline int cts_plat_release_all_vkey(struct cts_platform_data *pdata) {return 0;}
static inline int cts_plat_init_vkey_device(struct cts_platform_data *pdata)
{
return 0;
}
static inline void cts_plat_deinit_vkey_device(struct cts_platform_data *pdata)
{
}
static inline int cts_plat_process_vkey(struct cts_platform_data *pdata,
u8 vkey_state)
{
return 0;
}
static inline int cts_plat_release_all_vkey(struct cts_platform_data *pdata)
{
return 0;
}
#endif /* CONFIG_CTS_VIRTUALKEY */
#ifdef CFG_CTS_GESTURE
@ -201,17 +230,27 @@ extern int cts_plat_disable_irq_wake(struct cts_platform_data *pdata);
extern int cts_plat_init_gesture(struct cts_platform_data *pdata);
extern void cts_plat_deinit_gesture(struct cts_platform_data *pdata);
extern int cts_plat_process_gesture_info(struct cts_platform_data *pdata,
struct cts_device_gesture_info *gesture_info);
struct cts_device_gesture_info
*gesture_info);
#else /* CFG_CTS_GESTURE */
static inline int cts_plat_init_gesture(struct cts_platform_data *pdata) {return 0;}
static inline void cts_plat_deinit_gesture(struct cts_platform_data *pdata) {}
#endif /* CFG_CTS_GESTURE */
static inline int cts_plat_init_gesture(struct cts_platform_data *pdata)
{
return 0;
}
#endif /* CTS_PLATFORM_H */
static inline void cts_plat_deinit_gesture(struct cts_platform_data *pdata)
{
}
#endif /* CFG_CTS_GESTURE */
#ifdef CFG_CTS_FW_LOG_REDIRECT
extern size_t cts_plat_get_max_fw_log_size(struct cts_platform_data *pdata);
extern u8 *cts_plat_get_fw_log_buf(struct cts_platform_data *pdata, size_t size);
extern u8 *cts_plat_get_fw_log_buf(struct cts_platform_data *pdata,
size_t size);
#endif
extern int cts_plat_set_reset(struct cts_platform_data *pdata, int val);
extern int cts_plat_get_int_pin(struct cts_platform_data *pdata);
#endif /* CTS_PLATFORM_H */

77
drivers/input/touchscreen/chipone_tddi_mmi/cts_sfctrl.h Executable file → Normal file
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@ -1,39 +1,38 @@
#ifndef CTS_SFCTRL_H
#define CTS_SFCTRL_H
#include "cts_core.h"
#include "cts_spi_flash.h"
struct cts_device;
struct cts_sfctrl_ops {
int (*rdid)(const struct cts_device *cts_dev, u32 *id);
int (*se)(const struct cts_device *cts_dev, u32 sector_addr);
int (*be)(const struct cts_device *cts_dev, u32 sector_addr);
int (*read)(const struct cts_device *cts_dev,
u32 flash_addr, void *dst, size_t len);
int (*read_to_sram)(const struct cts_device *cts_dev,
u32 flash_addr, u32 sram_addr, size_t len);
int (*program)(const struct cts_device *cts_dev,
u32 flash_addr, const void *src, size_t len);
int (*program_from_sram)(const struct cts_device *cts_dev,
u32 flash_addr, u32 sram_addr, size_t len);
int (*calc_sram_crc)(const struct cts_device *cts_dev,
u32 sram_addr, size_t len, u32 *crc);
int (*calc_flash_crc)(const struct cts_device *cts_dev,
u32 flash_addr, size_t len, u32 *crc);
};
struct cts_sfctrl {
u32 reg_base;
u32 xchg_sram_base;
size_t xchg_sram_size;
const struct cts_sfctrl_ops *ops;
};
extern const struct cts_sfctrl_ops cts_sfctrlv2_ops;
#endif /* CTS_SFCTRL_H */
#ifndef CTS_SFCTRL_H
#define CTS_SFCTRL_H
#include "cts_core.h"
#include "cts_spi_flash.h"
struct cts_device;
struct cts_sfctrl_ops {
int (*rdid) (const struct cts_device *cts_dev, u32 *id);
int (*se) (const struct cts_device *cts_dev, u32 sector_addr);
int (*be) (const struct cts_device *cts_dev, u32 sector_addr);
int (*read) (const struct cts_device *cts_dev,
u32 flash_addr, void *dst, size_t len);
int (*read_to_sram) (const struct cts_device *cts_dev,
u32 flash_addr, u32 sram_addr, size_t len);
int (*program) (const struct cts_device *cts_dev,
u32 flash_addr, const void *src, size_t len);
int (*program_from_sram) (const struct cts_device *cts_dev,
u32 flash_addr, u32 sram_addr, size_t len);
int (*calc_sram_crc) (const struct cts_device *cts_dev,
u32 sram_addr, size_t len, u32 *crc);
int (*calc_flash_crc) (const struct cts_device *cts_dev,
u32 flash_addr, size_t len, u32 *crc);
};
struct cts_sfctrl {
u32 reg_base;
u32 xchg_sram_base;
size_t xchg_sram_size;
const struct cts_sfctrl_ops *ops;
};
extern const struct cts_sfctrl_ops cts_sfctrlv2_ops;
#endif /* CTS_SFCTRL_H */

680
drivers/input/touchscreen/chipone_tddi_mmi/cts_sfctrlv2.c Executable file → Normal file
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@ -1,333 +1,347 @@
#define LOG_TAG "SFCtrl"
#include "cts_config.h"
#include "cts_platform.h"
#include "cts_core.h"
#include "cts_sfctrl.h"
#define rSFCTRLv2_CMD_SEL (0x0000)
#define rSFCTRLv2_FLASH_ADDR (0x0004)
#define rSFCTRLv2_SRAM_ADDR (0x0008)
#define rSFCTRLv2_DATA_LENGTH (0x000C)
#define rSFCTRLv2_START_DEXC (0x0010)
#define rSFCTRLv2_RELEASE_FLASH (0x0014)
#define rSFCTRLv2_HW_STATE (0x0018)
#define rSFCTRLv2_CRC_RESULT (0x001C)
#define rSFCTRLv2_SRAM_CRC_START (0x0020)
#define rSFCTRLv2_FLASH_CRC_START (0x0022)
#define rSFCTRLv2_SF_BUSY (0x0024)
/** Constants for register @ref rSFCTRLv2_CMD_SEL */
enum sfctrlv2_cmd {
SFCTRLv2_CMD_FAST_READ = 0x01u,
SFCTRLv2_CMD_SE = 0x02u,
SFCTRLv2_CMD_BE = 0x03u,
SFCTRLv2_CMD_PP = 0x04u,
SFCTRLv2_CMD_RDSR = 0x05u,
SFCTRLv2_CMD_RDID = 0x06u
};
/** SPI flash controller v2 operation flags. */
enum sfctrlv2_opflags {
SFCTRLv2_OPFLAG_READ = BIT(0),
SFCTRLv2_OPFLAG_SET_FLASH_ADDR = BIT(1),
SFCTRLv2_OPFLAG_SRAM_DATA_XCHG = BIT(2),
SFCTRLv2_OPFLAG_SET_DATA_LENGTH = BIT(3),
SFCTRLv2_OPFLAG_WAIT_WIP_CLR = BIT(4),
};
#define SFCTRLv2_CMD_RDID_FLAGS \
(SFCTRLv2_OPFLAG_READ | \
SFCTRLv2_OPFLAG_SRAM_DATA_XCHG)
#define SFCTRLv2_CMD_RDSR_FLAGS \
(SFCTRLv2_OPFLAG_READ | \
SFCTRLv2_OPFLAG_SRAM_DATA_XCHG)
#define SFCTRLv2_CMD_SE_FLAGS \
(SFCTRLv2_OPFLAG_SET_FLASH_ADDR | \
SFCTRLv2_OPFLAG_WAIT_WIP_CLR)
#define SFCTRLv2_CMD_BE_FLAGS \
(SFCTRLv2_OPFLAG_SET_FLASH_ADDR | \
SFCTRLv2_OPFLAG_WAIT_WIP_CLR)
#define SFCTRLv2_CMD_PP_FLAGS \
(SFCTRLv2_OPFLAG_SET_FLASH_ADDR | \
SFCTRLv2_OPFLAG_SRAM_DATA_XCHG | \
SFCTRLv2_OPFLAG_SET_DATA_LENGTH | \
SFCTRLv2_OPFLAG_WAIT_WIP_CLR)
#define SFCTRLv2_CMD_FAST_READ_FLAGS \
(SFCTRLv2_OPFLAG_READ | \
SFCTRLv2_OPFLAG_SET_FLASH_ADDR | \
SFCTRLv2_OPFLAG_SRAM_DATA_XCHG | \
SFCTRLv2_OPFLAG_SET_DATA_LENGTH)
#define sfctrl_reg_addr(cts_dev, offset) \
((cts_dev)->hwdata->sfctrl->reg_base + offset)
#define DEFINE_SFCTRL_REG_ACCESS_FUNC(access_type, data_type) \
static inline int sfctrl_reg_ ## access_type(const struct cts_device *cts_dev, \
u32 reg, data_type data) { \
return cts_hw_reg_ ## access_type(cts_dev, sfctrl_reg_addr(cts_dev, reg), data); \
}
DEFINE_SFCTRL_REG_ACCESS_FUNC(writeb, u8)
DEFINE_SFCTRL_REG_ACCESS_FUNC(writew, u16)
DEFINE_SFCTRL_REG_ACCESS_FUNC(writel, u32)
DEFINE_SFCTRL_REG_ACCESS_FUNC(readb, u8 *)
DEFINE_SFCTRL_REG_ACCESS_FUNC(readw, u16 *)
DEFINE_SFCTRL_REG_ACCESS_FUNC(readl, u32 *)
#define sfctrl_write_reg_check_ret(access_type, reg, val) \
do { \
int ret; \
cts_dbg("Write " #reg " to 0x%x", val); \
ret = sfctrl_reg_ ## access_type(cts_dev, reg, val); \
if (ret) { \
cts_err("Write " #reg " failed %d", ret); \
return ret; \
} \
} while (0)
#define sfctrl_read_reg_check_ret(access_type, reg, val) \
do { \
int ret; \
cts_dbg("Read " #reg ""); \
ret = sfctrl_reg_ ## access_type(cts_dev, reg, val); \
if (ret) { \
cts_err("Read " #reg " failed %d", ret); \
return ret; \
} \
} while (0)
static int wait_sfctrl_xfer_comp(const struct cts_device *cts_dev)
{
int retries = 0;
u8 status;
do {
sfctrl_read_reg_check_ret(readb, rSFCTRLv2_SF_BUSY, &status);
if(status == 0) {
return 0;
}
mdelay(1);
} while(status && retries++ < 1000);
return -ETIMEDOUT;
}
static int sfctrlv2_rdsr(const struct cts_device *cts_dev, u8 *status)
{
#define RDSR_XCHG_SRAM_ADDR (cts_dev->hwdata->sram_size - 1)
int ret;
sfctrl_write_reg_check_ret(writeb, rSFCTRLv2_CMD_SEL, SFCTRLv2_CMD_RDSR);
sfctrl_write_reg_check_ret(writel, rSFCTRLv2_SRAM_ADDR, RDSR_XCHG_SRAM_ADDR);
sfctrl_write_reg_check_ret(writeb, rSFCTRLv2_START_DEXC, 1);
if((ret = wait_sfctrl_xfer_comp(cts_dev)) != 0) {
cts_err("Wait sfctrl ready failed %d", ret);
return ret;
}
ret = cts_sram_readb(cts_dev, RDSR_XCHG_SRAM_ADDR, status);
if (ret) {
cts_err("Read exchange sram failed %d", ret);
return ret;
}
#undef RDSR_XCHG_SRAM_ADDR
return 0;
}
static int wait_flash_wip_clear(const struct cts_device *cts_dev)
{
#define FLASH_SR_WIP BIT(0) /*!< Write in progress */
int ret, retries = 0;
u8 status;
do {
ret = sfctrlv2_rdsr(cts_dev, &status);
if (ret) {
cts_err("Read flash status register failed %d", ret);
return ret;
}
if (status & FLASH_SR_WIP) {
mdelay(1);
} else {
return 0;
}
} while (status & FLASH_SR_WIP && retries++ < 1000);
return -ETIMEDOUT;
#undef FLASH_SR_WIP
}
static int sfctrlv2_transfer(const struct cts_device *cts_dev,
u8 cmd, void *data, u32 flash_addr, u32 sram_addr, size_t size, u32 flags)
{
int ret;
sfctrl_write_reg_check_ret(writeb, rSFCTRLv2_CMD_SEL, cmd);
if (flags & SFCTRLv2_OPFLAG_SRAM_DATA_XCHG) {
sfctrl_write_reg_check_ret(writel, rSFCTRLv2_SRAM_ADDR, sram_addr);
/** - Write data to exchange SRAM if operation is write and
* data != NULL(data not in SRAM) */
if ((!(flags & SFCTRLv2_OPFLAG_READ)) && data) {
ret = cts_sram_writesb(cts_dev, sram_addr, data, size);
if (ret) {
cts_err("Write data to exchange sram 0x%06x size %zu failed %d",
sram_addr, size, ret);
return ret;
}
}
}
if (flags & SFCTRLv2_OPFLAG_SET_FLASH_ADDR) {
sfctrl_write_reg_check_ret(writel, rSFCTRLv2_FLASH_ADDR, flash_addr);
}
if (flags & SFCTRLv2_OPFLAG_SET_DATA_LENGTH) {
sfctrl_write_reg_check_ret(writel, rSFCTRLv2_DATA_LENGTH, (u32)size);
}
sfctrl_write_reg_check_ret(writeb, rSFCTRLv2_START_DEXC, 1);
if((ret = wait_sfctrl_xfer_comp(cts_dev)) != 0) {
cts_err("Wait sfctrl ready failed %d", ret);
return ret;
}
if (flags & SFCTRLv2_OPFLAG_WAIT_WIP_CLR &&
(ret = wait_flash_wip_clear(cts_dev)) != 0) {
cts_err("Wait WIP clear failed %d", ret);
return ret;
}
if ((flags & SFCTRLv2_OPFLAG_READ) && data) {
ret = cts_sram_readsb(cts_dev, sram_addr, data, size);
if (ret) {
cts_err("Read data from exchange sram 0x%06x size %zu failed %d",
sram_addr, size, ret);
return ret;
}
}
return 0;
}
static int sfctrlv2_rdid(const struct cts_device *cts_dev, u32 *id)
{
int ret;
u8 buf[4];
ret = sfctrlv2_transfer(cts_dev, SFCTRLv2_CMD_RDID, buf,
0, cts_dev->hwdata->sfctrl->xchg_sram_base, 3,
SFCTRLv2_CMD_RDID_FLAGS);
*id = ret ? 0 : get_unaligned_be24(buf);
return ret;
}
static int sfctrlv2_se(const struct cts_device *cts_dev, u32 sector_addr)
{
return sfctrlv2_transfer(cts_dev, SFCTRLv2_CMD_SE, NULL,
sector_addr, 0, 0, SFCTRLv2_CMD_SE_FLAGS);
}
static int sfctrlv2_be(const struct cts_device *cts_dev, u32 block_addr)
{
return sfctrlv2_transfer(cts_dev, SFCTRLv2_CMD_BE, NULL,
block_addr, 0, 0, SFCTRLv2_CMD_BE_FLAGS);
}
static int sfctrlv2_pp(const struct cts_device *cts_dev,
u32 flash_addr, const void *src, size_t size)
{
return sfctrlv2_transfer(cts_dev, SFCTRLv2_CMD_PP, (void *)src,
flash_addr, cts_dev->hwdata->sfctrl->xchg_sram_base, size,
SFCTRLv2_CMD_PP_FLAGS);
}
static int sfctrlv2_program_flash_from_sram(const struct cts_device *cts_dev,
u32 flash_addr, u32 sram_addr, size_t len)
{
return sfctrlv2_transfer(cts_dev, SFCTRLv2_CMD_PP, NULL,
flash_addr, sram_addr, len, SFCTRLv2_CMD_PP_FLAGS);
}
static int sfctrlv2_read(const struct cts_device *cts_dev,
u32 flash_addr, void *dst, size_t size)
{
return sfctrlv2_transfer(cts_dev, SFCTRLv2_CMD_FAST_READ, dst,
flash_addr, cts_dev->hwdata->sfctrl->xchg_sram_base, size,
SFCTRLv2_CMD_FAST_READ_FLAGS);
}
static int sfctrlv2_read_flash_to_sram(const struct cts_device *cts_dev,
u32 flash_addr, u32 sram_addr, size_t size)
{
return sfctrlv2_transfer(cts_dev, SFCTRLv2_CMD_FAST_READ, NULL,
flash_addr, sram_addr, size, SFCTRLv2_CMD_FAST_READ_FLAGS);
}
int sfctrlv2_calc_sram_crc(const struct cts_device *cts_dev,
u32 sram_addr, size_t size, u32 *crc)
{
int ret;
sfctrl_write_reg_check_ret(writel, rSFCTRLv2_SRAM_ADDR, sram_addr);
sfctrl_write_reg_check_ret(writel, rSFCTRLv2_DATA_LENGTH, (u32)size);
sfctrl_write_reg_check_ret(writeb, rSFCTRLv2_SRAM_CRC_START, 1);
if((ret = wait_sfctrl_xfer_comp(cts_dev)) != 0) {
cts_err("Wait sfctrl ready failed %d", ret);
return ret;
}
sfctrl_read_reg_check_ret(readl, rSFCTRLv2_CRC_RESULT, crc);
return 0;
}
int sfctrlv2_calc_flash_crc(const struct cts_device *cts_dev,
u32 flash_addr, size_t size, u32 *crc)
{
int ret;
cts_info("Calc crc from flash 0x%06x size %zu", flash_addr, size);
sfctrl_write_reg_check_ret(writel, rSFCTRLv2_FLASH_ADDR, flash_addr);
sfctrl_write_reg_check_ret(writel, rSFCTRLv2_DATA_LENGTH, (u32)size);
sfctrl_write_reg_check_ret(writeb, rSFCTRLv2_FLASH_CRC_START, 1);
if((ret = wait_sfctrl_xfer_comp(cts_dev)) != 0) {
cts_err("Wait sfctrl ready failed %d", ret);
return ret;
}
sfctrl_read_reg_check_ret(readl, rSFCTRLv2_CRC_RESULT, crc);
return 0;
}
const struct cts_sfctrl_ops cts_sfctrlv2_ops = {
.rdid = sfctrlv2_rdid,
.se = sfctrlv2_se,
.be = sfctrlv2_be,
.read = sfctrlv2_read,
.read_to_sram = sfctrlv2_read_flash_to_sram,
.program = sfctrlv2_pp,
.program_from_sram = sfctrlv2_program_flash_from_sram,
.calc_sram_crc = sfctrlv2_calc_sram_crc,
.calc_flash_crc = sfctrlv2_calc_flash_crc,
};
#define LOG_TAG "SFCtrl"
#include "cts_config.h"
#include "cts_platform.h"
#include "cts_core.h"
#include "cts_sfctrl.h"
#define rSFCTRLv2_CMD_SEL (0x0000)
#define rSFCTRLv2_FLASH_ADDR (0x0004)
#define rSFCTRLv2_SRAM_ADDR (0x0008)
#define rSFCTRLv2_DATA_LENGTH (0x000C)
#define rSFCTRLv2_START_DEXC (0x0010)
#define rSFCTRLv2_RELEASE_FLASH (0x0014)
#define rSFCTRLv2_HW_STATE (0x0018)
#define rSFCTRLv2_CRC_RESULT (0x001C)
#define rSFCTRLv2_SRAM_CRC_START (0x0020)
#define rSFCTRLv2_FLASH_CRC_START (0x0022)
#define rSFCTRLv2_SF_BUSY (0x0024)
/** Constants for register @ref rSFCTRLv2_CMD_SEL */
enum sfctrlv2_cmd {
SFCTRLv2_CMD_FAST_READ = 0x01u,
SFCTRLv2_CMD_SE = 0x02u,
SFCTRLv2_CMD_BE = 0x03u,
SFCTRLv2_CMD_PP = 0x04u,
SFCTRLv2_CMD_RDSR = 0x05u,
SFCTRLv2_CMD_RDID = 0x06u
};
/** SPI flash controller v2 operation flags. */
enum sfctrlv2_opflags {
SFCTRLv2_OPFLAG_READ = BIT(0),
SFCTRLv2_OPFLAG_SET_FLASH_ADDR = BIT(1),
SFCTRLv2_OPFLAG_SRAM_DATA_XCHG = BIT(2),
SFCTRLv2_OPFLAG_SET_DATA_LENGTH = BIT(3),
SFCTRLv2_OPFLAG_WAIT_WIP_CLR = BIT(4),
};
#define SFCTRLv2_CMD_RDID_FLAGS \
(SFCTRLv2_OPFLAG_READ | \
SFCTRLv2_OPFLAG_SRAM_DATA_XCHG)
#define SFCTRLv2_CMD_RDSR_FLAGS \
(SFCTRLv2_OPFLAG_READ | \
SFCTRLv2_OPFLAG_SRAM_DATA_XCHG)
#define SFCTRLv2_CMD_SE_FLAGS \
(SFCTRLv2_OPFLAG_SET_FLASH_ADDR | \
SFCTRLv2_OPFLAG_WAIT_WIP_CLR)
#define SFCTRLv2_CMD_BE_FLAGS \
(SFCTRLv2_OPFLAG_SET_FLASH_ADDR | \
SFCTRLv2_OPFLAG_WAIT_WIP_CLR)
#define SFCTRLv2_CMD_PP_FLAGS \
(SFCTRLv2_OPFLAG_SET_FLASH_ADDR | \
SFCTRLv2_OPFLAG_SRAM_DATA_XCHG | \
SFCTRLv2_OPFLAG_SET_DATA_LENGTH | \
SFCTRLv2_OPFLAG_WAIT_WIP_CLR)
#define SFCTRLv2_CMD_FAST_READ_FLAGS \
(SFCTRLv2_OPFLAG_READ | \
SFCTRLv2_OPFLAG_SET_FLASH_ADDR | \
SFCTRLv2_OPFLAG_SRAM_DATA_XCHG | \
SFCTRLv2_OPFLAG_SET_DATA_LENGTH)
#define sfctrl_reg_addr(cts_dev, offset) \
((cts_dev)->hwdata->sfctrl->reg_base + offset)
#define DEFINE_SFCTRL_REG_ACCESS_FUNC(access_type, data_type) \
static inline int sfctrl_reg_ ## access_type(const struct cts_device *cts_dev, \
u32 reg, data_type data) { \
return cts_hw_reg_ ## access_type(cts_dev, sfctrl_reg_addr(cts_dev, reg), data); \
}
DEFINE_SFCTRL_REG_ACCESS_FUNC(writeb_relaxed, u8)
DEFINE_SFCTRL_REG_ACCESS_FUNC(writew_relaxed, u16)
DEFINE_SFCTRL_REG_ACCESS_FUNC(writel_relaxed, u32)
DEFINE_SFCTRL_REG_ACCESS_FUNC(readb_relaxed, u8 *)
DEFINE_SFCTRL_REG_ACCESS_FUNC(readw_relaxed, u16 *)
DEFINE_SFCTRL_REG_ACCESS_FUNC(readl_relaxed, u32 *)
#define sfctrl_write_reg_check_ret(access_type, reg, val) \
do { \
int ret; \
cts_dbg("Write " #reg " to 0x%x", val); \
ret = sfctrl_reg_ ## access_type(cts_dev, reg, val); \
if (ret) { \
cts_err("Write " #reg " failed %d", ret); \
return ret; \
} \
} while (0)
#define sfctrl_read_reg_check_ret(access_type, reg, val) \
do { \
int ret; \
cts_dbg("Read " #reg ""); \
ret = sfctrl_reg_ ## access_type(cts_dev, reg, val); \
if (ret) { \
cts_err("Read " #reg " failed %d", ret); \
return ret; \
} \
} while (0)
static int wait_sfctrl_xfer_comp(const struct cts_device *cts_dev)
{
int retries = 0;
u8 status;
do {
sfctrl_read_reg_check_ret(readb_relaxed, rSFCTRLv2_SF_BUSY, &status);
if (status == 0) {
return 0;
}
mdelay(1);
} while (status && retries++ < 1000);
return -ETIMEDOUT;
}
static int sfctrlv2_rdsr(const struct cts_device *cts_dev, u8 *status)
{
#define RDSR_XCHG_SRAM_ADDR (cts_dev->hwdata->sram_size - 1)
int ret;
sfctrl_write_reg_check_ret(writeb_relaxed, rSFCTRLv2_CMD_SEL,
SFCTRLv2_CMD_RDSR);
sfctrl_write_reg_check_ret(writel_relaxed, rSFCTRLv2_SRAM_ADDR,
RDSR_XCHG_SRAM_ADDR);
sfctrl_write_reg_check_ret(writeb_relaxed, rSFCTRLv2_START_DEXC, 1);
ret = wait_sfctrl_xfer_comp(cts_dev);
if (ret != 0) {
cts_err("Wait sfctrl ready failed %d", ret);
return ret;
}
ret = cts_sram_readb(cts_dev, RDSR_XCHG_SRAM_ADDR, status);
if (ret) {
cts_err("Read exchange sram failed %d", ret);
return ret;
}
#undef RDSR_XCHG_SRAM_ADDR
return 0;
}
static int wait_flash_wip_clear(const struct cts_device *cts_dev)
{
#define FLASH_SR_WIP BIT(0) /*!< Write in progress */
int ret, retries = 0;
u8 status;
do {
ret = sfctrlv2_rdsr(cts_dev, &status);
if (ret) {
cts_err("Read flash status register failed %d", ret);
return ret;
}
if (status & FLASH_SR_WIP) {
mdelay(1);
} else {
return 0;
}
} while (status & FLASH_SR_WIP && retries++ < 1000);
return -ETIMEDOUT;
#undef FLASH_SR_WIP
}
static int sfctrlv2_transfer(const struct cts_device *cts_dev,
u8 cmd, void *data, u32 flash_addr, u32 sram_addr,
size_t size, u32 flags)
{
int ret;
sfctrl_write_reg_check_ret(writeb_relaxed, rSFCTRLv2_CMD_SEL, cmd);
if (flags & SFCTRLv2_OPFLAG_SRAM_DATA_XCHG) {
sfctrl_write_reg_check_ret(writel_relaxed, rSFCTRLv2_SRAM_ADDR,
sram_addr);
/** - Write data to exchange SRAM if operation is write and
* data != NULL(data not in SRAM) */
if ((!(flags & SFCTRLv2_OPFLAG_READ)) && data) {
ret = cts_sram_writesb(cts_dev, sram_addr, data, size);
if (ret) {
cts_err
("Write data to exchange sram 0x%06x size %zu failed %d",
sram_addr, size, ret);
return ret;
}
}
}
if (flags & SFCTRLv2_OPFLAG_SET_FLASH_ADDR) {
sfctrl_write_reg_check_ret(writel_relaxed, rSFCTRLv2_FLASH_ADDR,
flash_addr);
}
if (flags & SFCTRLv2_OPFLAG_SET_DATA_LENGTH) {
sfctrl_write_reg_check_ret(writel_relaxed, rSFCTRLv2_DATA_LENGTH,
(u32) size);
}
sfctrl_write_reg_check_ret(writeb_relaxed, rSFCTRLv2_START_DEXC, 1);
ret = wait_sfctrl_xfer_comp(cts_dev);
if (ret != 0) {
cts_err("Wait sfctrl ready failed %d", ret);
return ret;
}
ret = wait_flash_wip_clear(cts_dev);
if (flags & SFCTRLv2_OPFLAG_WAIT_WIP_CLR && ret != 0) {
cts_err("Wait WIP clear failed %d", ret);
return ret;
}
if ((flags & SFCTRLv2_OPFLAG_READ) && data) {
ret = cts_sram_readsb(cts_dev, sram_addr, data, size);
if (ret) {
cts_err
("Read data from exchange sram 0x%06x size %zu failed %d",
sram_addr, size, ret);
return ret;
}
}
return 0;
}
static int sfctrlv2_rdid(const struct cts_device *cts_dev, u32 *id)
{
int ret;
u8 buf[4];
ret = sfctrlv2_transfer(cts_dev, SFCTRLv2_CMD_RDID, buf,
0, cts_dev->hwdata->sfctrl->xchg_sram_base, 3,
SFCTRLv2_CMD_RDID_FLAGS);
*id = ret ? 0 : get_unaligned_be24(buf);
return ret;
}
static int sfctrlv2_se(const struct cts_device *cts_dev, u32 sector_addr)
{
return sfctrlv2_transfer(cts_dev, SFCTRLv2_CMD_SE, NULL,
sector_addr, 0, 0, SFCTRLv2_CMD_SE_FLAGS);
}
static int sfctrlv2_be(const struct cts_device *cts_dev, u32 block_addr)
{
return sfctrlv2_transfer(cts_dev, SFCTRLv2_CMD_BE, NULL,
block_addr, 0, 0, SFCTRLv2_CMD_BE_FLAGS);
}
static int sfctrlv2_pp(const struct cts_device *cts_dev,
u32 flash_addr, const void *src, size_t size)
{
return sfctrlv2_transfer(cts_dev, SFCTRLv2_CMD_PP, (void *)src,
flash_addr,
cts_dev->hwdata->sfctrl->xchg_sram_base, size,
SFCTRLv2_CMD_PP_FLAGS);
}
static int sfctrlv2_program_flash_from_sram(const struct cts_device *cts_dev,
u32 flash_addr, u32 sram_addr,
size_t len)
{
return sfctrlv2_transfer(cts_dev, SFCTRLv2_CMD_PP, NULL,
flash_addr, sram_addr, len,
SFCTRLv2_CMD_PP_FLAGS);
}
static int sfctrlv2_read(const struct cts_device *cts_dev,
u32 flash_addr, void *dst, size_t size)
{
return sfctrlv2_transfer(cts_dev, SFCTRLv2_CMD_FAST_READ, dst,
flash_addr,
cts_dev->hwdata->sfctrl->xchg_sram_base, size,
SFCTRLv2_CMD_FAST_READ_FLAGS);
}
static int sfctrlv2_read_flash_to_sram(const struct cts_device *cts_dev,
u32 flash_addr, u32 sram_addr,
size_t size)
{
return sfctrlv2_transfer(cts_dev, SFCTRLv2_CMD_FAST_READ, NULL,
flash_addr, sram_addr, size,
SFCTRLv2_CMD_FAST_READ_FLAGS);
}
int sfctrlv2_calc_sram_crc(const struct cts_device *cts_dev,
u32 sram_addr, size_t size, u32 *crc)
{
int ret;
sfctrl_write_reg_check_ret(writel_relaxed, rSFCTRLv2_SRAM_ADDR, sram_addr);
sfctrl_write_reg_check_ret(writel_relaxed, rSFCTRLv2_DATA_LENGTH, (u32) size);
sfctrl_write_reg_check_ret(writeb_relaxed, rSFCTRLv2_SRAM_CRC_START, 1);
ret = wait_sfctrl_xfer_comp(cts_dev);
if (ret != 0) {
cts_err("Wait sfctrl ready failed %d", ret);
return ret;
}
sfctrl_read_reg_check_ret(readl_relaxed, rSFCTRLv2_CRC_RESULT, crc);
return 0;
}
int sfctrlv2_calc_flash_crc(const struct cts_device *cts_dev,
u32 flash_addr, size_t size, u32 *crc)
{
int ret;
cts_info("Calc crc from flash 0x%06x size %zu", flash_addr, size);
sfctrl_write_reg_check_ret(writel_relaxed, rSFCTRLv2_FLASH_ADDR, flash_addr);
sfctrl_write_reg_check_ret(writel_relaxed, rSFCTRLv2_DATA_LENGTH, (u32) size);
sfctrl_write_reg_check_ret(writeb_relaxed, rSFCTRLv2_FLASH_CRC_START, 1);
ret = wait_sfctrl_xfer_comp(cts_dev);
if (ret != 0) {
cts_err("Wait sfctrl ready failed %d", ret);
return ret;
}
sfctrl_read_reg_check_ret(readl_relaxed, rSFCTRLv2_CRC_RESULT, crc);
return 0;
}
const struct cts_sfctrl_ops cts_sfctrlv2_ops = {
.rdid = sfctrlv2_rdid,
.se = sfctrlv2_se,
.be = sfctrlv2_be,
.read = sfctrlv2_read,
.read_to_sram = sfctrlv2_read_flash_to_sram,
.program = sfctrlv2_pp,
.program_from_sram = sfctrlv2_program_flash_from_sram,
.calc_sram_crc = sfctrlv2_calc_sram_crc,
.calc_flash_crc = sfctrlv2_calc_flash_crc,
};

1217
drivers/input/touchscreen/chipone_tddi_mmi/cts_spi_flash.c Executable file → Normal file
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62
drivers/input/touchscreen/chipone_tddi_mmi/cts_spi_flash.h Executable file → Normal file
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@ -2,13 +2,13 @@
#define CTS_SPI_FLASH_H
struct cts_flash {
const char *name;
u32 jedec_id; /* Device ID by command 0x9F */
size_t page_size; /* Page size by command 0x02 */
size_t sector_size; /* Sector size by command 0x20 */
size_t block_size; /* Block size by command 0x52,
if 0 means block erase NOT supported */
size_t total_size;
const char *name;
u32 jedec_id; /* Device ID by command 0x9F */
size_t page_size; /* Page size by command 0x02 */
size_t sector_size; /* Sector size by command 0x20 */
size_t block_size; /* Block size by command 0x52,
if 0 means block erase NOT supported */
size_t total_size;
};
@ -21,38 +21,50 @@ extern int cts_prepare_flash_operation(struct cts_device *cts_dev);
extern int cts_post_flash_operation(struct cts_device *cts_dev);
extern int cts_read_flash_retry(const struct cts_device *cts_dev,
u32 flash_addr, void *dst, size_t size, int retry);
u32 flash_addr, void *dst, size_t size,
int retry);
static inline int cts_read_flash(const struct cts_device *cts_dev,
u32 flash_addr, void *dst, size_t size)
u32 flash_addr, void *dst, size_t size)
{
return cts_read_flash_retry(cts_dev,
flash_addr, dst, size, CTS_FLASH_READ_DEFAULT_RETRY);
return cts_read_flash_retry(cts_dev,
flash_addr, dst, size,
CTS_FLASH_READ_DEFAULT_RETRY);
}
extern int cts_read_flash_to_sram_retry(const struct cts_device *cts_dev,
u32 flash_addr, u32 sram_addr, size_t size, int retry);
u32 flash_addr, u32 sram_addr,
size_t size, int retry);
static inline int cts_read_flash_to_sram(const struct cts_device *cts_dev,
u32 flash_addr, u32 sram_addr, size_t size)
u32 flash_addr, u32 sram_addr,
size_t size)
{
return cts_read_flash_to_sram_retry(cts_dev,
flash_addr, sram_addr, size, CTS_FLASH_READ_DEFAULT_RETRY);
return cts_read_flash_to_sram_retry(cts_dev,
flash_addr, sram_addr, size,
CTS_FLASH_READ_DEFAULT_RETRY);
}
extern int cts_read_flash_to_sram_check_crc_retry(const struct cts_device *cts_dev,
u32 flash_addr, u32 sram_addr, size_t size, u32 crc, int retry);
static inline int cts_read_flash_to_sram_check_crc(const struct cts_device *cts_dev,
u32 flash_addr, u32 sram_addr, size_t size, u32 crc)
extern int cts_read_flash_to_sram_check_crc_retry(const struct cts_device
*cts_dev, u32 flash_addr,
u32 sram_addr, size_t size,
u32 crc, int retry);
static inline int cts_read_flash_to_sram_check_crc(const struct cts_device
*cts_dev, u32 flash_addr,
u32 sram_addr, size_t size,
u32 crc)
{
return cts_read_flash_to_sram_check_crc_retry(cts_dev,
flash_addr, sram_addr, size, crc, CTS_FLASH_READ_DEFAULT_RETRY);
return cts_read_flash_to_sram_check_crc_retry(cts_dev,
flash_addr, sram_addr,
size, crc,
CTS_FLASH_READ_DEFAULT_RETRY);
}
extern int cts_erase_flash(const struct cts_device *cts_dev, u32 addr, size_t size);
extern int cts_erase_flash(const struct cts_device *cts_dev, u32 addr,
size_t size);
extern int cts_program_flash(const struct cts_device *cts_dev,
u32 flash_addr, const void *src, size_t size);
u32 flash_addr, const void *src, size_t size);
extern int cts_program_flash_from_sram(const struct cts_device *cts_dev,
u32 flash_addr, u32 sram_addr, size_t size);
u32 flash_addr, u32 sram_addr,
size_t size);
#endif /* CTS_SPI_FLASH_H */

4766
drivers/input/touchscreen/chipone_tddi_mmi/cts_sysfs.c Executable file → Normal file
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41
drivers/input/touchscreen/chipone_tddi_mmi/cts_sysfs.h Executable file → Normal file
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@ -1,17 +1,24 @@
#ifndef CTS_SYSFS_H
#define CTS_SYSFS_H
#include "cts_config.h"
struct device;
#ifdef CONFIG_CTS_SYSFS
extern int cts_sysfs_add_device(struct device *dev);
extern void cts_sysfs_remove_device(struct device *dev);
#else /* CONFIG_CTS_SYSFS */
static inline int cts_sysfs_add_device(struct device *dev) {return -ENOTSUPP;}
static inline void cts_sysfs_remove_device(struct device *dev) {}
#endif /* CONFIG_CTS_SYSFS */
#endif /* CTS_SYSFS_H */
#ifndef CTS_SYSFS_H
#define CTS_SYSFS_H
#include "cts_config.h"
struct device;
extern u16 speed;
#ifdef CONFIG_CTS_SYSFS
extern int cts_sysfs_add_device(struct device *dev);
extern void cts_sysfs_remove_device(struct device *dev);
#else /* CONFIG_CTS_SYSFS */
static inline int cts_sysfs_add_device(struct device *dev)
{
return -ENOTSUPP;
}
static inline void cts_sysfs_remove_device(struct device *dev)
{
}
#endif /* CONFIG_CTS_SYSFS */
#endif /* CTS_SYSFS_H */

2451
drivers/input/touchscreen/chipone_tddi_mmi/cts_test.c Executable file → Normal file
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29
drivers/input/touchscreen/chipone_tddi_mmi/cts_test.h Executable file → Normal file
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@ -1,13 +1,16 @@
#ifndef CTS_TEST_H
#define CTS_TEST_H
struct cts_device;
extern int cts_short_test(struct cts_device *cts_dev, u16 threshold);
extern int cts_open_test(struct cts_device *cts_dev, u16 threshold);
extern int cts_reset_test(struct cts_device *cts_dev);
extern int cts_compensate_cap_test(struct cts_device *cts_dev, u8 min_thres, u8 max_thres);
extern int cts_rawdata_test(struct cts_device *cts_dev, u16 min_thres, u16 max_thres);
#endif /* CTS_TEST_H */
#ifndef CTS_TEST_H
#define CTS_TEST_H
struct cts_device;
extern int cts_short_test(struct cts_device *cts_dev, u16 threshold);
extern int cts_open_test(struct cts_device *cts_dev, u16 threshold);
extern int cts_reset_test(struct cts_device *cts_dev);
extern int cts_compensate_cap_test(struct cts_device *cts_dev, u8 min_thres,
u8 max_thres);
extern int cts_rawdata_test(struct cts_device *cts_dev, u16 min_thres,
u16 max_thres);
extern int cts_noise_test(struct cts_device *cts_dev, u32 frames, u16 max);
extern int cts_test_int_pin(struct cts_device *cts_dev);
#endif /* CTS_TEST_H */

1045
drivers/input/touchscreen/chipone_tddi_mmi/cts_tool.c Executable file → Normal file
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