From d30308cbb14f97b83cb66955cfee9c7501442b54 Mon Sep 17 00:00:00 2001
From: "Tao,Zhang" <taozha@qti.qualcomm.com>
Date: Wed, 12 Aug 2020 16:22:17 +0800
Subject: [PATCH] ARM: dts: msm: Add CTI config for ETB and ETR for shima

Add CTI flush and reset config to coresight device tree for ETR
and ETB for shima.

Change-Id: I607545e0085ffafae123129ce83e772a403e1475
---
 qcom/shima-coresight.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/qcom/shima-coresight.dtsi b/qcom/shima-coresight.dtsi
index 12c2d5480587..74d196646886 100644
--- a/qcom/shima-coresight.dtsi
+++ b/qcom/shima-coresight.dtsi
@@ -107,6 +107,7 @@
 
 		coresight-name = "coresight-tmc-etf";
 		coresight-csr = <&swao_csr>;
+		coresight-ctis = <&cti0_swao &cti3_swao>;
 		clocks = <&aopcc QDSS_CLK>;
 		clock-names = "apb_pclk";
 
@@ -153,7 +154,7 @@
 
 		qcom,sw-usb;
 		coresight-name = "coresight-tmc-etr";
-		coresight-ctis = <&cti0 &cti0>;
+		coresight-ctis = <&cti0 &cti3_swao>;
 		coresight-csr = <&csr>;
 
 		clocks = <&aopcc QDSS_CLK>;