From b2cdc0d7907dd66c1f72d2688ea0a5a91fdf3162 Mon Sep 17 00:00:00 2001 From: Puranam V G Tejaswi Date: Thu, 19 Nov 2020 00:18:49 +0530 Subject: [PATCH 1/4] msm: kgsl: Don't deassert GBIF halt for non-GMU targets During adreno_stop, GBIF halt is asserted to halt any new transaction from GPU before GPU power collapse, but in current code it is cleared immediately which can allow few GPU transactions to go through before gdsc is turned-off and can result in issues. To avoid this situation don't deassert this halt before GPU gdsc goes off. It will deassert automatically when gdsc goes off but in case gdsc doesn't toggle as it is a shared resource, it is deasserted during adreno_start to ensure wake-up doesn't fail. Change-Id: If0a892470d04a0f3a79a1ea882ee5bfd16ad24ed Signed-off-by: Puranam V G Tejaswi --- drivers/gpu/msm/adreno_a6xx_gmu.c | 10 ++++++---- drivers/gpu/msm/adreno_a6xx_hwsched.c | 2 ++ 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.c b/drivers/gpu/msm/adreno_a6xx_gmu.c index 1ae6d4488b3d..f90d7f2d51e6 100644 --- a/drivers/gpu/msm/adreno_a6xx_gmu.c +++ b/drivers/gpu/msm/adreno_a6xx_gmu.c @@ -1626,6 +1626,8 @@ static void a6xx_gmu_pwrctrl_suspend(struct adreno_device *adreno_dev) } /* Halt CX traffic */ a6xx_halt_gbif(adreno_dev); + /* De-assert the halts */ + kgsl_regwrite(device, A6XX_GBIF_HALT, 0x0); } if (a6xx_gmu_gx_is_on(device)) @@ -2764,9 +2766,6 @@ int a6xx_halt_gbif(struct adreno_device *adreno_dev) ret = adreno_wait_for_halt_ack(device, A6XX_GBIF_HALT_ACK, A6XX_GBIF_ARB_HALT_MASK); - /* De-assert the halts */ - kgsl_regwrite(device, A6XX_GBIF_HALT, 0x0); - return ret; } @@ -2797,8 +2796,11 @@ static int a6xx_gmu_power_off(struct adreno_device *adreno_dev) a6xx_rdpm_mx_freq_update(gmu, 0); /* Now that we are done with GMU and GPU, Clear the GBIF */ - if (!adreno_is_a630(adreno_dev)) + if (!adreno_is_a630(adreno_dev)) { ret = a6xx_halt_gbif(adreno_dev); + /* De-assert the halts */ + kgsl_regwrite(device, A6XX_GBIF_HALT, 0x0); + } a6xx_gmu_irq_disable(adreno_dev); diff --git a/drivers/gpu/msm/adreno_a6xx_hwsched.c b/drivers/gpu/msm/adreno_a6xx_hwsched.c index f83b63497408..8f40f625a3bc 100644 --- a/drivers/gpu/msm/adreno_a6xx_hwsched.c +++ b/drivers/gpu/msm/adreno_a6xx_hwsched.c @@ -373,6 +373,8 @@ static int a6xx_hwsched_gmu_power_off(struct adreno_device *adreno_dev) /* Now that we are done with GMU and GPU, Clear the GBIF */ ret = a6xx_halt_gbif(adreno_dev); + /* De-assert the halts */ + kgsl_regwrite(device, A6XX_GBIF_HALT, 0x0); a6xx_gmu_irq_disable(adreno_dev); From 8e0b5e5aaa55b260435af28e68ab16a090237871 Mon Sep 17 00:00:00 2001 From: Puranam V G Tejaswi Date: Thu, 19 Nov 2020 00:33:34 +0530 Subject: [PATCH 2/4] msm: kgsl: Move deassert_gbif_halt to a6xx specific space deassert_gbif_halt is needed only for the a6xx targets that use clear_pending_transactions. So move deassert_gbif_halt to a6xx specific space. This helps to provide some clarity and avoid gmu and gbif related checks. Change-Id: If46fa22a54737c2dbc35205318ed75ead351760a Signed-off-by: Puranam V G Tejaswi --- drivers/gpu/msm/adreno.c | 12 ------------ drivers/gpu/msm/adreno.h | 18 ------------------ drivers/gpu/msm/adreno_a6xx.c | 28 +++++++++++++++++++++++++--- 3 files changed, 25 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c index 13923ee66d8f..c29293a5d840 100644 --- a/drivers/gpu/msm/adreno.c +++ b/drivers/gpu/msm/adreno.c @@ -2031,18 +2031,6 @@ static int _adreno_start(struct adreno_device *adreno_dev) if (regulator_left_on) _soft_reset(adreno_dev); - /* - * During adreno_stop, GBIF halt is asserted to ensure - * no further transaction can go through GPU before GPU - * headswitch is turned off. - * - * This halt is deasserted once headswitch goes off but - * incase headswitch doesn't goes off clear GBIF halt - * here to ensure GPU wake-up doesn't fail because of - * halted GPU transactions. - */ - adreno_deassert_gbif_halt(adreno_dev); - adreno_ringbuffer_set_global(adreno_dev, 0); status = kgsl_mmu_start(device); diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h index 6189f810d439..22874c25f99c 100644 --- a/drivers/gpu/msm/adreno.h +++ b/drivers/gpu/msm/adreno.h @@ -696,9 +696,7 @@ enum adreno_regs { ADRENO_REG_RBBM_PERFCTR_RBBM_0_HI, ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_LO, ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_HI, - ADRENO_REG_GBIF_HALT, ADRENO_REG_VBIF_VERSION, - ADRENO_REG_RBBM_GBIF_HALT, ADRENO_REG_GMU_AO_HOST_INTERRUPT_MASK, ADRENO_REG_GMU_AHB_FENCE_STATUS, ADRENO_REG_GMU_GMU2HOST_INTR_MASK, @@ -1692,22 +1690,6 @@ static inline int adreno_wait_for_halt_ack(struct kgsl_device *device, return 0; } -static inline void adreno_deassert_gbif_halt(struct adreno_device *adreno_dev) -{ - if (adreno_has_gbif(adreno_dev)) { - adreno_writereg(adreno_dev, ADRENO_REG_GBIF_HALT, 0x0); - - /* - * Release GBIF GX halt. For A615 family, GPU GX halt - * will be cleared automatically on reset. - */ - if (!gmu_core_gpmu_isenabled(KGSL_DEVICE(adreno_dev)) && - !adreno_is_a615_family(adreno_dev)) - adreno_writereg(adreno_dev, - ADRENO_REG_RBBM_GBIF_HALT, 0x0); - } -} - /** * adreno_move_preempt_state - Update the preemption state * @adreno_dev: An Adreno GPU device handle diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c index 4b796166b1a9..4f950a8fd498 100644 --- a/drivers/gpu/msm/adreno_a6xx.c +++ b/drivers/gpu/msm/adreno_a6xx.c @@ -426,6 +426,18 @@ static void a6xx_set_secvid(struct kgsl_device *device) set = true; } +static void a6xx_deassert_gbif_halt(struct adreno_device *adreno_dev) +{ + struct kgsl_device *device = KGSL_DEVICE(adreno_dev); + + kgsl_regwrite(device, A6XX_GBIF_HALT, 0x0); + + if (adreno_is_a619_holi(adreno_dev)) + kgsl_regwrite(device, A6XX_RBBM_GPR0_CNTL, 0x0); + else + kgsl_regwrite(device, A6XX_RBBM_GBIF_HALT, 0x0); +} + /* * Some targets support marking certain transactions as always privileged which * allows us to mark more memory as privileged without having to explicitly set @@ -696,6 +708,19 @@ void a6xx_start(struct adreno_device *adreno_dev) a6xx_patch_pwrup_reglist(adreno_dev); patch_reglist = true; } + + /* + * During adreno_stop, GBIF halt is asserted to ensure + * no further transaction can go through GPU before GPU + * headswitch is turned off. + * + * This halt is deasserted once headswitch goes off but + * incase headswitch doesn't goes off clear GBIF halt + * here to ensure GPU wake-up doesn't fail because of + * halted GPU transactions. + */ + a6xx_deassert_gbif_halt(adreno_dev); + } /* Offsets into the MX/CX mapped register regions */ @@ -2300,9 +2325,6 @@ static unsigned int a6xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_HI, A6XX_RBBM_PERFCTR_LOAD_VALUE_HI), ADRENO_REG_DEFINE(ADRENO_REG_VBIF_VERSION, A6XX_VBIF_VERSION), - ADRENO_REG_DEFINE(ADRENO_REG_RBBM_GBIF_HALT, - A6XX_RBBM_GBIF_HALT), - ADRENO_REG_DEFINE(ADRENO_REG_GBIF_HALT, A6XX_GBIF_HALT), ADRENO_REG_DEFINE(ADRENO_REG_GMU_AO_HOST_INTERRUPT_MASK, A6XX_GMU_AO_HOST_INTERRUPT_MASK), ADRENO_REG_DEFINE(ADRENO_REG_GMU_AHB_FENCE_STATUS, From f021cc3c5d2dfa692860b91be74f3f629193ebba Mon Sep 17 00:00:00 2001 From: Puranam V G Tejaswi Date: Wed, 18 Nov 2020 23:22:44 +0530 Subject: [PATCH 3/4] msm: kgsl: Halt GBIF before moving to NAP state It has been observed that without gmu_clk, any active transactions will cause that transaction to be stuck in QSMMU. As of now we don't halt GBIF when moving to NAP state. So there is a possibility of transactions inflight when gmu_clk is gated. This will cause transactions to be stuck in QSMMU forever. This can eventually lead to GPU hang or TLB sync timeout. So halt GBIF before moving to NAP. Change-Id: I13bbe3b21b327d0d5c962bb2133c6d5d0f3a43c3 Signed-off-by: Puranam V G Tejaswi --- drivers/gpu/msm/adreno.c | 27 ++++++++++++++++++++++----- drivers/gpu/msm/adreno.h | 3 +-- drivers/gpu/msm/adreno_a6xx.c | 2 ++ drivers/gpu/msm/kgsl_device.h | 4 ++-- drivers/gpu/msm/kgsl_pwrctrl.c | 6 +++--- 5 files changed, 30 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c index c29293a5d840..510012f5c8aa 100644 --- a/drivers/gpu/msm/adreno.c +++ b/drivers/gpu/msm/adreno.c @@ -3505,7 +3505,7 @@ static int adreno_regulator_enable(struct kgsl_device *device) return ret; } -static bool adreno_is_hw_collapsible(struct kgsl_device *device) +static bool adreno_prepare_for_power_off(struct kgsl_device *device) { struct adreno_device *adreno_dev = ADRENO_DEVICE(device); const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); @@ -3519,8 +3519,16 @@ static bool adreno_is_hw_collapsible(struct kgsl_device *device) device->pwrctrl.ctrl_flags) return false; - return adreno_isidle(adreno_dev) && (gpudev->is_sptp_idle ? - gpudev->is_sptp_idle(adreno_dev) : true); + if (!adreno_isidle(adreno_dev) || !(gpudev->is_sptp_idle ? + gpudev->is_sptp_idle(adreno_dev) : true)) + return false; + + if (gpudev->clear_pending_transactions(adreno_dev)) + return false; + + adreno_dispatcher_stop_fault_timer(device); + + return true; } static void adreno_regulator_disable(struct kgsl_device *device) @@ -3727,6 +3735,15 @@ static int adreno_gpu_bus_set(struct kgsl_device *device, int level, u32 ab) return adreno_interconnect_bus_set(adreno_dev, level, ab); } +static void adreno_deassert_gbif_halt(struct kgsl_device *device) +{ + struct adreno_device *adreno_dev = ADRENO_DEVICE(device); + const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); + + if (gpudev->deassert_gbif_halt) + gpudev->deassert_gbif_halt(adreno_dev); +} + static const struct kgsl_functable adreno_functable = { /* Mandatory functions */ .regread = adreno_regread, @@ -3761,17 +3778,17 @@ static const struct kgsl_functable adreno_functable = { .drawctxt_sched = adreno_drawctxt_sched, .resume = adreno_dispatcher_start, .regulator_enable = adreno_regulator_enable, - .is_hw_collapsible = adreno_is_hw_collapsible, + .prepare_for_power_off = adreno_prepare_for_power_off, .regulator_disable = adreno_regulator_disable, .pwrlevel_change_settings = adreno_pwrlevel_change_settings, .regulator_disable_poll = adreno_regulator_disable_poll, .clk_set_options = adreno_clk_set_options, .gpu_model = adreno_gpu_model, - .stop_fault_timer = adreno_dispatcher_stop_fault_timer, .query_property_list = adreno_query_property_list, .is_hwcg_on = adreno_is_hwcg_on, .gpu_clock_set = adreno_gpu_clock_set, .gpu_bus_set = adreno_gpu_bus_set, + .deassert_gbif_halt = adreno_deassert_gbif_halt, }; static const struct component_master_ops adreno_ops = { diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h index 22874c25f99c..fbf8a12ff56d 100644 --- a/drivers/gpu/msm/adreno.h +++ b/drivers/gpu/msm/adreno.h @@ -811,6 +811,7 @@ struct adreno_gpudev { */ const struct adreno_power_ops *power_ops; int (*clear_pending_transactions)(struct adreno_device *adreno_dev); + void (*deassert_gbif_halt)(struct adreno_device *adreno_dev); }; /** @@ -1735,8 +1736,6 @@ static inline u32 adreno_get_level(u32 priority) int adreno_gmu_fenced_write(struct adreno_device *adreno_dev, enum adreno_regs offset, unsigned int val, unsigned int fence_mask); -int adreno_clear_pending_transactions(struct kgsl_device *device); - /** * adreno_get_firwmare - Load firmware into a adreno_firmware struct diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c index 4f950a8fd498..fb4497cfc82d 100644 --- a/drivers/gpu/msm/adreno_a6xx.c +++ b/drivers/gpu/msm/adreno_a6xx.c @@ -2509,6 +2509,7 @@ const struct adreno_gpudev adreno_a6xx_gpudev = { .read_alwayson = a6xx_read_alwayson, .power_ops = &adreno_power_operations, .clear_pending_transactions = a6xx_clear_pending_transactions, + .deassert_gbif_halt = a6xx_deassert_gbif_halt, }; const struct adreno_gpudev adreno_a6xx_hwsched_gpudev = { @@ -2622,6 +2623,7 @@ const struct adreno_gpudev adreno_a619_holi_gpudev = { .read_alwayson = a6xx_read_alwayson, .power_ops = &adreno_power_operations, .clear_pending_transactions = a6xx_clear_pending_transactions, + .deassert_gbif_halt = a6xx_deassert_gbif_halt, }; const struct adreno_gpudev adreno_a630_gpudev = { diff --git a/drivers/gpu/msm/kgsl_device.h b/drivers/gpu/msm/kgsl_device.h index c68d4cac981f..544cabeb3890 100644 --- a/drivers/gpu/msm/kgsl_device.h +++ b/drivers/gpu/msm/kgsl_device.h @@ -148,7 +148,7 @@ struct kgsl_functable { struct kgsl_context *context); void (*resume)(struct kgsl_device *device); int (*regulator_enable)(struct kgsl_device *device); - bool (*is_hw_collapsible)(struct kgsl_device *device); + bool (*prepare_for_power_off)(struct kgsl_device *device); void (*regulator_disable)(struct kgsl_device *device); void (*pwrlevel_change_settings)(struct kgsl_device *device, unsigned int prelevel, unsigned int postlevel, bool post); @@ -157,7 +157,6 @@ struct kgsl_functable { const char *name, struct clk *clk, bool on); void (*gpu_model)(struct kgsl_device *device, char *str, size_t bufsz); - void (*stop_fault_timer)(struct kgsl_device *device); /** * @query_property_list: query the list of properties * supported by the device. If 'list' is NULL just return the total @@ -171,6 +170,7 @@ struct kgsl_functable { int (*gpu_clock_set)(struct kgsl_device *device, u32 pwrlevel); /** @gpu_bus_set: Target specific function to set gpu bandwidth */ int (*gpu_bus_set)(struct kgsl_device *device, int bus_level, u32 ab); + void (*deassert_gbif_halt)(struct kgsl_device *device); }; struct kgsl_ioctl { diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c index 88ac2285245e..28aba03c96af 100644 --- a/drivers/gpu/msm/kgsl_pwrctrl.c +++ b/drivers/gpu/msm/kgsl_pwrctrl.c @@ -1859,6 +1859,7 @@ static int _wake(struct kgsl_device *device) /* Turn on the core clocks */ kgsl_pwrctrl_clk(device, KGSL_PWRFLAGS_ON, KGSL_STATE_ACTIVE); + device->ftbl->deassert_gbif_halt(device); /* * No need to turn on/off irq here as it no longer affects * power collapse @@ -1943,12 +1944,11 @@ _nap(struct kgsl_device *device) { switch (device->state) { case KGSL_STATE_ACTIVE: - if (!device->ftbl->is_hw_collapsible(device)) { + if (!device->ftbl->prepare_for_power_off(device)) { kgsl_pwrctrl_request_state(device, KGSL_STATE_NONE); return -EBUSY; } - device->ftbl->stop_fault_timer(device); kgsl_pwrscale_midframe_timer_cancel(device); /* @@ -2006,7 +2006,7 @@ _slumber(struct kgsl_device *device) switch (device->state) { case KGSL_STATE_ACTIVE: - if (!device->ftbl->is_hw_collapsible(device)) { + if (!device->ftbl->prepare_for_power_off(device)) { kgsl_pwrctrl_request_state(device, KGSL_STATE_NONE); return -EBUSY; } From a18eecda80b92f2636d912245d5333820960de81 Mon Sep 17 00:00:00 2001 From: Puranam V G Tejaswi Date: Wed, 18 Nov 2020 11:49:38 +0530 Subject: [PATCH 4/4] msm: kgsl: Poll GDCSR for holi target to ensure CX collapse The regulator_is_enabled() API doesn't guarantee that CX gdsc has collapsed at hardware. There could be a vote on the GDSC from another subsystem like TZ. So poll the CX GDSCR register to ensure that CX has indeed collapsed. Change-Id: Ic07cde5ba3442689cb73b33fe57c3d4371cb9565 Signed-off-by: Puranam V G Tejaswi --- drivers/gpu/msm/adreno.c | 10 ++++------ drivers/gpu/msm/adreno.h | 1 + drivers/gpu/msm/adreno_a6xx.c | 34 ++++++++++++++++++++++++++++++++-- 3 files changed, 37 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c index 510012f5c8aa..1202b6ce928d 100644 --- a/drivers/gpu/msm/adreno.c +++ b/drivers/gpu/msm/adreno.c @@ -3567,17 +3567,15 @@ static void adreno_clk_set_options(struct kgsl_device *device, const char *name, static void adreno_regulator_disable_poll(struct kgsl_device *device) { struct kgsl_pwrctrl *pwr = &device->pwrctrl; + const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE( + ADRENO_DEVICE(device)); - /* Set the parent in retention voltage to disable CPR interrupts */ - kgsl_regulator_set_voltage(device->dev, pwr->gx_gdsc_parent, - pwr->gx_gdsc_parent_min_corner); + if (gpudev->regulator_disable_poll) + return gpudev->regulator_disable_poll(device); if (!kgsl_regulator_disable_wait(pwr->gx_gdsc, 200)) dev_err(device->dev, "Regulator vdd is stuck on\n"); - /* Remove the vote for the vdd parent supply */ - kgsl_regulator_set_voltage(device->dev, pwr->gx_gdsc_parent, 0); - if (!kgsl_regulator_disable_wait(pwr->cx_gdsc, 200)) dev_err(device->dev, "Regulator vddcx is stuck on\n"); } diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h index fbf8a12ff56d..c3e572b4cd49 100644 --- a/drivers/gpu/msm/adreno.h +++ b/drivers/gpu/msm/adreno.h @@ -812,6 +812,7 @@ struct adreno_gpudev { const struct adreno_power_ops *power_ops; int (*clear_pending_transactions)(struct adreno_device *adreno_dev); void (*deassert_gbif_halt)(struct adreno_device *adreno_dev); + void (*regulator_disable_poll)(struct kgsl_device *device); }; /** diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c index fb4497cfc82d..657758df39bd 100644 --- a/drivers/gpu/msm/adreno_a6xx.c +++ b/drivers/gpu/msm/adreno_a6xx.c @@ -17,6 +17,7 @@ #include "adreno_pm4types.h" #include "adreno_trace.h" #include "kgsl_trace.h" +#include "kgsl_util.h" /* IFPC & Preemption static powerup restore list */ static u32 a6xx_pwrup_reglist[] = { @@ -249,6 +250,7 @@ bool a6xx_cx_regulator_disable_wait(struct regulator *reg, { ktime_t tout = ktime_add_us(ktime_get(), timeout * 1000); unsigned int val; + struct adreno_device *adreno_dev = ADRENO_DEVICE(device); if (IS_ERR_OR_NULL(reg)) return true; @@ -256,13 +258,22 @@ bool a6xx_cx_regulator_disable_wait(struct regulator *reg, regulator_disable(reg); for (;;) { - gmu_core_regread(device, A6XX_GPU_CC_CX_GDSCR, &val); + if (adreno_is_a619_holi(adreno_dev)) + adreno_read_gmu_wrapper(adreno_dev, + A6XX_GPU_CC_CX_GDSCR, &val); + else + gmu_core_regread(device, A6XX_GPU_CC_CX_GDSCR, &val); if (!(val & BIT(31))) return true; if (ktime_compare(ktime_get(), tout) > 0) { - gmu_core_regread(device, A6XX_GPU_CC_CX_GDSCR, &val); + if (adreno_is_a619_holi(adreno_dev)) + adreno_read_gmu_wrapper(adreno_dev, + A6XX_GPU_CC_CX_GDSCR, &val); + else + gmu_core_regread(device, A6XX_GPU_CC_CX_GDSCR, + &val); return (!(val & BIT(31))); } @@ -2476,6 +2487,24 @@ u64 a6xx_read_alwayson(struct adreno_device *adreno_dev) return (((u64) hi) << 32) | lo; } +static void a619_holi_regulator_disable_poll(struct kgsl_device *device) +{ + struct kgsl_pwrctrl *pwr = &device->pwrctrl; + + /* Set the parent in retention voltage to disable CPR interrupts */ + kgsl_regulator_set_voltage(device->dev, pwr->gx_gdsc_parent, + pwr->gx_gdsc_parent_min_corner); + + if (!kgsl_regulator_disable_wait(pwr->gx_gdsc, 200)) + dev_err(device->dev, "Regulator vdd is stuck on\n"); + + /* Remove the vote for the vdd parent supply */ + kgsl_regulator_set_voltage(device->dev, pwr->gx_gdsc_parent, 0); + + if (!a6xx_cx_regulator_disable_wait(pwr->cx_gdsc, device, 200)) + dev_err(device->dev, "Regulator vddcx is stuck on\n"); +} + const struct adreno_gpudev adreno_a6xx_gpudev = { .reg_offsets = a6xx_register_offsets, .probe = a6xx_probe, @@ -2624,6 +2653,7 @@ const struct adreno_gpudev adreno_a619_holi_gpudev = { .power_ops = &adreno_power_operations, .clear_pending_transactions = a6xx_clear_pending_transactions, .deassert_gbif_halt = a6xx_deassert_gbif_halt, + .regulator_disable_poll = a619_holi_regulator_disable_poll, }; const struct adreno_gpudev adreno_a630_gpudev = {