From 70602d12d95b418c0195024f50f415239fa20f94 Mon Sep 17 00:00:00 2001
From: Jyothi Kumar Seerapu <jseerapu@qti.qualcomm.com>
Date: Mon, 19 Sep 2022 13:48:56 +0530
Subject: [PATCH] ARM: dts: qcom: Enable PCIe halt feature on sdxlemur

In sdxlemur, with PCIe halt feature disable, IPA has raised
some SMMU errors due to out of order of transactions.

So, enabled the PCIe halt feature to default, which is
PCIe write halt enable with 1MB and enable PCIe read halt.

Change-Id: I660b6bc16db3af05bdedc67ea28c92ee769166db
---
 qcom/sdxlemur-pcie.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi
index 437bac326385..05b1db8be5e1 100644
--- a/qcom/sdxlemur-pcie.dtsi
+++ b/qcom/sdxlemur-pcie.dtsi
@@ -115,7 +115,6 @@
 		qcom,slv-addr-space-size = <0x40000000>;
 		qcom,ep-latency = <10>;
 		qcom,num-parf-testbus-sel = <0xb9>;
-		qcom,pcie-halt-feature-dis;
 
 		qcom,pcie-phy-ver = <1108>;
 		qcom,phy-status-offset = <0x1214>;